root / hw / sun4m.c @ b8c18e4c
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 8b17de88 | blueswir1 | #include "scsi.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | d2c63fc1 | blueswir1 | |
40 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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41 | 420557e8 | bellard | |
42 | 36cd9210 | blueswir1 | /*
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43 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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44 | 36cd9210 | blueswir1 | *
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45 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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46 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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47 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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48 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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49 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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50 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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51 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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52 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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53 | 36cd9210 | blueswir1 | * SPARCstation 4
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54 | 36cd9210 | blueswir1 | *
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55 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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56 | 7d85892b | blueswir1 | *
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57 | 7d85892b | blueswir1 | * SPARCcenter 2000
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58 | 7d85892b | blueswir1 | * SPARCserver 1000
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59 | 7d85892b | blueswir1 | *
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60 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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61 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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62 | ee76f82e | blueswir1 | * SPARCstation SLC
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63 | ee76f82e | blueswir1 | * SPARCstation IPC
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64 | ee76f82e | blueswir1 | * SPARCstation ELC
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65 | ee76f82e | blueswir1 | * SPARCstation IPX
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66 | ee76f82e | blueswir1 | *
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67 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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68 | 36cd9210 | blueswir1 | */
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69 | 36cd9210 | blueswir1 | |
70 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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71 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...) \
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72 | b3a23197 | blueswir1 | do { printf("CPUIRQ: " fmt , ##args); } while (0) |
73 | b3a23197 | blueswir1 | #else
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74 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...)
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75 | b3a23197 | blueswir1 | #endif
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76 | b3a23197 | blueswir1 | |
77 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
78 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
79 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
80 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
81 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
82 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
83 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
84 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
85 | b8174937 | bellard | |
86 | ac2e9d66 | blueswir1 | // Control plane, 8-bit and 24-bit planes
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87 | ac2e9d66 | blueswir1 | #define TCX_SIZE (9 * 1024 * 1024) |
88 | ac2e9d66 | blueswir1 | |
89 | ba3c64fb | bellard | #define MAX_CPUS 16 |
90 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
91 | 420557e8 | bellard | |
92 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
93 | b4ed08e0 | blueswir1 | |
94 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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95 | 5dcb6b91 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
96 | 5dcb6b91 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
97 | 5dcb6b91 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
98 | 4c2485de | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
99 | 0019ad53 | blueswir1 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
100 | 7eb0c8e8 | blueswir1 | target_phys_addr_t ecc_base; |
101 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
102 | 36cd9210 | blueswir1 | long vram_size, nvram_size;
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103 | 6341fdcb | blueswir1 | // IRQ numbers are not PIL ones, but master interrupt controller
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104 | e3a79bca | blueswir1 | // register bit numbers
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105 | 1572a18c | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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106 | e42c20b4 | blueswir1 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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107 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
108 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
109 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
110 | e0353fe2 | blueswir1 | uint32_t intbit_to_level[32];
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111 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
112 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
113 | 36cd9210 | blueswir1 | }; |
114 | 36cd9210 | blueswir1 | |
115 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
116 | 7d85892b | blueswir1 | |
117 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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118 | 7d85892b | blueswir1 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
119 | 7d85892b | blueswir1 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
120 | 7d85892b | blueswir1 | target_phys_addr_t serial_base; |
121 | 7d85892b | blueswir1 | target_phys_addr_t espdma_base, esp_base; |
122 | 7d85892b | blueswir1 | target_phys_addr_t ledma_base, le_base; |
123 | 7d85892b | blueswir1 | target_phys_addr_t tcx_base; |
124 | 7d85892b | blueswir1 | target_phys_addr_t sbi_base; |
125 | 7d85892b | blueswir1 | unsigned long vram_size, nvram_size; |
126 | 7d85892b | blueswir1 | // IRQ numbers are not PIL ones, but SBI register bit numbers
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127 | 7d85892b | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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128 | 7d85892b | blueswir1 | int ser_irq, ms_kb_irq, me_irq;
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129 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
130 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
131 | 7d85892b | blueswir1 | uint32_t iounit_version; |
132 | 7d85892b | blueswir1 | uint64_t max_mem; |
133 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
134 | 7d85892b | blueswir1 | }; |
135 | 7d85892b | blueswir1 | |
136 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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137 | 8137cde8 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
138 | 8137cde8 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
139 | 8137cde8 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
140 | 8137cde8 | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
141 | 1572a18c | blueswir1 | target_phys_addr_t tcx_base, aux1_base; |
142 | 8137cde8 | blueswir1 | long vram_size, nvram_size;
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143 | 8137cde8 | blueswir1 | // IRQ numbers are not PIL ones, but master interrupt controller
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144 | 8137cde8 | blueswir1 | // register bit numbers
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145 | 1572a18c | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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146 | 1572a18c | blueswir1 | int ser_irq, ms_kb_irq, fd_irq, me_irq;
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147 | 8137cde8 | blueswir1 | uint8_t nvram_machine_id; |
148 | 8137cde8 | blueswir1 | uint16_t machine_id; |
149 | 8137cde8 | blueswir1 | uint32_t iommu_version; |
150 | 8137cde8 | blueswir1 | uint32_t intbit_to_level[32];
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151 | 8137cde8 | blueswir1 | uint64_t max_mem; |
152 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
153 | 8137cde8 | blueswir1 | }; |
154 | 8137cde8 | blueswir1 | |
155 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
156 | 6f7e9aec | bellard | { |
157 | 6f7e9aec | bellard | return 0; |
158 | 6f7e9aec | bellard | } |
159 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
160 | 6f7e9aec | bellard | { |
161 | 6f7e9aec | bellard | return 0; |
162 | 6f7e9aec | bellard | } |
163 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
164 | 6f7e9aec | bellard | { |
165 | 6f7e9aec | bellard | return 0; |
166 | 6f7e9aec | bellard | } |
167 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
168 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
169 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
170 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
171 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
172 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
173 | 6f7e9aec | bellard | void *opaque)
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174 | 6f7e9aec | bellard | { |
175 | 6f7e9aec | bellard | } |
176 | 6f7e9aec | bellard | |
177 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
178 | 81864572 | blueswir1 | { |
179 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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180 | 81864572 | blueswir1 | return 0; |
181 | 81864572 | blueswir1 | } |
182 | 81864572 | blueswir1 | |
183 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
184 | 6ef05b95 | blueswir1 | const char *boot_devices, ram_addr_t RAM_size, |
185 | f930d07e | blueswir1 | uint32_t kernel_size, |
186 | f930d07e | blueswir1 | int width, int height, int depth, |
187 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
188 | e80cfcfc | bellard | { |
189 | d2c63fc1 | blueswir1 | unsigned int i; |
190 | 66508601 | blueswir1 | uint32_t start, end; |
191 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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192 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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193 | d2c63fc1 | blueswir1 | |
194 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
195 | e80cfcfc | bellard | |
196 | 513f789f | blueswir1 | start = 0;
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197 | b6f479d3 | bellard | |
198 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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199 | 66508601 | blueswir1 | // Variable partition
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200 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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201 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
202 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
203 | 66508601 | blueswir1 | |
204 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
205 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
206 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
207 | d2c63fc1 | blueswir1 | |
208 | d2c63fc1 | blueswir1 | // End marker
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209 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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210 | 66508601 | blueswir1 | |
211 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
212 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
213 | 66508601 | blueswir1 | |
214 | 66508601 | blueswir1 | // free partition
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215 | 66508601 | blueswir1 | start = end; |
216 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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217 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
218 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
219 | 66508601 | blueswir1 | |
220 | 66508601 | blueswir1 | end = 0x1fd0;
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221 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
222 | d2c63fc1 | blueswir1 | |
223 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
224 | 905fdcb5 | blueswir1 | nvram_machine_id); |
225 | d2c63fc1 | blueswir1 | |
226 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
227 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
228 | e80cfcfc | bellard | } |
229 | e80cfcfc | bellard | |
230 | e80cfcfc | bellard | static void *slavio_intctl; |
231 | e80cfcfc | bellard | |
232 | 376253ec | aliguori | void pic_info(Monitor *mon)
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233 | e80cfcfc | bellard | { |
234 | 7d85892b | blueswir1 | if (slavio_intctl)
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235 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
236 | e80cfcfc | bellard | } |
237 | e80cfcfc | bellard | |
238 | 376253ec | aliguori | void irq_info(Monitor *mon)
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239 | e80cfcfc | bellard | { |
240 | 7d85892b | blueswir1 | if (slavio_intctl)
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241 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
242 | e80cfcfc | bellard | } |
243 | e80cfcfc | bellard | |
244 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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245 | 327ac2e7 | blueswir1 | { |
246 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
247 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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248 | 327ac2e7 | blueswir1 | unsigned int i; |
249 | 327ac2e7 | blueswir1 | |
250 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
251 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
252 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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253 | 327ac2e7 | blueswir1 | |
254 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
255 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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256 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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257 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
258 | f32d7ec5 | blueswir1 | } |
259 | 327ac2e7 | blueswir1 | break;
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260 | 327ac2e7 | blueswir1 | } |
261 | 327ac2e7 | blueswir1 | } |
262 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
263 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
264 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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265 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
266 | 327ac2e7 | blueswir1 | } |
267 | 327ac2e7 | blueswir1 | } |
268 | 327ac2e7 | blueswir1 | |
269 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
270 | b3a23197 | blueswir1 | { |
271 | b3a23197 | blueswir1 | CPUState *env = opaque; |
272 | b3a23197 | blueswir1 | |
273 | b3a23197 | blueswir1 | if (level) {
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274 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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275 | b3a23197 | blueswir1 | env->halted = 0;
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276 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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277 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
278 | b3a23197 | blueswir1 | } else {
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279 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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280 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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281 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
282 | b3a23197 | blueswir1 | } |
283 | b3a23197 | blueswir1 | } |
284 | b3a23197 | blueswir1 | |
285 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
286 | b3a23197 | blueswir1 | { |
287 | b3a23197 | blueswir1 | } |
288 | b3a23197 | blueswir1 | |
289 | 3475187d | bellard | static void *slavio_misc; |
290 | 3475187d | bellard | |
291 | 3475187d | bellard | void qemu_system_powerdown(void) |
292 | 3475187d | bellard | { |
293 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
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294 | 3475187d | bellard | } |
295 | 3475187d | bellard | |
296 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
297 | c68ea704 | bellard | { |
298 | c68ea704 | bellard | CPUState *env = opaque; |
299 | 3d29fbef | blueswir1 | |
300 | 3d29fbef | blueswir1 | cpu_reset(env); |
301 | 3d29fbef | blueswir1 | env->halted = 0;
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302 | 3d29fbef | blueswir1 | } |
303 | 3d29fbef | blueswir1 | |
304 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
305 | 3d29fbef | blueswir1 | { |
306 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
307 | 3d29fbef | blueswir1 | |
308 | c68ea704 | bellard | cpu_reset(env); |
309 | 3d29fbef | blueswir1 | env->halted = 1;
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310 | c68ea704 | bellard | } |
311 | c68ea704 | bellard | |
312 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
313 | 6d0c293d | blueswir1 | { |
314 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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315 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
316 | 6d0c293d | blueswir1 | } |
317 | 6d0c293d | blueswir1 | |
318 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
319 | 293f78bc | blueswir1 | const char *initrd_filename, |
320 | 293f78bc | blueswir1 | ram_addr_t RAM_size) |
321 | 3ebf5aaf | blueswir1 | { |
322 | 3ebf5aaf | blueswir1 | int linux_boot;
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323 | 3ebf5aaf | blueswir1 | unsigned int i; |
324 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
|
325 | 3ebf5aaf | blueswir1 | |
326 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
|
327 | 3ebf5aaf | blueswir1 | |
328 | 3ebf5aaf | blueswir1 | kernel_size = 0;
|
329 | 3ebf5aaf | blueswir1 | if (linux_boot) {
|
330 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
331 | 3ebf5aaf | blueswir1 | NULL);
|
332 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
333 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
334 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
335 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
336 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
337 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
338 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
339 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
340 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
341 | 3ebf5aaf | blueswir1 | kernel_filename); |
342 | 3ebf5aaf | blueswir1 | exit(1);
|
343 | 3ebf5aaf | blueswir1 | } |
344 | 3ebf5aaf | blueswir1 | |
345 | 3ebf5aaf | blueswir1 | /* load initrd */
|
346 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
347 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
348 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
349 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
350 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
351 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
352 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
353 | 3ebf5aaf | blueswir1 | initrd_filename); |
354 | 3ebf5aaf | blueswir1 | exit(1);
|
355 | 3ebf5aaf | blueswir1 | } |
356 | 3ebf5aaf | blueswir1 | } |
357 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
358 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
359 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
360 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
361 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
362 | 3ebf5aaf | blueswir1 | break;
|
363 | 3ebf5aaf | blueswir1 | } |
364 | 3ebf5aaf | blueswir1 | } |
365 | 3ebf5aaf | blueswir1 | } |
366 | 3ebf5aaf | blueswir1 | } |
367 | 3ebf5aaf | blueswir1 | return kernel_size;
|
368 | 3ebf5aaf | blueswir1 | } |
369 | 3ebf5aaf | blueswir1 | |
370 | 8137cde8 | blueswir1 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
371 | 3ebf5aaf | blueswir1 | const char *boot_device, |
372 | 3023f332 | aliguori | const char *kernel_filename, |
373 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
374 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
375 | 36cd9210 | blueswir1 | |
376 | 420557e8 | bellard | { |
377 | ba3c64fb | bellard | CPUState *env, *envs[MAX_CPUS]; |
378 | 713c45fa | bellard | unsigned int i; |
379 | b3ceef24 | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
380 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
381 | d7edfd27 | blueswir1 | *espdma_irq, *ledma_irq; |
382 | 2d069bab | blueswir1 | qemu_irq *esp_reset, *le_reset; |
383 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
384 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
385 | 5c6602c5 | blueswir1 | ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset; |
386 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
387 | 3ebf5aaf | blueswir1 | int ret;
|
388 | 3ebf5aaf | blueswir1 | char buf[1024]; |
389 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
390 | 22548760 | blueswir1 | int drive_index;
|
391 | 3cce6243 | blueswir1 | void *fw_cfg;
|
392 | 420557e8 | bellard | |
393 | ba3c64fb | bellard | /* init CPUs */
|
394 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
395 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
396 | b3a23197 | blueswir1 | |
397 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
398 | aaed909a | bellard | env = cpu_init(cpu_model); |
399 | aaed909a | bellard | if (!env) {
|
400 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
401 | aaed909a | bellard | exit(1);
|
402 | aaed909a | bellard | } |
403 | aaed909a | bellard | cpu_sparc_set_id(env, i); |
404 | ba3c64fb | bellard | envs[i] = env; |
405 | 3d29fbef | blueswir1 | if (i == 0) { |
406 | 3d29fbef | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
407 | 3d29fbef | blueswir1 | } else {
|
408 | 3d29fbef | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
409 | ba3c64fb | bellard | env->halted = 1;
|
410 | 3d29fbef | blueswir1 | } |
411 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
412 | 3ebf5aaf | blueswir1 | env->prom_addr = hwdef->slavio_base; |
413 | ba3c64fb | bellard | } |
414 | b3a23197 | blueswir1 | |
415 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
416 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
417 | b3a23197 | blueswir1 | |
418 | 3ebf5aaf | blueswir1 | |
419 | 420557e8 | bellard | /* allocate RAM */
|
420 | 3ebf5aaf | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
421 | 77f193da | blueswir1 | fprintf(stderr, |
422 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
423 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
424 | 3ebf5aaf | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
425 | 3ebf5aaf | blueswir1 | exit(1);
|
426 | 3ebf5aaf | blueswir1 | } |
427 | 5c6602c5 | blueswir1 | ram_offset = qemu_ram_alloc(RAM_size); |
428 | 5c6602c5 | blueswir1 | cpu_register_physical_memory(0, RAM_size, ram_offset);
|
429 | 420557e8 | bellard | |
430 | 3ebf5aaf | blueswir1 | /* load boot prom */
|
431 | 5c6602c5 | blueswir1 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
432 | 3ebf5aaf | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
433 | 3ebf5aaf | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
434 | 3ebf5aaf | blueswir1 | TARGET_PAGE_MASK, |
435 | 3ebf5aaf | blueswir1 | prom_offset | IO_MEM_ROM); |
436 | 3ebf5aaf | blueswir1 | |
437 | 3ebf5aaf | blueswir1 | if (bios_name == NULL) |
438 | 3ebf5aaf | blueswir1 | bios_name = PROM_FILENAME; |
439 | 3ebf5aaf | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
440 | 3ebf5aaf | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
441 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
442 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
443 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
444 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
445 | 3ebf5aaf | blueswir1 | buf); |
446 | 3ebf5aaf | blueswir1 | exit(1);
|
447 | 3ebf5aaf | blueswir1 | } |
448 | 3ebf5aaf | blueswir1 | |
449 | 3ebf5aaf | blueswir1 | /* set up devices */
|
450 | 36cd9210 | blueswir1 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
451 | 5dcb6b91 | blueswir1 | hwdef->intctl_base + 0x10000ULL,
|
452 | d537cf6c | pbrook | &hwdef->intbit_to_level[0],
|
453 | d7edfd27 | blueswir1 | &slavio_irq, &slavio_cpu_irq, |
454 | b3a23197 | blueswir1 | cpu_irqs, |
455 | d7edfd27 | blueswir1 | hwdef->clock_irq); |
456 | b3a23197 | blueswir1 | |
457 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
458 | 293f78bc | blueswir1 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
459 | 4c2485de | blueswir1 | |
460 | 5c6602c5 | blueswir1 | idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
|
461 | 293f78bc | blueswir1 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
|
462 | 5c6602c5 | blueswir1 | idreg_offset | IO_MEM_ROM); |
463 | 293f78bc | blueswir1 | cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data, |
464 | 293f78bc | blueswir1 | sizeof(idreg_data));
|
465 | 4c2485de | blueswir1 | } |
466 | 4c2485de | blueswir1 | |
467 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
468 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
469 | ff403da6 | blueswir1 | |
470 | 5aca8c3b | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
471 | 2d069bab | blueswir1 | iommu, &espdma_irq, &esp_reset); |
472 | 2d069bab | blueswir1 | |
473 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
474 | 2d069bab | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
475 | 2d069bab | blueswir1 | &le_reset); |
476 | ba3c64fb | bellard | |
477 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
478 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
479 | eee0b836 | blueswir1 | exit (1);
|
480 | eee0b836 | blueswir1 | } |
481 | 5c6602c5 | blueswir1 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
482 | 3023f332 | aliguori | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
483 | eee0b836 | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
484 | dbe06e18 | blueswir1 | |
485 | 0ae18cee | aliguori | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
486 | dbe06e18 | blueswir1 | |
487 | d537cf6c | pbrook | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
488 | d537cf6c | pbrook | hwdef->nvram_size, 8);
|
489 | 81732d19 | blueswir1 | |
490 | 81732d19 | blueswir1 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
491 | 19f8e5dd | blueswir1 | slavio_cpu_irq, smp_cpus); |
492 | 81732d19 | blueswir1 | |
493 | 577390ff | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
494 | b4ed08e0 | blueswir1 | nographic, ESCC_CLOCK, 1);
|
495 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
496 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
497 | aeeb69c7 | aurel32 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq], |
498 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
499 | 741402f9 | blueswir1 | |
500 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
501 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
502 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
503 | 6d0c293d | blueswir1 | slavio_irq[hwdef->me_irq], cpu_halt[0],
|
504 | 2be17ebd | blueswir1 | &fdc_tc); |
505 | 2be17ebd | blueswir1 | |
506 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
507 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
508 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
509 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
510 | 22548760 | blueswir1 | if (drive_index != -1) |
511 | 22548760 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
512 | 2d069bab | blueswir1 | |
513 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
514 | 2be17ebd | blueswir1 | fdc_tc); |
515 | e4bcb14c | ths | } |
516 | e4bcb14c | ths | |
517 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
518 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
519 | e4bcb14c | ths | exit(1);
|
520 | e4bcb14c | ths | } |
521 | e4bcb14c | ths | |
522 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
523 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
524 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
525 | f1587550 | ths | |
526 | e4bcb14c | ths | for (i = 0; i < ESP_MAX_DEVS; i++) { |
527 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
528 | 22548760 | blueswir1 | if (drive_index == -1) |
529 | e4bcb14c | ths | continue;
|
530 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
531 | f1587550 | ths | } |
532 | f1587550 | ths | |
533 | fe096129 | blueswir1 | if (hwdef->cs_base)
|
534 | 803b3c7b | blueswir1 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
535 | b3ceef24 | blueswir1 | |
536 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
537 | 293f78bc | blueswir1 | RAM_size); |
538 | 36cd9210 | blueswir1 | |
539 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
540 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
541 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
542 | 905fdcb5 | blueswir1 | "Sun4m");
|
543 | 7eb0c8e8 | blueswir1 | |
544 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
545 | e42c20b4 | blueswir1 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
546 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
547 | 3cce6243 | blueswir1 | |
548 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
549 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
550 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
551 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
552 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
553 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
554 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
555 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
556 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
557 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
558 | 513f789f | blueswir1 | } else {
|
559 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
560 | 513f789f | blueswir1 | } |
561 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
562 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
563 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
564 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
565 | 36cd9210 | blueswir1 | } |
566 | 36cd9210 | blueswir1 | |
567 | 905fdcb5 | blueswir1 | enum {
|
568 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
569 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
570 | 905fdcb5 | blueswir1 | vger_id, |
571 | 905fdcb5 | blueswir1 | lx_id, |
572 | 905fdcb5 | blueswir1 | ss4_id, |
573 | 905fdcb5 | blueswir1 | scls_id, |
574 | 905fdcb5 | blueswir1 | sbook_id, |
575 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
576 | 905fdcb5 | blueswir1 | ss20_id, |
577 | 905fdcb5 | blueswir1 | ss600mp_id, |
578 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
579 | 905fdcb5 | blueswir1 | ss2000_id, |
580 | 905fdcb5 | blueswir1 | }; |
581 | 905fdcb5 | blueswir1 | |
582 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
583 | 36cd9210 | blueswir1 | /* SS-5 */
|
584 | 36cd9210 | blueswir1 | { |
585 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
586 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
587 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
588 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
589 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
590 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
591 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
592 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
593 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
594 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
595 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
596 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
597 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
598 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
599 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
600 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
601 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
602 | 36cd9210 | blueswir1 | .vram_size = 0x00100000,
|
603 | 36cd9210 | blueswir1 | .nvram_size = 0x2000,
|
604 | 36cd9210 | blueswir1 | .esp_irq = 18,
|
605 | 36cd9210 | blueswir1 | .le_irq = 16,
|
606 | e3a79bca | blueswir1 | .clock_irq = 7,
|
607 | 36cd9210 | blueswir1 | .clock1_irq = 19,
|
608 | 36cd9210 | blueswir1 | .ms_kb_irq = 14,
|
609 | 36cd9210 | blueswir1 | .ser_irq = 15,
|
610 | 36cd9210 | blueswir1 | .fd_irq = 22,
|
611 | 36cd9210 | blueswir1 | .me_irq = 30,
|
612 | 36cd9210 | blueswir1 | .cs_irq = 5,
|
613 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
614 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
615 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
616 | e0353fe2 | blueswir1 | .intbit_to_level = { |
617 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
618 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
619 | e0353fe2 | blueswir1 | }, |
620 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
621 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
622 | e0353fe2 | blueswir1 | }, |
623 | e0353fe2 | blueswir1 | /* SS-10 */
|
624 | e0353fe2 | blueswir1 | { |
625 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
626 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
627 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
628 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
629 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
630 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
631 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
632 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
633 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
634 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
635 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
636 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
637 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
638 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
639 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
640 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
641 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
642 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
643 | e0353fe2 | blueswir1 | .vram_size = 0x00100000,
|
644 | e0353fe2 | blueswir1 | .nvram_size = 0x2000,
|
645 | e0353fe2 | blueswir1 | .esp_irq = 18,
|
646 | e0353fe2 | blueswir1 | .le_irq = 16,
|
647 | e3a79bca | blueswir1 | .clock_irq = 7,
|
648 | e0353fe2 | blueswir1 | .clock1_irq = 19,
|
649 | e0353fe2 | blueswir1 | .ms_kb_irq = 14,
|
650 | e0353fe2 | blueswir1 | .ser_irq = 15,
|
651 | e0353fe2 | blueswir1 | .fd_irq = 22,
|
652 | e0353fe2 | blueswir1 | .me_irq = 30,
|
653 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
654 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
655 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
656 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
657 | e0353fe2 | blueswir1 | .intbit_to_level = { |
658 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
659 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
660 | e0353fe2 | blueswir1 | }, |
661 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
662 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
663 | 36cd9210 | blueswir1 | }, |
664 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
665 | 6a3b9cc9 | blueswir1 | { |
666 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
667 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
668 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
669 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
670 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
671 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
672 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
673 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
674 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
675 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
676 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
677 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
678 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
679 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
680 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
681 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
682 | 6a3b9cc9 | blueswir1 | .vram_size = 0x00100000,
|
683 | 6a3b9cc9 | blueswir1 | .nvram_size = 0x2000,
|
684 | 6a3b9cc9 | blueswir1 | .esp_irq = 18,
|
685 | 6a3b9cc9 | blueswir1 | .le_irq = 16,
|
686 | e3a79bca | blueswir1 | .clock_irq = 7,
|
687 | 6a3b9cc9 | blueswir1 | .clock1_irq = 19,
|
688 | 6a3b9cc9 | blueswir1 | .ms_kb_irq = 14,
|
689 | 6a3b9cc9 | blueswir1 | .ser_irq = 15,
|
690 | 6a3b9cc9 | blueswir1 | .fd_irq = 22,
|
691 | 6a3b9cc9 | blueswir1 | .me_irq = 30,
|
692 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
693 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
694 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
695 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
696 | 6a3b9cc9 | blueswir1 | .intbit_to_level = { |
697 | 6a3b9cc9 | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
698 | 6a3b9cc9 | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
699 | 6a3b9cc9 | blueswir1 | }, |
700 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
701 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
702 | 6a3b9cc9 | blueswir1 | }, |
703 | ae40972f | blueswir1 | /* SS-20 */
|
704 | ae40972f | blueswir1 | { |
705 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
706 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
707 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
708 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
709 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
710 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
711 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
712 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
713 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
714 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
715 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
716 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
717 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
718 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
719 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
720 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
721 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
722 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
723 | ae40972f | blueswir1 | .vram_size = 0x00100000,
|
724 | ae40972f | blueswir1 | .nvram_size = 0x2000,
|
725 | ae40972f | blueswir1 | .esp_irq = 18,
|
726 | ae40972f | blueswir1 | .le_irq = 16,
|
727 | e3a79bca | blueswir1 | .clock_irq = 7,
|
728 | ae40972f | blueswir1 | .clock1_irq = 19,
|
729 | ae40972f | blueswir1 | .ms_kb_irq = 14,
|
730 | ae40972f | blueswir1 | .ser_irq = 15,
|
731 | ae40972f | blueswir1 | .fd_irq = 22,
|
732 | ae40972f | blueswir1 | .me_irq = 30,
|
733 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
734 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
735 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
736 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
737 | ae40972f | blueswir1 | .intbit_to_level = { |
738 | ae40972f | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
739 | ae40972f | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
740 | ae40972f | blueswir1 | }, |
741 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
742 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
743 | ae40972f | blueswir1 | }, |
744 | a526a31c | blueswir1 | /* Voyager */
|
745 | a526a31c | blueswir1 | { |
746 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
747 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
748 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
749 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
750 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
751 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
752 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
753 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
754 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
755 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
756 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
757 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
758 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
759 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
760 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
761 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
762 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
763 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
764 | a526a31c | blueswir1 | .esp_irq = 18,
|
765 | a526a31c | blueswir1 | .le_irq = 16,
|
766 | a526a31c | blueswir1 | .clock_irq = 7,
|
767 | a526a31c | blueswir1 | .clock1_irq = 19,
|
768 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
769 | a526a31c | blueswir1 | .ser_irq = 15,
|
770 | a526a31c | blueswir1 | .fd_irq = 22,
|
771 | a526a31c | blueswir1 | .me_irq = 30,
|
772 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
773 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
774 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
775 | a526a31c | blueswir1 | .intbit_to_level = { |
776 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
777 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
778 | a526a31c | blueswir1 | }, |
779 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
780 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
781 | a526a31c | blueswir1 | }, |
782 | a526a31c | blueswir1 | /* LX */
|
783 | a526a31c | blueswir1 | { |
784 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
785 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
786 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
787 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
788 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
789 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
790 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
791 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
792 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
793 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
794 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
795 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
796 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
797 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
798 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
799 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
800 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
801 | a526a31c | blueswir1 | .esp_irq = 18,
|
802 | a526a31c | blueswir1 | .le_irq = 16,
|
803 | a526a31c | blueswir1 | .clock_irq = 7,
|
804 | a526a31c | blueswir1 | .clock1_irq = 19,
|
805 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
806 | a526a31c | blueswir1 | .ser_irq = 15,
|
807 | a526a31c | blueswir1 | .fd_irq = 22,
|
808 | a526a31c | blueswir1 | .me_irq = 30,
|
809 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
810 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
811 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
812 | a526a31c | blueswir1 | .intbit_to_level = { |
813 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
814 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
815 | a526a31c | blueswir1 | }, |
816 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
817 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
818 | a526a31c | blueswir1 | }, |
819 | a526a31c | blueswir1 | /* SS-4 */
|
820 | a526a31c | blueswir1 | { |
821 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
822 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
823 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
824 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
825 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
826 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
827 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
828 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
829 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
830 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
831 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
832 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
833 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
834 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
835 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
836 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
837 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
838 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
839 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
840 | a526a31c | blueswir1 | .esp_irq = 18,
|
841 | a526a31c | blueswir1 | .le_irq = 16,
|
842 | a526a31c | blueswir1 | .clock_irq = 7,
|
843 | a526a31c | blueswir1 | .clock1_irq = 19,
|
844 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
845 | a526a31c | blueswir1 | .ser_irq = 15,
|
846 | a526a31c | blueswir1 | .fd_irq = 22,
|
847 | a526a31c | blueswir1 | .me_irq = 30,
|
848 | a526a31c | blueswir1 | .cs_irq = 5,
|
849 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
850 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
851 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
852 | a526a31c | blueswir1 | .intbit_to_level = { |
853 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
854 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
855 | a526a31c | blueswir1 | }, |
856 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
857 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
858 | a526a31c | blueswir1 | }, |
859 | a526a31c | blueswir1 | /* SPARCClassic */
|
860 | a526a31c | blueswir1 | { |
861 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
862 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
863 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
864 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
865 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
866 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
867 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
868 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
869 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
870 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
871 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
872 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
873 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
874 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
875 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
876 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
877 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
878 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
879 | a526a31c | blueswir1 | .esp_irq = 18,
|
880 | a526a31c | blueswir1 | .le_irq = 16,
|
881 | a526a31c | blueswir1 | .clock_irq = 7,
|
882 | a526a31c | blueswir1 | .clock1_irq = 19,
|
883 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
884 | a526a31c | blueswir1 | .ser_irq = 15,
|
885 | a526a31c | blueswir1 | .fd_irq = 22,
|
886 | a526a31c | blueswir1 | .me_irq = 30,
|
887 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
888 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
889 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
890 | a526a31c | blueswir1 | .intbit_to_level = { |
891 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
892 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
893 | a526a31c | blueswir1 | }, |
894 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
895 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
896 | a526a31c | blueswir1 | }, |
897 | a526a31c | blueswir1 | /* SPARCbook */
|
898 | a526a31c | blueswir1 | { |
899 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
900 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
901 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
902 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
903 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
904 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
905 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
906 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
907 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
908 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
909 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
910 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
911 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
912 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
913 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
914 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
915 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
916 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
917 | a526a31c | blueswir1 | .esp_irq = 18,
|
918 | a526a31c | blueswir1 | .le_irq = 16,
|
919 | a526a31c | blueswir1 | .clock_irq = 7,
|
920 | a526a31c | blueswir1 | .clock1_irq = 19,
|
921 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
922 | a526a31c | blueswir1 | .ser_irq = 15,
|
923 | a526a31c | blueswir1 | .fd_irq = 22,
|
924 | a526a31c | blueswir1 | .me_irq = 30,
|
925 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
926 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
927 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
928 | a526a31c | blueswir1 | .intbit_to_level = { |
929 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
930 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
931 | a526a31c | blueswir1 | }, |
932 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
933 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
934 | a526a31c | blueswir1 | }, |
935 | 36cd9210 | blueswir1 | }; |
936 | 36cd9210 | blueswir1 | |
937 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
938 | 00f82b8a | aurel32 | static void ss5_init(ram_addr_t RAM_size, int vga_ram_size, |
939 | 3023f332 | aliguori | const char *boot_device, |
940 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
941 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
942 | 36cd9210 | blueswir1 | { |
943 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
944 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
945 | 420557e8 | bellard | } |
946 | c0e564d5 | bellard | |
947 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
948 | 00f82b8a | aurel32 | static void ss10_init(ram_addr_t RAM_size, int vga_ram_size, |
949 | 3023f332 | aliguori | const char *boot_device, |
950 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
951 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
952 | e0353fe2 | blueswir1 | { |
953 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
954 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
955 | e0353fe2 | blueswir1 | } |
956 | e0353fe2 | blueswir1 | |
957 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
958 | 00f82b8a | aurel32 | static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size, |
959 | 3023f332 | aliguori | const char *boot_device, |
960 | 77f193da | blueswir1 | const char *kernel_filename, |
961 | 77f193da | blueswir1 | const char *kernel_cmdline, |
962 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
963 | 6a3b9cc9 | blueswir1 | { |
964 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
965 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
966 | 6a3b9cc9 | blueswir1 | } |
967 | 6a3b9cc9 | blueswir1 | |
968 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
969 | 00f82b8a | aurel32 | static void ss20_init(ram_addr_t RAM_size, int vga_ram_size, |
970 | 3023f332 | aliguori | const char *boot_device, |
971 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
972 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
973 | ae40972f | blueswir1 | { |
974 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
975 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
976 | ee76f82e | blueswir1 | } |
977 | ee76f82e | blueswir1 | |
978 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
979 | 6ef05b95 | blueswir1 | static void vger_init(ram_addr_t RAM_size, int vga_ram_size, |
980 | 3023f332 | aliguori | const char *boot_device, |
981 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
982 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
983 | a526a31c | blueswir1 | { |
984 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
985 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
986 | a526a31c | blueswir1 | } |
987 | a526a31c | blueswir1 | |
988 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
989 | 6ef05b95 | blueswir1 | static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size, |
990 | 3023f332 | aliguori | const char *boot_device, |
991 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
992 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
993 | a526a31c | blueswir1 | { |
994 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
995 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
996 | a526a31c | blueswir1 | } |
997 | a526a31c | blueswir1 | |
998 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
999 | 6ef05b95 | blueswir1 | static void ss4_init(ram_addr_t RAM_size, int vga_ram_size, |
1000 | 3023f332 | aliguori | const char *boot_device, |
1001 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1002 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1003 | a526a31c | blueswir1 | { |
1004 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1005 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1006 | a526a31c | blueswir1 | } |
1007 | a526a31c | blueswir1 | |
1008 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1009 | 6ef05b95 | blueswir1 | static void scls_init(ram_addr_t RAM_size, int vga_ram_size, |
1010 | 3023f332 | aliguori | const char *boot_device, |
1011 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1012 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1013 | a526a31c | blueswir1 | { |
1014 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1015 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1016 | a526a31c | blueswir1 | } |
1017 | a526a31c | blueswir1 | |
1018 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1019 | 6ef05b95 | blueswir1 | static void sbook_init(ram_addr_t RAM_size, int vga_ram_size, |
1020 | 3023f332 | aliguori | const char *boot_device, |
1021 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1022 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1023 | a526a31c | blueswir1 | { |
1024 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1025 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1026 | a526a31c | blueswir1 | } |
1027 | a526a31c | blueswir1 | |
1028 | 36cd9210 | blueswir1 | QEMUMachine ss5_machine = { |
1029 | 66de733b | blueswir1 | .name = "SS-5",
|
1030 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1031 | 66de733b | blueswir1 | .init = ss5_init, |
1032 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1033 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1034 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1035 | c0e564d5 | bellard | }; |
1036 | e0353fe2 | blueswir1 | |
1037 | e0353fe2 | blueswir1 | QEMUMachine ss10_machine = { |
1038 | 66de733b | blueswir1 | .name = "SS-10",
|
1039 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1040 | 66de733b | blueswir1 | .init = ss10_init, |
1041 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1042 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1043 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1044 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1045 | e0353fe2 | blueswir1 | }; |
1046 | 6a3b9cc9 | blueswir1 | |
1047 | 6a3b9cc9 | blueswir1 | QEMUMachine ss600mp_machine = { |
1048 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1049 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1050 | 66de733b | blueswir1 | .init = ss600mp_init, |
1051 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1052 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1053 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1054 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1055 | 6a3b9cc9 | blueswir1 | }; |
1056 | ae40972f | blueswir1 | |
1057 | ae40972f | blueswir1 | QEMUMachine ss20_machine = { |
1058 | 66de733b | blueswir1 | .name = "SS-20",
|
1059 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1060 | 66de733b | blueswir1 | .init = ss20_init, |
1061 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1062 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1063 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1064 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1065 | ae40972f | blueswir1 | }; |
1066 | ae40972f | blueswir1 | |
1067 | a526a31c | blueswir1 | QEMUMachine voyager_machine = { |
1068 | 66de733b | blueswir1 | .name = "Voyager",
|
1069 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1070 | 66de733b | blueswir1 | .init = vger_init, |
1071 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1072 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1073 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1074 | a526a31c | blueswir1 | }; |
1075 | a526a31c | blueswir1 | |
1076 | a526a31c | blueswir1 | QEMUMachine ss_lx_machine = { |
1077 | 66de733b | blueswir1 | .name = "LX",
|
1078 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1079 | 66de733b | blueswir1 | .init = ss_lx_init, |
1080 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1081 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1082 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1083 | a526a31c | blueswir1 | }; |
1084 | a526a31c | blueswir1 | |
1085 | a526a31c | blueswir1 | QEMUMachine ss4_machine = { |
1086 | 66de733b | blueswir1 | .name = "SS-4",
|
1087 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1088 | 66de733b | blueswir1 | .init = ss4_init, |
1089 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1090 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1091 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1092 | a526a31c | blueswir1 | }; |
1093 | a526a31c | blueswir1 | |
1094 | a526a31c | blueswir1 | QEMUMachine scls_machine = { |
1095 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1096 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1097 | 66de733b | blueswir1 | .init = scls_init, |
1098 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1099 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1100 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1101 | a526a31c | blueswir1 | }; |
1102 | a526a31c | blueswir1 | |
1103 | a526a31c | blueswir1 | QEMUMachine sbook_machine = { |
1104 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1105 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1106 | 66de733b | blueswir1 | .init = sbook_init, |
1107 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1108 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1109 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1110 | a526a31c | blueswir1 | }; |
1111 | a526a31c | blueswir1 | |
1112 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1113 | 7d85892b | blueswir1 | /* SS-1000 */
|
1114 | 7d85892b | blueswir1 | { |
1115 | 7d85892b | blueswir1 | .iounit_bases = { |
1116 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1117 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1118 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1119 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1120 | 7d85892b | blueswir1 | -1,
|
1121 | 7d85892b | blueswir1 | }, |
1122 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1123 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1124 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1125 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1126 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1127 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1128 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1129 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1130 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1131 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1132 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1133 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1134 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1135 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1136 | 7d85892b | blueswir1 | .le_irq = 4,
|
1137 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1138 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1139 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1140 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1141 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1142 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1143 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1144 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1145 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1146 | 7d85892b | blueswir1 | }, |
1147 | 7d85892b | blueswir1 | /* SS-2000 */
|
1148 | 7d85892b | blueswir1 | { |
1149 | 7d85892b | blueswir1 | .iounit_bases = { |
1150 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1151 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1152 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1153 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1154 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1155 | 7d85892b | blueswir1 | }, |
1156 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1157 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1158 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1159 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1160 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1161 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1162 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1163 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1164 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1165 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1166 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1167 | c1d00dc0 | blueswir1 | .vram_size = 0x00100000,
|
1168 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1169 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1170 | 7d85892b | blueswir1 | .le_irq = 4,
|
1171 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1172 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1173 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1174 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1175 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1176 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1177 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1178 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1179 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1180 | 7d85892b | blueswir1 | }, |
1181 | 7d85892b | blueswir1 | }; |
1182 | 7d85892b | blueswir1 | |
1183 | 6ef05b95 | blueswir1 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1184 | 7d85892b | blueswir1 | const char *boot_device, |
1185 | 3023f332 | aliguori | const char *kernel_filename, |
1186 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1187 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1188 | 7d85892b | blueswir1 | { |
1189 | 7d85892b | blueswir1 | CPUState *env, *envs[MAX_CPUS]; |
1190 | 7d85892b | blueswir1 | unsigned int i; |
1191 | 7d85892b | blueswir1 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
1192 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
1193 | 7d85892b | blueswir1 | *espdma_irq, *ledma_irq; |
1194 | 7d85892b | blueswir1 | qemu_irq *esp_reset, *le_reset; |
1195 | 5c6602c5 | blueswir1 | ram_addr_t ram_offset, prom_offset, tcx_offset; |
1196 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1197 | 7d85892b | blueswir1 | int ret;
|
1198 | 7d85892b | blueswir1 | char buf[1024]; |
1199 | 22548760 | blueswir1 | int drive_index;
|
1200 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1201 | 7d85892b | blueswir1 | |
1202 | 7d85892b | blueswir1 | /* init CPUs */
|
1203 | 7d85892b | blueswir1 | if (!cpu_model)
|
1204 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1205 | 7d85892b | blueswir1 | |
1206 | 7d85892b | blueswir1 | for (i = 0; i < smp_cpus; i++) { |
1207 | 7d85892b | blueswir1 | env = cpu_init(cpu_model); |
1208 | 7d85892b | blueswir1 | if (!env) {
|
1209 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1210 | 7d85892b | blueswir1 | exit(1);
|
1211 | 7d85892b | blueswir1 | } |
1212 | 7d85892b | blueswir1 | cpu_sparc_set_id(env, i); |
1213 | 7d85892b | blueswir1 | envs[i] = env; |
1214 | 7d85892b | blueswir1 | if (i == 0) { |
1215 | 7d85892b | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
1216 | 7d85892b | blueswir1 | } else {
|
1217 | 7d85892b | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
1218 | 7d85892b | blueswir1 | env->halted = 1;
|
1219 | 7d85892b | blueswir1 | } |
1220 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1221 | 7d85892b | blueswir1 | env->prom_addr = hwdef->slavio_base; |
1222 | 7d85892b | blueswir1 | } |
1223 | 7d85892b | blueswir1 | |
1224 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1225 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1226 | 7d85892b | blueswir1 | |
1227 | 7d85892b | blueswir1 | /* allocate RAM */
|
1228 | 7d85892b | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1229 | 77f193da | blueswir1 | fprintf(stderr, |
1230 | 77f193da | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1231 | 6ef05b95 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
1232 | 7d85892b | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1233 | 7d85892b | blueswir1 | exit(1);
|
1234 | 7d85892b | blueswir1 | } |
1235 | 5c6602c5 | blueswir1 | ram_offset = qemu_ram_alloc(RAM_size); |
1236 | 5c6602c5 | blueswir1 | cpu_register_physical_memory(0, RAM_size, ram_offset);
|
1237 | 7d85892b | blueswir1 | |
1238 | 7d85892b | blueswir1 | /* load boot prom */
|
1239 | 5c6602c5 | blueswir1 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
1240 | 7d85892b | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
1241 | 7d85892b | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1242 | 7d85892b | blueswir1 | TARGET_PAGE_MASK, |
1243 | 7d85892b | blueswir1 | prom_offset | IO_MEM_ROM); |
1244 | 7d85892b | blueswir1 | |
1245 | 7d85892b | blueswir1 | if (bios_name == NULL) |
1246 | 7d85892b | blueswir1 | bios_name = PROM_FILENAME; |
1247 | 7d85892b | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1248 | 7d85892b | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1249 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
1250 | e01f4a1c | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
1251 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1252 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1253 | 7d85892b | blueswir1 | buf); |
1254 | 7d85892b | blueswir1 | exit(1);
|
1255 | 7d85892b | blueswir1 | } |
1256 | 7d85892b | blueswir1 | |
1257 | 7d85892b | blueswir1 | /* set up devices */
|
1258 | 7d85892b | blueswir1 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
1259 | 7d85892b | blueswir1 | |
1260 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1261 | 7d85892b | blueswir1 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1262 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1263 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1264 | ff403da6 | blueswir1 | sbi_irq[hwdef->me_irq]); |
1265 | 7d85892b | blueswir1 | |
1266 | 7d85892b | blueswir1 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
1267 | 7d85892b | blueswir1 | iounits[0], &espdma_irq, &esp_reset);
|
1268 | 7d85892b | blueswir1 | |
1269 | 7d85892b | blueswir1 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
1270 | 7d85892b | blueswir1 | iounits[0], &ledma_irq, &le_reset);
|
1271 | 7d85892b | blueswir1 | |
1272 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1273 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1274 | 7d85892b | blueswir1 | exit (1);
|
1275 | 7d85892b | blueswir1 | } |
1276 | 5c6602c5 | blueswir1 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
1277 | 3023f332 | aliguori | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
1278 | 7d85892b | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1279 | 7d85892b | blueswir1 | |
1280 | 0ae18cee | aliguori | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1281 | 7d85892b | blueswir1 | |
1282 | 7d85892b | blueswir1 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
1283 | 7d85892b | blueswir1 | hwdef->nvram_size, 8);
|
1284 | 7d85892b | blueswir1 | |
1285 | 7d85892b | blueswir1 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
1286 | 7d85892b | blueswir1 | sbi_cpu_irq, smp_cpus); |
1287 | 7d85892b | blueswir1 | |
1288 | 7d85892b | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
1289 | b4ed08e0 | blueswir1 | nographic, ESCC_CLOCK, 1);
|
1290 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1291 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1292 | aeeb69c7 | aurel32 | escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq], |
1293 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1294 | 7d85892b | blueswir1 | |
1295 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1296 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1297 | 7d85892b | blueswir1 | exit(1);
|
1298 | 7d85892b | blueswir1 | } |
1299 | 7d85892b | blueswir1 | |
1300 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
1301 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
1302 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
1303 | 7d85892b | blueswir1 | |
1304 | 7d85892b | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
1305 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
1306 | 22548760 | blueswir1 | if (drive_index == -1) |
1307 | 7d85892b | blueswir1 | continue;
|
1308 | 22548760 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
1309 | 7d85892b | blueswir1 | } |
1310 | 7d85892b | blueswir1 | |
1311 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1312 | 293f78bc | blueswir1 | RAM_size); |
1313 | 7d85892b | blueswir1 | |
1314 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1315 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1316 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1317 | 905fdcb5 | blueswir1 | "Sun4d");
|
1318 | 3cce6243 | blueswir1 | |
1319 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1320 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1321 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1322 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1323 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1324 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1325 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1326 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1327 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1328 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1329 | 513f789f | blueswir1 | } else {
|
1330 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1331 | 513f789f | blueswir1 | } |
1332 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1333 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1334 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1335 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1336 | 7d85892b | blueswir1 | } |
1337 | 7d85892b | blueswir1 | |
1338 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1339 | 00f82b8a | aurel32 | static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size, |
1340 | 3023f332 | aliguori | const char *boot_device, |
1341 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1342 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1343 | 7d85892b | blueswir1 | { |
1344 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1345 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1346 | 7d85892b | blueswir1 | } |
1347 | 7d85892b | blueswir1 | |
1348 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1349 | 00f82b8a | aurel32 | static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size, |
1350 | 3023f332 | aliguori | const char *boot_device, |
1351 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1352 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1353 | 7d85892b | blueswir1 | { |
1354 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1355 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1356 | 7d85892b | blueswir1 | } |
1357 | 7d85892b | blueswir1 | |
1358 | 7d85892b | blueswir1 | QEMUMachine ss1000_machine = { |
1359 | 66de733b | blueswir1 | .name = "SS-1000",
|
1360 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1361 | 66de733b | blueswir1 | .init = ss1000_init, |
1362 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1363 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1364 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1365 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1366 | 7d85892b | blueswir1 | }; |
1367 | 7d85892b | blueswir1 | |
1368 | 7d85892b | blueswir1 | QEMUMachine ss2000_machine = { |
1369 | 66de733b | blueswir1 | .name = "SS-2000",
|
1370 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1371 | 66de733b | blueswir1 | .init = ss2000_init, |
1372 | 66de733b | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1373 | f88e4b91 | blueswir1 | .nodisk_ok = 1,
|
1374 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1375 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1376 | 7d85892b | blueswir1 | }; |
1377 | 8137cde8 | blueswir1 | |
1378 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1379 | 8137cde8 | blueswir1 | /* SS-2 */
|
1380 | 8137cde8 | blueswir1 | { |
1381 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1382 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1383 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1384 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1385 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1386 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1387 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1388 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1389 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1390 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1391 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1392 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1393 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1394 | 8137cde8 | blueswir1 | .vram_size = 0x00100000,
|
1395 | 8137cde8 | blueswir1 | .nvram_size = 0x800,
|
1396 | 8137cde8 | blueswir1 | .esp_irq = 2,
|
1397 | 8137cde8 | blueswir1 | .le_irq = 3,
|
1398 | 8137cde8 | blueswir1 | .clock_irq = 5,
|
1399 | 8137cde8 | blueswir1 | .clock1_irq = 7,
|
1400 | 8137cde8 | blueswir1 | .ms_kb_irq = 1,
|
1401 | 8137cde8 | blueswir1 | .ser_irq = 1,
|
1402 | 8137cde8 | blueswir1 | .fd_irq = 1,
|
1403 | 8137cde8 | blueswir1 | .me_irq = 1,
|
1404 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1405 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1406 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1407 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1408 | 8137cde8 | blueswir1 | }, |
1409 | 8137cde8 | blueswir1 | }; |
1410 | 8137cde8 | blueswir1 | |
1411 | 8137cde8 | blueswir1 | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1412 | 8137cde8 | blueswir1 | const char *boot_device, |
1413 | 3023f332 | aliguori | const char *kernel_filename, |
1414 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1415 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1416 | 8137cde8 | blueswir1 | { |
1417 | 8137cde8 | blueswir1 | CPUState *env; |
1418 | 8137cde8 | blueswir1 | unsigned int i; |
1419 | 8137cde8 | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
1420 | 8137cde8 | blueswir1 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
1421 | 8137cde8 | blueswir1 | qemu_irq *esp_reset, *le_reset; |
1422 | 8137cde8 | blueswir1 | qemu_irq *fdc_tc; |
1423 | 5c6602c5 | blueswir1 | ram_addr_t ram_offset, prom_offset, tcx_offset; |
1424 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1425 | 8137cde8 | blueswir1 | int ret;
|
1426 | 8137cde8 | blueswir1 | char buf[1024]; |
1427 | 8137cde8 | blueswir1 | BlockDriverState *fd[MAX_FD]; |
1428 | 8137cde8 | blueswir1 | int drive_index;
|
1429 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1430 | 8137cde8 | blueswir1 | |
1431 | 8137cde8 | blueswir1 | /* init CPU */
|
1432 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1433 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1434 | 8137cde8 | blueswir1 | |
1435 | 8137cde8 | blueswir1 | env = cpu_init(cpu_model); |
1436 | 8137cde8 | blueswir1 | if (!env) {
|
1437 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1438 | 8137cde8 | blueswir1 | exit(1);
|
1439 | 8137cde8 | blueswir1 | } |
1440 | 8137cde8 | blueswir1 | |
1441 | 8137cde8 | blueswir1 | cpu_sparc_set_id(env, 0);
|
1442 | 8137cde8 | blueswir1 | |
1443 | 8137cde8 | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
1444 | 8137cde8 | blueswir1 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
1445 | 8137cde8 | blueswir1 | env->prom_addr = hwdef->slavio_base; |
1446 | 8137cde8 | blueswir1 | |
1447 | 8137cde8 | blueswir1 | /* allocate RAM */
|
1448 | 8137cde8 | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1449 | 8137cde8 | blueswir1 | fprintf(stderr, |
1450 | 8137cde8 | blueswir1 | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1451 | 8137cde8 | blueswir1 | (unsigned int)(RAM_size / (1024 * 1024)), |
1452 | 8137cde8 | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1453 | 8137cde8 | blueswir1 | exit(1);
|
1454 | 8137cde8 | blueswir1 | } |
1455 | 5c6602c5 | blueswir1 | ram_offset = qemu_ram_alloc(RAM_size); |
1456 | 5c6602c5 | blueswir1 | cpu_register_physical_memory(0, RAM_size, ram_offset);
|
1457 | 8137cde8 | blueswir1 | |
1458 | 8137cde8 | blueswir1 | /* load boot prom */
|
1459 | 5c6602c5 | blueswir1 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
1460 | 8137cde8 | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
1461 | 8137cde8 | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1462 | 8137cde8 | blueswir1 | TARGET_PAGE_MASK, |
1463 | 8137cde8 | blueswir1 | prom_offset | IO_MEM_ROM); |
1464 | 8137cde8 | blueswir1 | |
1465 | 8137cde8 | blueswir1 | if (bios_name == NULL) |
1466 | 8137cde8 | blueswir1 | bios_name = PROM_FILENAME; |
1467 | 8137cde8 | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1468 | 8137cde8 | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1469 | 8137cde8 | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
1470 | 8137cde8 | blueswir1 | ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX); |
1471 | 8137cde8 | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1472 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1473 | 8137cde8 | blueswir1 | buf); |
1474 | 8137cde8 | blueswir1 | exit(1);
|
1475 | 8137cde8 | blueswir1 | } |
1476 | 8137cde8 | blueswir1 | |
1477 | 8137cde8 | blueswir1 | /* set up devices */
|
1478 | 8137cde8 | blueswir1 | slavio_intctl = sun4c_intctl_init(hwdef->intctl_base, |
1479 | 8137cde8 | blueswir1 | &slavio_irq, cpu_irqs); |
1480 | 8137cde8 | blueswir1 | |
1481 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1482 | 8137cde8 | blueswir1 | slavio_irq[hwdef->me_irq]); |
1483 | 8137cde8 | blueswir1 | |
1484 | 8137cde8 | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
1485 | 8137cde8 | blueswir1 | iommu, &espdma_irq, &esp_reset); |
1486 | 8137cde8 | blueswir1 | |
1487 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1488 | 8137cde8 | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
1489 | 8137cde8 | blueswir1 | &le_reset); |
1490 | 8137cde8 | blueswir1 | |
1491 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1492 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1493 | 8137cde8 | blueswir1 | exit (1);
|
1494 | 8137cde8 | blueswir1 | } |
1495 | 5c6602c5 | blueswir1 | tcx_offset = qemu_ram_alloc(hwdef->vram_size); |
1496 | 3023f332 | aliguori | tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset, |
1497 | 8137cde8 | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1498 | 8137cde8 | blueswir1 | |
1499 | 0ae18cee | aliguori | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1500 | 8137cde8 | blueswir1 | |
1501 | 8137cde8 | blueswir1 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
1502 | 8137cde8 | blueswir1 | hwdef->nvram_size, 2);
|
1503 | 8137cde8 | blueswir1 | |
1504 | 8137cde8 | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
1505 | b4ed08e0 | blueswir1 | nographic, ESCC_CLOCK, 1);
|
1506 | 8137cde8 | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1507 | 8137cde8 | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1508 | aeeb69c7 | aurel32 | escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
1509 | aeeb69c7 | aurel32 | slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1], |
1510 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1511 | 8137cde8 | blueswir1 | |
1512 | fe096129 | blueswir1 | slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0, |
1513 | 6d0c293d | blueswir1 | slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
|
1514 | 8137cde8 | blueswir1 | |
1515 | 8137cde8 | blueswir1 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1516 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1517 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1518 | 8137cde8 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, 0); |
1519 | 8137cde8 | blueswir1 | if (drive_index != -1) |
1520 | 8137cde8 | blueswir1 | fd[0] = drives_table[drive_index].bdrv;
|
1521 | 8137cde8 | blueswir1 | |
1522 | 8137cde8 | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
1523 | 8137cde8 | blueswir1 | fdc_tc); |
1524 | 8137cde8 | blueswir1 | } |
1525 | 8137cde8 | blueswir1 | |
1526 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1527 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1528 | 8137cde8 | blueswir1 | exit(1);
|
1529 | 8137cde8 | blueswir1 | } |
1530 | 8137cde8 | blueswir1 | |
1531 | 8137cde8 | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
1532 | 8137cde8 | blueswir1 | espdma_memory_read, espdma_memory_write, |
1533 | 8137cde8 | blueswir1 | espdma, *espdma_irq, esp_reset); |
1534 | 8137cde8 | blueswir1 | |
1535 | 8137cde8 | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
1536 | 8137cde8 | blueswir1 | drive_index = drive_get_index(IF_SCSI, 0, i);
|
1537 | 8137cde8 | blueswir1 | if (drive_index == -1) |
1538 | 8137cde8 | blueswir1 | continue;
|
1539 | 8137cde8 | blueswir1 | esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i); |
1540 | 8137cde8 | blueswir1 | } |
1541 | 8137cde8 | blueswir1 | |
1542 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1543 | 8137cde8 | blueswir1 | RAM_size); |
1544 | 8137cde8 | blueswir1 | |
1545 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1546 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1547 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1548 | 8137cde8 | blueswir1 | "Sun4c");
|
1549 | 8137cde8 | blueswir1 | |
1550 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1551 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1552 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1553 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1554 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1555 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1556 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1557 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1558 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1559 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
1560 | 513f789f | blueswir1 | } else {
|
1561 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1562 | 513f789f | blueswir1 | } |
1563 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1564 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1565 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1566 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1567 | 8137cde8 | blueswir1 | } |
1568 | 8137cde8 | blueswir1 | |
1569 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1570 | 8137cde8 | blueswir1 | static void ss2_init(ram_addr_t RAM_size, int vga_ram_size, |
1571 | 3023f332 | aliguori | const char *boot_device, |
1572 | 8137cde8 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1573 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1574 | 8137cde8 | blueswir1 | { |
1575 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1576 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1577 | 8137cde8 | blueswir1 | } |
1578 | 8137cde8 | blueswir1 | |
1579 | 8137cde8 | blueswir1 | QEMUMachine ss2_machine = { |
1580 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1581 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1582 | 8137cde8 | blueswir1 | .init = ss2_init, |
1583 | 8137cde8 | blueswir1 | .ram_require = PROM_SIZE_MAX + TCX_SIZE, |
1584 | 8137cde8 | blueswir1 | .nodisk_ok = 1,
|
1585 | 8137cde8 | blueswir1 | .use_scsi = 1,
|
1586 | 8137cde8 | blueswir1 | }; |