root / hw / tc58128.c @ b8c18e4c
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1 | 27c7ca7e | bellard | #include <assert.h> |
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2 | 87ecb68b | pbrook | #include "hw.h" |
3 | 87ecb68b | pbrook | #include "sh.h" |
4 | 87ecb68b | pbrook | #include "sysemu.h" |
5 | 27c7ca7e | bellard | |
6 | 27c7ca7e | bellard | #define CE1 0x0100 |
7 | 27c7ca7e | bellard | #define CE2 0x0200 |
8 | 27c7ca7e | bellard | #define RE 0x0400 |
9 | 27c7ca7e | bellard | #define WE 0x0800 |
10 | 27c7ca7e | bellard | #define ALE 0x1000 |
11 | 27c7ca7e | bellard | #define CLE 0x2000 |
12 | 27c7ca7e | bellard | #define RDY1 0x4000 |
13 | 27c7ca7e | bellard | #define RDY2 0x8000 |
14 | 27c7ca7e | bellard | #define RDY(n) ((n) == 0 ? RDY1 : RDY2) |
15 | 27c7ca7e | bellard | |
16 | 27c7ca7e | bellard | typedef enum { WAIT, READ1, READ2, READ3 } state_t; |
17 | 27c7ca7e | bellard | |
18 | 27c7ca7e | bellard | typedef struct { |
19 | 27c7ca7e | bellard | uint8_t *flash_contents; |
20 | 27c7ca7e | bellard | state_t state; |
21 | 27c7ca7e | bellard | uint32_t address; |
22 | 27c7ca7e | bellard | uint8_t address_cycle; |
23 | 27c7ca7e | bellard | } tc58128_dev; |
24 | 27c7ca7e | bellard | |
25 | 27c7ca7e | bellard | static tc58128_dev tc58128_devs[2]; |
26 | 27c7ca7e | bellard | |
27 | 27c7ca7e | bellard | #define FLASH_SIZE (16*1024*1024) |
28 | 27c7ca7e | bellard | |
29 | 7ccfb2eb | blueswir1 | static void init_dev(tc58128_dev * dev, const char *filename) |
30 | 27c7ca7e | bellard | { |
31 | 27c7ca7e | bellard | int ret, blocks;
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32 | 27c7ca7e | bellard | |
33 | 27c7ca7e | bellard | dev->state = WAIT; |
34 | 27c7ca7e | bellard | dev->flash_contents = qemu_mallocz(FLASH_SIZE); |
35 | 27c7ca7e | bellard | memset(dev->flash_contents, 0xff, FLASH_SIZE);
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36 | 27c7ca7e | bellard | if (!dev->flash_contents) {
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37 | 27c7ca7e | bellard | fprintf(stderr, "could not alloc memory for flash\n");
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38 | 27c7ca7e | bellard | exit(1);
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39 | 27c7ca7e | bellard | } |
40 | 27c7ca7e | bellard | if (filename) {
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41 | 27c7ca7e | bellard | /* Load flash image skipping the first block */
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42 | 27c7ca7e | bellard | ret = load_image(filename, dev->flash_contents + 528 * 32); |
43 | 27c7ca7e | bellard | if (ret < 0) { |
44 | 27c7ca7e | bellard | fprintf(stderr, "ret=%d\n", ret);
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45 | 27c7ca7e | bellard | fprintf(stderr, "qemu: could not load flash image %s\n",
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46 | 27c7ca7e | bellard | filename); |
47 | 27c7ca7e | bellard | exit(1);
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48 | 27c7ca7e | bellard | } else {
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49 | 27c7ca7e | bellard | /* Build first block with number of blocks */
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50 | 27c7ca7e | bellard | blocks = (ret + 528 * 32 - 1) / (528 * 32); |
51 | 27c7ca7e | bellard | dev->flash_contents[0] = blocks & 0xff; |
52 | 27c7ca7e | bellard | dev->flash_contents[1] = (blocks >> 8) & 0xff; |
53 | 27c7ca7e | bellard | dev->flash_contents[2] = (blocks >> 16) & 0xff; |
54 | 27c7ca7e | bellard | dev->flash_contents[3] = (blocks >> 24) & 0xff; |
55 | 27c7ca7e | bellard | fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
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56 | 27c7ca7e | bellard | filename); |
57 | 27c7ca7e | bellard | } |
58 | 27c7ca7e | bellard | } |
59 | 27c7ca7e | bellard | } |
60 | 27c7ca7e | bellard | |
61 | b1d8e52e | blueswir1 | static void handle_command(tc58128_dev * dev, uint8_t command) |
62 | 27c7ca7e | bellard | { |
63 | 27c7ca7e | bellard | switch (command) {
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64 | 27c7ca7e | bellard | case 0xff: |
65 | 27c7ca7e | bellard | fprintf(stderr, "reset flash device\n");
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66 | 27c7ca7e | bellard | dev->state = WAIT; |
67 | 27c7ca7e | bellard | break;
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68 | 27c7ca7e | bellard | case 0x00: |
69 | 27c7ca7e | bellard | fprintf(stderr, "read mode 1\n");
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70 | 27c7ca7e | bellard | dev->state = READ1; |
71 | 27c7ca7e | bellard | dev->address_cycle = 0;
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72 | 27c7ca7e | bellard | break;
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73 | 27c7ca7e | bellard | case 0x01: |
74 | 27c7ca7e | bellard | fprintf(stderr, "read mode 2\n");
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75 | 27c7ca7e | bellard | dev->state = READ2; |
76 | 27c7ca7e | bellard | dev->address_cycle = 0;
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77 | 27c7ca7e | bellard | break;
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78 | 27c7ca7e | bellard | case 0x50: |
79 | 27c7ca7e | bellard | fprintf(stderr, "read mode 3\n");
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80 | 27c7ca7e | bellard | dev->state = READ3; |
81 | 27c7ca7e | bellard | dev->address_cycle = 0;
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82 | 27c7ca7e | bellard | break;
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83 | 27c7ca7e | bellard | default:
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84 | 27c7ca7e | bellard | fprintf(stderr, "unknown flash command 0x%02x\n", command);
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85 | 27c7ca7e | bellard | assert(0);
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86 | 27c7ca7e | bellard | } |
87 | 27c7ca7e | bellard | } |
88 | 27c7ca7e | bellard | |
89 | b1d8e52e | blueswir1 | static void handle_address(tc58128_dev * dev, uint8_t data) |
90 | 27c7ca7e | bellard | { |
91 | 27c7ca7e | bellard | switch (dev->state) {
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92 | 27c7ca7e | bellard | case READ1:
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93 | 27c7ca7e | bellard | case READ2:
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94 | 27c7ca7e | bellard | case READ3:
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95 | 27c7ca7e | bellard | switch (dev->address_cycle) {
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96 | 27c7ca7e | bellard | case 0: |
97 | 27c7ca7e | bellard | dev->address = data; |
98 | 27c7ca7e | bellard | if (dev->state == READ2)
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99 | 27c7ca7e | bellard | dev->address |= 0x100;
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100 | 27c7ca7e | bellard | else if (dev->state == READ3) |
101 | 27c7ca7e | bellard | dev->address |= 0x200;
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102 | 27c7ca7e | bellard | break;
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103 | 27c7ca7e | bellard | case 1: |
104 | 27c7ca7e | bellard | dev->address += data * 528 * 0x100; |
105 | 27c7ca7e | bellard | break;
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106 | 27c7ca7e | bellard | case 2: |
107 | 27c7ca7e | bellard | dev->address += data * 528;
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108 | 27c7ca7e | bellard | fprintf(stderr, "address pointer in flash: 0x%08x\n",
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109 | 27c7ca7e | bellard | dev->address); |
110 | 27c7ca7e | bellard | break;
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111 | 27c7ca7e | bellard | default:
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112 | 27c7ca7e | bellard | /* Invalid data */
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113 | 27c7ca7e | bellard | assert(0);
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114 | 27c7ca7e | bellard | } |
115 | 27c7ca7e | bellard | dev->address_cycle++; |
116 | 27c7ca7e | bellard | break;
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117 | 27c7ca7e | bellard | default:
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118 | 27c7ca7e | bellard | assert(0);
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119 | 27c7ca7e | bellard | } |
120 | 27c7ca7e | bellard | } |
121 | 27c7ca7e | bellard | |
122 | b1d8e52e | blueswir1 | static uint8_t handle_read(tc58128_dev * dev)
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123 | 27c7ca7e | bellard | { |
124 | 27c7ca7e | bellard | #if 0
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125 | 27c7ca7e | bellard | if (dev->address % 0x100000 == 0)
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126 | 27c7ca7e | bellard | fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
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127 | 27c7ca7e | bellard | #endif
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128 | 27c7ca7e | bellard | return dev->flash_contents[dev->address++];
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129 | 27c7ca7e | bellard | } |
130 | 27c7ca7e | bellard | |
131 | 27c7ca7e | bellard | /* We never mark the device as busy, so interrupts cannot be triggered
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132 | 27c7ca7e | bellard | XXXXX */
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133 | 27c7ca7e | bellard | |
134 | b1d8e52e | blueswir1 | static int tc58128_cb(uint16_t porta, uint16_t portb, |
135 | b1d8e52e | blueswir1 | uint16_t * periph_pdtra, uint16_t * periph_portadir, |
136 | b1d8e52e | blueswir1 | uint16_t * periph_pdtrb, uint16_t * periph_portbdir) |
137 | 27c7ca7e | bellard | { |
138 | 27c7ca7e | bellard | int dev;
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139 | 27c7ca7e | bellard | |
140 | 27c7ca7e | bellard | if ((porta & CE1) == 0) |
141 | 27c7ca7e | bellard | dev = 0;
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142 | 27c7ca7e | bellard | else if ((porta & CE2) == 0) |
143 | 27c7ca7e | bellard | dev = 1;
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144 | 27c7ca7e | bellard | else
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145 | 27c7ca7e | bellard | return 0; /* No device selected */ |
146 | 27c7ca7e | bellard | |
147 | 27c7ca7e | bellard | if ((porta & RE) && (porta & WE)) {
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148 | 27c7ca7e | bellard | /* Nothing to do, assert ready and return to input state */
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149 | 27c7ca7e | bellard | *periph_portadir &= 0xff00;
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150 | 27c7ca7e | bellard | *periph_portadir |= RDY(dev); |
151 | 27c7ca7e | bellard | *periph_pdtra |= RDY(dev); |
152 | 27c7ca7e | bellard | return 1; |
153 | 27c7ca7e | bellard | } |
154 | 27c7ca7e | bellard | |
155 | 27c7ca7e | bellard | if (porta & CLE) {
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156 | 27c7ca7e | bellard | /* Command */
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157 | 27c7ca7e | bellard | assert((porta & WE) == 0);
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158 | 27c7ca7e | bellard | handle_command(&tc58128_devs[dev], porta & 0x00ff);
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159 | 27c7ca7e | bellard | } else if (porta & ALE) { |
160 | 27c7ca7e | bellard | assert((porta & WE) == 0);
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161 | 27c7ca7e | bellard | handle_address(&tc58128_devs[dev], porta & 0x00ff);
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162 | 27c7ca7e | bellard | } else if ((porta & RE) == 0) { |
163 | 27c7ca7e | bellard | *periph_portadir |= 0x00ff;
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164 | 27c7ca7e | bellard | *periph_pdtra &= 0xff00;
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165 | 27c7ca7e | bellard | *periph_pdtra |= handle_read(&tc58128_devs[dev]); |
166 | 27c7ca7e | bellard | } else {
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167 | 27c7ca7e | bellard | assert(0);
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168 | 27c7ca7e | bellard | } |
169 | 27c7ca7e | bellard | return 1; |
170 | 27c7ca7e | bellard | } |
171 | 27c7ca7e | bellard | |
172 | 27c7ca7e | bellard | static sh7750_io_device tc58128 = {
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173 | 27c7ca7e | bellard | RE | WE, /* Port A triggers */
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174 | 27c7ca7e | bellard | 0, /* Port B triggers */ |
175 | 27c7ca7e | bellard | tc58128_cb /* Callback */
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176 | 27c7ca7e | bellard | }; |
177 | 27c7ca7e | bellard | |
178 | 7ccfb2eb | blueswir1 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) |
179 | 27c7ca7e | bellard | { |
180 | 27c7ca7e | bellard | init_dev(&tc58128_devs[0], zone1);
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181 | 27c7ca7e | bellard | init_dev(&tc58128_devs[1], zone2);
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182 | 27c7ca7e | bellard | return sh7750_register_io_device(s, &tc58128);
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183 | 27c7ca7e | bellard | } |