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1 | e33d8cdb | balrog | /*
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2 | e33d8cdb | balrog | * Copyright (c) 2006-2008 Openedhand Ltd.
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3 | e33d8cdb | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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4 | e33d8cdb | balrog | *
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5 | e33d8cdb | balrog | * This program is free software; you can redistribute it and/or
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6 | e33d8cdb | balrog | * modify it under the terms of the GNU General Public License as
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7 | e33d8cdb | balrog | * published by the Free Software Foundation; either version 2 or
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8 | e33d8cdb | balrog | * (at your option) version 3 of the License.
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9 | e33d8cdb | balrog | *
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10 | e33d8cdb | balrog | * This program is distributed in the hope that it will be useful,
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11 | e33d8cdb | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | e33d8cdb | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 | e33d8cdb | balrog | * GNU General Public License for more details.
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14 | e33d8cdb | balrog | *
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15 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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16 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
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17 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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18 | e33d8cdb | balrog | */
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19 | e33d8cdb | balrog | #include "hw.h" |
20 | e33d8cdb | balrog | #include "pxa.h" |
21 | e33d8cdb | balrog | #include "sharpsl.h" |
22 | e33d8cdb | balrog | |
23 | e33d8cdb | balrog | #undef REG_FMT
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24 | e33d8cdb | balrog | #if TARGET_PHYS_ADDR_BITS == 32 |
25 | e33d8cdb | balrog | #define REG_FMT "0x%02x" |
26 | e33d8cdb | balrog | #else
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27 | e33d8cdb | balrog | #define REG_FMT "0x%02lx" |
28 | e33d8cdb | balrog | #endif
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29 | e33d8cdb | balrog | |
30 | e33d8cdb | balrog | /* SCOOP devices */
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31 | e33d8cdb | balrog | |
32 | e33d8cdb | balrog | struct scoop_info_s {
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33 | e33d8cdb | balrog | qemu_irq handler[16];
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34 | e33d8cdb | balrog | qemu_irq *in; |
35 | e33d8cdb | balrog | uint16_t status; |
36 | e33d8cdb | balrog | uint16_t power; |
37 | e33d8cdb | balrog | uint32_t gpio_level; |
38 | e33d8cdb | balrog | uint32_t gpio_dir; |
39 | e33d8cdb | balrog | uint32_t prev_level; |
40 | e33d8cdb | balrog | |
41 | e33d8cdb | balrog | uint16_t mcr; |
42 | e33d8cdb | balrog | uint16_t cdr; |
43 | e33d8cdb | balrog | uint16_t ccr; |
44 | e33d8cdb | balrog | uint16_t irr; |
45 | e33d8cdb | balrog | uint16_t imr; |
46 | e33d8cdb | balrog | uint16_t isr; |
47 | e33d8cdb | balrog | }; |
48 | e33d8cdb | balrog | |
49 | e33d8cdb | balrog | #define SCOOP_MCR 0x00 |
50 | e33d8cdb | balrog | #define SCOOP_CDR 0x04 |
51 | e33d8cdb | balrog | #define SCOOP_CSR 0x08 |
52 | e33d8cdb | balrog | #define SCOOP_CPR 0x0c |
53 | e33d8cdb | balrog | #define SCOOP_CCR 0x10 |
54 | e33d8cdb | balrog | #define SCOOP_IRR_IRM 0x14 |
55 | e33d8cdb | balrog | #define SCOOP_IMR 0x18 |
56 | e33d8cdb | balrog | #define SCOOP_ISR 0x1c |
57 | e33d8cdb | balrog | #define SCOOP_GPCR 0x20 |
58 | e33d8cdb | balrog | #define SCOOP_GPWR 0x24 |
59 | e33d8cdb | balrog | #define SCOOP_GPRR 0x28 |
60 | e33d8cdb | balrog | |
61 | e33d8cdb | balrog | static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { |
62 | e33d8cdb | balrog | uint32_t level, diff; |
63 | e33d8cdb | balrog | int bit;
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64 | e33d8cdb | balrog | level = s->gpio_level & s->gpio_dir; |
65 | e33d8cdb | balrog | |
66 | e33d8cdb | balrog | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
67 | e33d8cdb | balrog | bit = ffs(diff) - 1;
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68 | e33d8cdb | balrog | qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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69 | e33d8cdb | balrog | } |
70 | e33d8cdb | balrog | |
71 | e33d8cdb | balrog | s->prev_level = level; |
72 | e33d8cdb | balrog | } |
73 | e33d8cdb | balrog | |
74 | e33d8cdb | balrog | static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) |
75 | e33d8cdb | balrog | { |
76 | e33d8cdb | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
77 | e33d8cdb | balrog | |
78 | e33d8cdb | balrog | switch (addr) {
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79 | e33d8cdb | balrog | case SCOOP_MCR:
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80 | e33d8cdb | balrog | return s->mcr;
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81 | e33d8cdb | balrog | case SCOOP_CDR:
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82 | e33d8cdb | balrog | return s->cdr;
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83 | e33d8cdb | balrog | case SCOOP_CSR:
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84 | e33d8cdb | balrog | return s->status;
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85 | e33d8cdb | balrog | case SCOOP_CPR:
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86 | e33d8cdb | balrog | return s->power;
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87 | e33d8cdb | balrog | case SCOOP_CCR:
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88 | e33d8cdb | balrog | return s->ccr;
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89 | e33d8cdb | balrog | case SCOOP_IRR_IRM:
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90 | e33d8cdb | balrog | return s->irr;
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91 | e33d8cdb | balrog | case SCOOP_IMR:
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92 | e33d8cdb | balrog | return s->imr;
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93 | e33d8cdb | balrog | case SCOOP_ISR:
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94 | e33d8cdb | balrog | return s->isr;
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95 | e33d8cdb | balrog | case SCOOP_GPCR:
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96 | e33d8cdb | balrog | return s->gpio_dir;
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97 | e33d8cdb | balrog | case SCOOP_GPWR:
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98 | e33d8cdb | balrog | case SCOOP_GPRR:
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99 | 1f163b14 | balrog | return s->gpio_level;
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100 | e33d8cdb | balrog | default:
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101 | e33d8cdb | balrog | zaurus_printf("Bad register offset " REG_FMT "\n", addr); |
102 | e33d8cdb | balrog | } |
103 | e33d8cdb | balrog | |
104 | e33d8cdb | balrog | return 0; |
105 | e33d8cdb | balrog | } |
106 | e33d8cdb | balrog | |
107 | e33d8cdb | balrog | static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
108 | e33d8cdb | balrog | { |
109 | e33d8cdb | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
110 | e33d8cdb | balrog | value &= 0xffff;
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111 | e33d8cdb | balrog | |
112 | e33d8cdb | balrog | switch (addr) {
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113 | e33d8cdb | balrog | case SCOOP_MCR:
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114 | e33d8cdb | balrog | s->mcr = value; |
115 | e33d8cdb | balrog | break;
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116 | e33d8cdb | balrog | case SCOOP_CDR:
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117 | e33d8cdb | balrog | s->cdr = value; |
118 | e33d8cdb | balrog | break;
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119 | e33d8cdb | balrog | case SCOOP_CPR:
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120 | e33d8cdb | balrog | s->power = value; |
121 | e33d8cdb | balrog | if (value & 0x80) |
122 | e33d8cdb | balrog | s->power |= 0x8040;
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123 | e33d8cdb | balrog | break;
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124 | e33d8cdb | balrog | case SCOOP_CCR:
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125 | e33d8cdb | balrog | s->ccr = value; |
126 | e33d8cdb | balrog | break;
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127 | e33d8cdb | balrog | case SCOOP_IRR_IRM:
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128 | e33d8cdb | balrog | s->irr = value; |
129 | e33d8cdb | balrog | break;
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130 | e33d8cdb | balrog | case SCOOP_IMR:
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131 | e33d8cdb | balrog | s->imr = value; |
132 | e33d8cdb | balrog | break;
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133 | e33d8cdb | balrog | case SCOOP_ISR:
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134 | e33d8cdb | balrog | s->isr = value; |
135 | e33d8cdb | balrog | break;
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136 | e33d8cdb | balrog | case SCOOP_GPCR:
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137 | e33d8cdb | balrog | s->gpio_dir = value; |
138 | e33d8cdb | balrog | scoop_gpio_handler_update(s); |
139 | e33d8cdb | balrog | break;
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140 | e33d8cdb | balrog | case SCOOP_GPWR:
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141 | 1f163b14 | balrog | case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ |
142 | e33d8cdb | balrog | s->gpio_level = value & s->gpio_dir; |
143 | e33d8cdb | balrog | scoop_gpio_handler_update(s); |
144 | e33d8cdb | balrog | break;
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145 | e33d8cdb | balrog | default:
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146 | e33d8cdb | balrog | zaurus_printf("Bad register offset " REG_FMT "\n", addr); |
147 | e33d8cdb | balrog | } |
148 | e33d8cdb | balrog | } |
149 | e33d8cdb | balrog | |
150 | b1d8e52e | blueswir1 | static CPUReadMemoryFunc *scoop_readfn[] = {
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151 | e33d8cdb | balrog | scoop_readb, |
152 | e33d8cdb | balrog | scoop_readb, |
153 | e33d8cdb | balrog | scoop_readb, |
154 | e33d8cdb | balrog | }; |
155 | b1d8e52e | blueswir1 | static CPUWriteMemoryFunc *scoop_writefn[] = {
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156 | e33d8cdb | balrog | scoop_writeb, |
157 | e33d8cdb | balrog | scoop_writeb, |
158 | e33d8cdb | balrog | scoop_writeb, |
159 | e33d8cdb | balrog | }; |
160 | e33d8cdb | balrog | |
161 | e33d8cdb | balrog | void scoop_gpio_set(void *opaque, int line, int level) |
162 | e33d8cdb | balrog | { |
163 | e33d8cdb | balrog | struct scoop_info_s *s = (struct scoop_info_s *) s; |
164 | e33d8cdb | balrog | |
165 | e33d8cdb | balrog | if (level)
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166 | e33d8cdb | balrog | s->gpio_level |= (1 << line);
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167 | e33d8cdb | balrog | else
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168 | e33d8cdb | balrog | s->gpio_level &= ~(1 << line);
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169 | e33d8cdb | balrog | } |
170 | e33d8cdb | balrog | |
171 | e33d8cdb | balrog | qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
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172 | e33d8cdb | balrog | { |
173 | e33d8cdb | balrog | return s->in;
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174 | e33d8cdb | balrog | } |
175 | e33d8cdb | balrog | |
176 | e33d8cdb | balrog | void scoop_gpio_out_set(struct scoop_info_s *s, int line, |
177 | e33d8cdb | balrog | qemu_irq handler) { |
178 | e33d8cdb | balrog | if (line >= 16) { |
179 | e33d8cdb | balrog | fprintf(stderr, "No GPIO pin %i\n", line);
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180 | e33d8cdb | balrog | exit(-1);
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181 | e33d8cdb | balrog | } |
182 | e33d8cdb | balrog | |
183 | e33d8cdb | balrog | s->handler[line] = handler; |
184 | e33d8cdb | balrog | } |
185 | e33d8cdb | balrog | |
186 | e33d8cdb | balrog | static void scoop_save(QEMUFile *f, void *opaque) |
187 | e33d8cdb | balrog | { |
188 | e33d8cdb | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
189 | e33d8cdb | balrog | qemu_put_be16s(f, &s->status); |
190 | e33d8cdb | balrog | qemu_put_be16s(f, &s->power); |
191 | e33d8cdb | balrog | qemu_put_be32s(f, &s->gpio_level); |
192 | e33d8cdb | balrog | qemu_put_be32s(f, &s->gpio_dir); |
193 | e33d8cdb | balrog | qemu_put_be32s(f, &s->prev_level); |
194 | e33d8cdb | balrog | qemu_put_be16s(f, &s->mcr); |
195 | e33d8cdb | balrog | qemu_put_be16s(f, &s->cdr); |
196 | e33d8cdb | balrog | qemu_put_be16s(f, &s->ccr); |
197 | e33d8cdb | balrog | qemu_put_be16s(f, &s->irr); |
198 | e33d8cdb | balrog | qemu_put_be16s(f, &s->imr); |
199 | e33d8cdb | balrog | qemu_put_be16s(f, &s->isr); |
200 | e33d8cdb | balrog | } |
201 | e33d8cdb | balrog | |
202 | e33d8cdb | balrog | static int scoop_load(QEMUFile *f, void *opaque, int version_id) |
203 | e33d8cdb | balrog | { |
204 | 1f163b14 | balrog | uint16_t dummy; |
205 | e33d8cdb | balrog | struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
206 | e33d8cdb | balrog | qemu_get_be16s(f, &s->status); |
207 | e33d8cdb | balrog | qemu_get_be16s(f, &s->power); |
208 | e33d8cdb | balrog | qemu_get_be32s(f, &s->gpio_level); |
209 | e33d8cdb | balrog | qemu_get_be32s(f, &s->gpio_dir); |
210 | e33d8cdb | balrog | qemu_get_be32s(f, &s->prev_level); |
211 | e33d8cdb | balrog | qemu_get_be16s(f, &s->mcr); |
212 | e33d8cdb | balrog | qemu_get_be16s(f, &s->cdr); |
213 | e33d8cdb | balrog | qemu_get_be16s(f, &s->ccr); |
214 | e33d8cdb | balrog | qemu_get_be16s(f, &s->irr); |
215 | e33d8cdb | balrog | qemu_get_be16s(f, &s->imr); |
216 | e33d8cdb | balrog | qemu_get_be16s(f, &s->isr); |
217 | 1f163b14 | balrog | if (version_id < 1) |
218 | 1f163b14 | balrog | qemu_get_be16s(f, &dummy); |
219 | e33d8cdb | balrog | |
220 | e33d8cdb | balrog | return 0; |
221 | e33d8cdb | balrog | } |
222 | e33d8cdb | balrog | |
223 | e33d8cdb | balrog | struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu, |
224 | e33d8cdb | balrog | int instance,
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225 | e33d8cdb | balrog | target_phys_addr_t target_base) { |
226 | e33d8cdb | balrog | int iomemtype;
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227 | e33d8cdb | balrog | struct scoop_info_s *s;
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228 | e33d8cdb | balrog | |
229 | e33d8cdb | balrog | s = (struct scoop_info_s *)
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230 | e33d8cdb | balrog | qemu_mallocz(sizeof(struct scoop_info_s)); |
231 | e33d8cdb | balrog | memset(s, 0, sizeof(struct scoop_info_s)); |
232 | e33d8cdb | balrog | |
233 | e33d8cdb | balrog | s->status = 0x02;
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234 | e33d8cdb | balrog | s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
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235 | e33d8cdb | balrog | iomemtype = cpu_register_io_memory(0, scoop_readfn,
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236 | e33d8cdb | balrog | scoop_writefn, s); |
237 | 8da3ff18 | pbrook | cpu_register_physical_memory(target_base, 0x1000, iomemtype);
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238 | 1f163b14 | balrog | register_savevm("scoop", instance, 1, scoop_save, scoop_load, s); |
239 | e33d8cdb | balrog | |
240 | e33d8cdb | balrog | return s;
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241 | e33d8cdb | balrog | } |
242 | e33d8cdb | balrog | |
243 | e33d8cdb | balrog | /* Write the bootloader parameters memory area. */
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244 | e33d8cdb | balrog | |
245 | e33d8cdb | balrog | #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) |
246 | e33d8cdb | balrog | |
247 | b1d8e52e | blueswir1 | static struct __attribute__ ((__packed__)) sl_param_info { |
248 | e33d8cdb | balrog | uint32_t comadj_keyword; |
249 | e33d8cdb | balrog | int32_t comadj; |
250 | e33d8cdb | balrog | |
251 | e33d8cdb | balrog | uint32_t uuid_keyword; |
252 | e33d8cdb | balrog | char uuid[16]; |
253 | e33d8cdb | balrog | |
254 | e33d8cdb | balrog | uint32_t touch_keyword; |
255 | e33d8cdb | balrog | int32_t touch_xp; |
256 | e33d8cdb | balrog | int32_t touch_yp; |
257 | e33d8cdb | balrog | int32_t touch_xd; |
258 | e33d8cdb | balrog | int32_t touch_yd; |
259 | e33d8cdb | balrog | |
260 | e33d8cdb | balrog | uint32_t adadj_keyword; |
261 | e33d8cdb | balrog | int32_t adadj; |
262 | e33d8cdb | balrog | |
263 | e33d8cdb | balrog | uint32_t phad_keyword; |
264 | e33d8cdb | balrog | int32_t phadadj; |
265 | e33d8cdb | balrog | } zaurus_bootparam = { |
266 | e33d8cdb | balrog | .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), |
267 | e33d8cdb | balrog | .comadj = 125,
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268 | e33d8cdb | balrog | .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), |
269 | e33d8cdb | balrog | .uuid = { -1 },
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270 | e33d8cdb | balrog | .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), |
271 | e33d8cdb | balrog | .touch_xp = -1,
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272 | e33d8cdb | balrog | .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), |
273 | e33d8cdb | balrog | .adadj = -1,
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274 | e33d8cdb | balrog | .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), |
275 | e33d8cdb | balrog | .phadadj = 0x01,
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276 | e33d8cdb | balrog | }; |
277 | e33d8cdb | balrog | |
278 | e33d8cdb | balrog | void sl_bootparam_write(uint32_t ptr)
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279 | e33d8cdb | balrog | { |
280 | e33d8cdb | balrog | memcpy(phys_ram_base + ptr, &zaurus_bootparam, |
281 | e33d8cdb | balrog | sizeof(struct sl_param_info)); |
282 | e33d8cdb | balrog | } |