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/*
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* Arm PrimeCell PL181 MultiMedia Card Interface
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "hw.h" |
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#include "primecell.h" |
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#include "sd.h" |
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|
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//#define DEBUG_PL181 1
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|
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#ifdef DEBUG_PL181
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#define DPRINTF(fmt, args...) \
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do { printf("pl181: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while(0) |
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#endif
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#define PL181_FIFO_LEN 16 |
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typedef struct { |
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SDState *card; |
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uint32_t clock; |
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uint32_t power; |
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uint32_t cmdarg; |
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uint32_t cmd; |
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uint32_t datatimer; |
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uint32_t datalength; |
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uint32_t respcmd; |
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uint32_t response[4];
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uint32_t datactrl; |
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uint32_t datacnt; |
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uint32_t status; |
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uint32_t mask[2];
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int fifo_pos;
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int fifo_len;
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/* The linux 2.6.21 driver is buggy, and misbehaves if new data arrives
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while it is reading the FIFO. We hack around this be defering
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subsequent transfers until after the driver polls the status word.
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http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=4446/1
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*/
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int linux_hack;
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uint32_t fifo[PL181_FIFO_LEN]; |
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qemu_irq irq[2];
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} pl181_state; |
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|
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#define PL181_CMD_INDEX 0x3f |
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#define PL181_CMD_RESPONSE (1 << 6) |
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#define PL181_CMD_LONGRESP (1 << 7) |
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#define PL181_CMD_INTERRUPT (1 << 8) |
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#define PL181_CMD_PENDING (1 << 9) |
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#define PL181_CMD_ENABLE (1 << 10) |
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|
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#define PL181_DATA_ENABLE (1 << 0) |
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#define PL181_DATA_DIRECTION (1 << 1) |
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#define PL181_DATA_MODE (1 << 2) |
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#define PL181_DATA_DMAENABLE (1 << 3) |
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|
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#define PL181_STATUS_CMDCRCFAIL (1 << 0) |
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#define PL181_STATUS_DATACRCFAIL (1 << 1) |
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#define PL181_STATUS_CMDTIMEOUT (1 << 2) |
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#define PL181_STATUS_DATATIMEOUT (1 << 3) |
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#define PL181_STATUS_TXUNDERRUN (1 << 4) |
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#define PL181_STATUS_RXOVERRUN (1 << 5) |
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#define PL181_STATUS_CMDRESPEND (1 << 6) |
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#define PL181_STATUS_CMDSENT (1 << 7) |
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#define PL181_STATUS_DATAEND (1 << 8) |
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#define PL181_STATUS_DATABLOCKEND (1 << 10) |
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#define PL181_STATUS_CMDACTIVE (1 << 11) |
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#define PL181_STATUS_TXACTIVE (1 << 12) |
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#define PL181_STATUS_RXACTIVE (1 << 13) |
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#define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14) |
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#define PL181_STATUS_RXFIFOHALFFULL (1 << 15) |
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#define PL181_STATUS_TXFIFOFULL (1 << 16) |
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#define PL181_STATUS_RXFIFOFULL (1 << 17) |
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#define PL181_STATUS_TXFIFOEMPTY (1 << 18) |
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#define PL181_STATUS_RXFIFOEMPTY (1 << 19) |
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#define PL181_STATUS_TXDATAAVLBL (1 << 20) |
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#define PL181_STATUS_RXDATAAVLBL (1 << 21) |
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#define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \
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|PL181_STATUS_TXFIFOHALFEMPTY \ |
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|PL181_STATUS_TXFIFOFULL \ |
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|PL181_STATUS_TXFIFOEMPTY \ |
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|PL181_STATUS_TXDATAAVLBL) |
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#define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \
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|PL181_STATUS_RXFIFOHALFFULL \ |
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|PL181_STATUS_RXFIFOFULL \ |
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|PL181_STATUS_RXFIFOEMPTY \ |
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|PL181_STATUS_RXDATAAVLBL) |
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static const unsigned char pl181_id[] = |
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{ 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
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static void pl181_update(pl181_state *s) |
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{ |
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int i;
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for (i = 0; i < 2; i++) { |
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qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);
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} |
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} |
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static void pl181_fifo_push(pl181_state *s, uint32_t value) |
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{ |
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int n;
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if (s->fifo_len == PL181_FIFO_LEN) {
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fprintf(stderr, "pl181: FIFO overflow\n");
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return;
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} |
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n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1);
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s->fifo_len++; |
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s->fifo[n] = value; |
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DPRINTF("FIFO push %08x\n", (int)value); |
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} |
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static uint32_t pl181_fifo_pop(pl181_state *s)
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{ |
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uint32_t value; |
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if (s->fifo_len == 0) { |
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fprintf(stderr, "pl181: FIFO underflow\n");
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return 0; |
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} |
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value = s->fifo[s->fifo_pos]; |
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s->fifo_len--; |
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s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1); |
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DPRINTF("FIFO pop %08x\n", (int)value); |
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return value;
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} |
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static void pl181_send_command(pl181_state *s) |
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{ |
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struct sd_request_s request;
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uint8_t response[16];
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int rlen;
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request.cmd = s->cmd & PL181_CMD_INDEX; |
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request.arg = s->cmdarg; |
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DPRINTF("Command %d %08x\n", request.cmd, request.arg);
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rlen = sd_do_command(s->card, &request, response); |
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if (rlen < 0) |
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goto error;
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if (s->cmd & PL181_CMD_RESPONSE) {
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#define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \ |
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| (response[n + 2] << 8) | response[n + 3]) |
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if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP))) |
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goto error;
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if (rlen != 4 && rlen != 16) |
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goto error;
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s->response[0] = RWORD(0); |
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if (rlen == 4) { |
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s->response[1] = s->response[2] = s->response[3] = 0; |
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} else {
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s->response[1] = RWORD(4); |
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s->response[2] = RWORD(8); |
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s->response[3] = RWORD(12) & ~1; |
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} |
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DPRINTF("Response received\n");
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s->status |= PL181_STATUS_CMDRESPEND; |
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#undef RWORD
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} else {
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DPRINTF("Command sent\n");
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s->status |= PL181_STATUS_CMDSENT; |
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} |
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return;
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error:
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DPRINTF("Timeout\n");
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s->status |= PL181_STATUS_CMDTIMEOUT; |
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} |
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/* Transfer data between the card and the FIFO. This is complicated by
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the FIFO holding 32-bit words and the card taking data in single byte
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chunks. FIFO bytes are transferred in little-endian order. */
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static void pl181_fifo_run(pl181_state *s) |
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{ |
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uint32_t bits; |
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uint32_t value; |
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int n;
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int limit;
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int is_read;
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is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;
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if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card)) |
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&& !s->linux_hack) { |
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limit = is_read ? PL181_FIFO_LEN : 0;
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n = 0;
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value = 0;
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while (s->datacnt && s->fifo_len != limit) {
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if (is_read) {
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value |= (uint32_t)sd_read_data(s->card) << (n * 8);
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n++; |
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if (n == 4) { |
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pl181_fifo_push(s, value); |
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value = 0;
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n = 0;
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} |
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} else {
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if (n == 0) { |
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value = pl181_fifo_pop(s); |
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n = 4;
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} |
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sd_write_data(s->card, value & 0xff);
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value >>= 8;
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n--; |
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} |
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s->datacnt--; |
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} |
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if (n && is_read) {
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pl181_fifo_push(s, value); |
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} |
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} |
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s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO); |
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if (s->datacnt == 0) { |
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s->status |= PL181_STATUS_DATAEND; |
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/* HACK: */
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s->status |= PL181_STATUS_DATABLOCKEND; |
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DPRINTF("Transfer Complete\n");
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} |
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if (s->datacnt == 0 && s->fifo_len == 0) { |
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s->datactrl &= ~PL181_DATA_ENABLE; |
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DPRINTF("Data engine idle\n");
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} else {
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/* Update FIFO bits. */
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bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE; |
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if (s->fifo_len == 0) { |
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bits |= PL181_STATUS_TXFIFOEMPTY; |
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bits |= PL181_STATUS_RXFIFOEMPTY; |
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} else {
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bits |= PL181_STATUS_TXDATAAVLBL; |
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bits |= PL181_STATUS_RXDATAAVLBL; |
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} |
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if (s->fifo_len == 16) { |
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bits |= PL181_STATUS_TXFIFOFULL; |
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bits |= PL181_STATUS_RXFIFOFULL; |
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} |
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if (s->fifo_len <= 8) { |
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bits |= PL181_STATUS_TXFIFOHALFEMPTY; |
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} |
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if (s->fifo_len >= 8) { |
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bits |= PL181_STATUS_RXFIFOHALFFULL; |
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} |
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if (s->datactrl & PL181_DATA_DIRECTION) {
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bits &= PL181_STATUS_RX_FIFO; |
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} else {
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bits &= PL181_STATUS_TX_FIFO; |
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} |
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s->status |= bits; |
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} |
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} |
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static uint32_t pl181_read(void *opaque, target_phys_addr_t offset) |
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{ |
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pl181_state *s = (pl181_state *)opaque; |
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uint32_t tmp; |
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if (offset >= 0xfe0 && offset < 0x1000) { |
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return pl181_id[(offset - 0xfe0) >> 2]; |
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} |
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switch (offset) {
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case 0x00: /* Power */ |
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return s->power;
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case 0x04: /* Clock */ |
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return s->clock;
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case 0x08: /* Argument */ |
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return s->cmdarg;
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case 0x0c: /* Command */ |
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return s->cmd;
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case 0x10: /* RespCmd */ |
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return s->respcmd;
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case 0x14: /* Response0 */ |
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return s->response[0]; |
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case 0x18: /* Response1 */ |
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return s->response[1]; |
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case 0x1c: /* Response2 */ |
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return s->response[2]; |
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case 0x20: /* Response3 */ |
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return s->response[3]; |
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case 0x24: /* DataTimer */ |
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return s->datatimer;
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case 0x28: /* DataLength */ |
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return s->datalength;
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case 0x2c: /* DataCtrl */ |
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return s->datactrl;
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case 0x30: /* DataCnt */ |
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return s->datacnt;
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case 0x34: /* Status */ |
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tmp = s->status; |
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if (s->linux_hack) {
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s->linux_hack = 0;
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pl181_fifo_run(s); |
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pl181_update(s); |
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} |
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return tmp;
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case 0x3c: /* Mask0 */ |
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return s->mask[0]; |
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case 0x40: /* Mask1 */ |
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return s->mask[1]; |
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case 0x48: /* FifoCnt */ |
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/* The documentation is somewhat vague about exactly what FifoCnt
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does. On real hardware it appears to be when decrememnted
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when a word is transfered between the FIFO and the serial
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data engine. DataCnt is decremented after each byte is
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transfered between the serial engine and the card.
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We don't emulate this level of detail, so both can be the same. */
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tmp = (s->datacnt + 3) >> 2; |
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if (s->linux_hack) {
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s->linux_hack = 0;
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pl181_fifo_run(s); |
316 |
pl181_update(s); |
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} |
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return tmp;
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case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
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case 0x90: case 0x94: case 0x98: case 0x9c: |
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case 0xa0: case 0xa4: case 0xa8: case 0xac: |
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case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
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if (s->fifo_len == 0) { |
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fprintf(stderr, "pl181: Unexpected FIFO read\n");
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return 0; |
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} else {
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uint32_t value; |
328 |
value = pl181_fifo_pop(s); |
329 |
s->linux_hack = 1;
|
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pl181_fifo_run(s); |
331 |
pl181_update(s); |
332 |
return value;
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} |
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default:
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cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset); |
336 |
return 0; |
337 |
} |
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} |
339 |
|
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static void pl181_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
343 |
pl181_state *s = (pl181_state *)opaque; |
344 |
|
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switch (offset) {
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case 0x00: /* Power */ |
347 |
s->power = value & 0xff;
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348 |
break;
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349 |
case 0x04: /* Clock */ |
350 |
s->clock = value & 0xff;
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break;
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case 0x08: /* Argument */ |
353 |
s->cmdarg = value; |
354 |
break;
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case 0x0c: /* Command */ |
356 |
s->cmd = value; |
357 |
if (s->cmd & PL181_CMD_ENABLE) {
|
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if (s->cmd & PL181_CMD_INTERRUPT) {
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fprintf(stderr, "pl181: Interrupt mode not implemented\n");
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abort(); |
361 |
} if (s->cmd & PL181_CMD_PENDING) {
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fprintf(stderr, "pl181: Pending commands not implemented\n");
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abort(); |
364 |
} else {
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pl181_send_command(s); |
366 |
pl181_fifo_run(s); |
367 |
} |
368 |
/* The command has completed one way or the other. */
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s->cmd &= ~PL181_CMD_ENABLE; |
370 |
} |
371 |
break;
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372 |
case 0x24: /* DataTimer */ |
373 |
s->datatimer = value; |
374 |
break;
|
375 |
case 0x28: /* DataLength */ |
376 |
s->datalength = value & 0xffff;
|
377 |
break;
|
378 |
case 0x2c: /* DataCtrl */ |
379 |
s->datactrl = value & 0xff;
|
380 |
if (value & PL181_DATA_ENABLE) {
|
381 |
s->datacnt = s->datalength; |
382 |
pl181_fifo_run(s); |
383 |
} |
384 |
break;
|
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case 0x38: /* Clear */ |
386 |
s->status &= ~(value & 0x7ff);
|
387 |
break;
|
388 |
case 0x3c: /* Mask0 */ |
389 |
s->mask[0] = value;
|
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break;
|
391 |
case 0x40: /* Mask1 */ |
392 |
s->mask[1] = value;
|
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break;
|
394 |
case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
395 |
case 0x90: case 0x94: case 0x98: case 0x9c: |
396 |
case 0xa0: case 0xa4: case 0xa8: case 0xac: |
397 |
case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
398 |
if (s->datacnt == 0) { |
399 |
fprintf(stderr, "pl181: Unexpected FIFO write\n");
|
400 |
} else {
|
401 |
pl181_fifo_push(s, value); |
402 |
pl181_fifo_run(s); |
403 |
} |
404 |
break;
|
405 |
default:
|
406 |
cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset); |
407 |
} |
408 |
pl181_update(s); |
409 |
} |
410 |
|
411 |
static CPUReadMemoryFunc *pl181_readfn[] = {
|
412 |
pl181_read, |
413 |
pl181_read, |
414 |
pl181_read |
415 |
}; |
416 |
|
417 |
static CPUWriteMemoryFunc *pl181_writefn[] = {
|
418 |
pl181_write, |
419 |
pl181_write, |
420 |
pl181_write |
421 |
}; |
422 |
|
423 |
static void pl181_reset(void *opaque) |
424 |
{ |
425 |
pl181_state *s = (pl181_state *)opaque; |
426 |
|
427 |
s->power = 0;
|
428 |
s->cmdarg = 0;
|
429 |
s->cmd = 0;
|
430 |
s->datatimer = 0;
|
431 |
s->datalength = 0;
|
432 |
s->respcmd = 0;
|
433 |
s->response[0] = 0; |
434 |
s->response[1] = 0; |
435 |
s->response[2] = 0; |
436 |
s->response[3] = 0; |
437 |
s->datatimer = 0;
|
438 |
s->datalength = 0;
|
439 |
s->datactrl = 0;
|
440 |
s->datacnt = 0;
|
441 |
s->status = 0;
|
442 |
s->linux_hack = 0;
|
443 |
s->mask[0] = 0; |
444 |
s->mask[1] = 0; |
445 |
} |
446 |
|
447 |
void pl181_init(uint32_t base, BlockDriverState *bd,
|
448 |
qemu_irq irq0, qemu_irq irq1) |
449 |
{ |
450 |
int iomemtype;
|
451 |
pl181_state *s; |
452 |
|
453 |
s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
|
454 |
iomemtype = cpu_register_io_memory(0, pl181_readfn,
|
455 |
pl181_writefn, s); |
456 |
cpu_register_physical_memory(base, 0x00001000, iomemtype);
|
457 |
s->card = sd_init(bd, 0);
|
458 |
s->irq[0] = irq0;
|
459 |
s->irq[1] = irq1;
|
460 |
qemu_register_reset(pl181_reset, s); |
461 |
pl181_reset(s); |
462 |
/* ??? Save/restore. */
|
463 |
} |