root / hw / mips_jazz.c @ b903a0f7
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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU MIPS Jazz support
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3 | 4ce7ff6e | aurel32 | *
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4 | 4ce7ff6e | aurel32 | * Copyright (c) 2007-2008 Hervé Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | 4ce7ff6e | aurel32 | #include "mips.h" |
27 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
28 | 4ce7ff6e | aurel32 | #include "pc.h" |
29 | 4ce7ff6e | aurel32 | #include "isa.h" |
30 | 4ce7ff6e | aurel32 | #include "fdc.h" |
31 | 4ce7ff6e | aurel32 | #include "sysemu.h" |
32 | 4ce7ff6e | aurel32 | #include "audio/audio.h" |
33 | 4ce7ff6e | aurel32 | #include "boards.h" |
34 | 4ce7ff6e | aurel32 | #include "net.h" |
35 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
36 | bba831e8 | Paul Brook | #include "mips-bios.h" |
37 | ca20cf32 | Blue Swirl | #include "loader.h" |
38 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 4ce7ff6e | aurel32 | |
41 | 4ce7ff6e | aurel32 | enum jazz_model_e
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42 | 4ce7ff6e | aurel32 | { |
43 | 4ce7ff6e | aurel32 | JAZZ_MAGNUM, |
44 | c171148c | aurel32 | JAZZ_PICA61, |
45 | 4ce7ff6e | aurel32 | }; |
46 | 4ce7ff6e | aurel32 | |
47 | 4ce7ff6e | aurel32 | static void main_cpu_reset(void *opaque) |
48 | 4ce7ff6e | aurel32 | { |
49 | 4ce7ff6e | aurel32 | CPUState *env = opaque; |
50 | 4ce7ff6e | aurel32 | cpu_reset(env); |
51 | 4ce7ff6e | aurel32 | } |
52 | 4ce7ff6e | aurel32 | |
53 | c227f099 | Anthony Liguori | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
54 | 4ce7ff6e | aurel32 | { |
55 | afcea8cb | Blue Swirl | return cpu_inw(0x71); |
56 | 4ce7ff6e | aurel32 | } |
57 | 4ce7ff6e | aurel32 | |
58 | c227f099 | Anthony Liguori | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
59 | 4ce7ff6e | aurel32 | { |
60 | afcea8cb | Blue Swirl | cpu_outw(0x71, val & 0xff); |
61 | 4ce7ff6e | aurel32 | } |
62 | 4ce7ff6e | aurel32 | |
63 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const rtc_read[3] = { |
64 | 4ce7ff6e | aurel32 | rtc_readb, |
65 | 4ce7ff6e | aurel32 | rtc_readb, |
66 | 4ce7ff6e | aurel32 | rtc_readb, |
67 | 4ce7ff6e | aurel32 | }; |
68 | 4ce7ff6e | aurel32 | |
69 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const rtc_write[3] = { |
70 | 4ce7ff6e | aurel32 | rtc_writeb, |
71 | 4ce7ff6e | aurel32 | rtc_writeb, |
72 | 4ce7ff6e | aurel32 | rtc_writeb, |
73 | 4ce7ff6e | aurel32 | }; |
74 | 4ce7ff6e | aurel32 | |
75 | c227f099 | Anthony Liguori | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
76 | c6945b15 | aurel32 | { |
77 | c6945b15 | aurel32 | /* Nothing to do. That is only to ensure that
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78 | c6945b15 | aurel32 | * the current DMA acknowledge cycle is completed. */
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79 | c6945b15 | aurel32 | } |
80 | c6945b15 | aurel32 | |
81 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dma_dummy_read[3] = { |
82 | c6945b15 | aurel32 | NULL,
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83 | c6945b15 | aurel32 | NULL,
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84 | c6945b15 | aurel32 | NULL,
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85 | c6945b15 | aurel32 | }; |
86 | c6945b15 | aurel32 | |
87 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dma_dummy_write[3] = { |
88 | c6945b15 | aurel32 | dma_dummy_writeb, |
89 | c6945b15 | aurel32 | dma_dummy_writeb, |
90 | c6945b15 | aurel32 | dma_dummy_writeb, |
91 | c6945b15 | aurel32 | }; |
92 | c6945b15 | aurel32 | |
93 | 4ce7ff6e | aurel32 | static void audio_init(qemu_irq *pic) |
94 | 4ce7ff6e | aurel32 | { |
95 | 4ce7ff6e | aurel32 | struct soundhw *c;
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96 | 4ce7ff6e | aurel32 | int audio_enabled = 0; |
97 | 4ce7ff6e | aurel32 | |
98 | 4ce7ff6e | aurel32 | for (c = soundhw; !audio_enabled && c->name; ++c) {
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99 | 4ce7ff6e | aurel32 | audio_enabled = c->enabled; |
100 | 4ce7ff6e | aurel32 | } |
101 | 4ce7ff6e | aurel32 | |
102 | 4ce7ff6e | aurel32 | if (audio_enabled) {
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103 | 0d9acba8 | Paul Brook | for (c = soundhw; c->name; ++c) {
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104 | 0d9acba8 | Paul Brook | if (c->enabled) {
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105 | 0d9acba8 | Paul Brook | if (c->isa) {
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106 | 22d83b14 | Paul Brook | c->init.init_isa(pic); |
107 | 4ce7ff6e | aurel32 | } |
108 | 4ce7ff6e | aurel32 | } |
109 | 4ce7ff6e | aurel32 | } |
110 | 4ce7ff6e | aurel32 | } |
111 | 4ce7ff6e | aurel32 | } |
112 | 4ce7ff6e | aurel32 | |
113 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
114 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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115 | 4ce7ff6e | aurel32 | |
116 | 4556bd8b | Blue Swirl | static void cpu_request_exit(void *opaque, int irq, int level) |
117 | 4556bd8b | Blue Swirl | { |
118 | 4556bd8b | Blue Swirl | CPUState *env = cpu_single_env; |
119 | 4556bd8b | Blue Swirl | |
120 | 4556bd8b | Blue Swirl | if (env && level) {
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121 | 4556bd8b | Blue Swirl | cpu_exit(env); |
122 | 4556bd8b | Blue Swirl | } |
123 | 4556bd8b | Blue Swirl | } |
124 | 4556bd8b | Blue Swirl | |
125 | 4ce7ff6e | aurel32 | static
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126 | c227f099 | Anthony Liguori | void mips_jazz_init (ram_addr_t ram_size,
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127 | 3023f332 | aliguori | const char *cpu_model, |
128 | 4ce7ff6e | aurel32 | enum jazz_model_e jazz_model)
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129 | 4ce7ff6e | aurel32 | { |
130 | 5cea8590 | Paul Brook | char *filename;
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131 | 4ce7ff6e | aurel32 | int bios_size, n;
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132 | 4ce7ff6e | aurel32 | CPUState *env; |
133 | 4ce7ff6e | aurel32 | qemu_irq *rc4030, *i8259; |
134 | c6945b15 | aurel32 | rc4030_dma *dmas; |
135 | 68238a9e | aurel32 | void* rc4030_opaque;
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136 | c6945b15 | aurel32 | int s_rtc, s_dma_dummy;
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137 | a65f56ee | aurel32 | NICInfo *nd; |
138 | 4ce7ff6e | aurel32 | PITState *pit; |
139 | fd8014e1 | Gerd Hoffmann | DriveInfo *fds[MAX_FD]; |
140 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
141 | 4556bd8b | Blue Swirl | qemu_irq *cpu_exit_irq; |
142 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
143 | c227f099 | Anthony Liguori | ram_addr_t bios_offset; |
144 | 4ce7ff6e | aurel32 | |
145 | 4ce7ff6e | aurel32 | /* init CPUs */
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146 | 4ce7ff6e | aurel32 | if (cpu_model == NULL) { |
147 | 4ce7ff6e | aurel32 | #ifdef TARGET_MIPS64
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148 | 4ce7ff6e | aurel32 | cpu_model = "R4000";
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149 | 4ce7ff6e | aurel32 | #else
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150 | 4ce7ff6e | aurel32 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
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151 | 4ce7ff6e | aurel32 | cpu_model = "24Kf";
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152 | 4ce7ff6e | aurel32 | #endif
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153 | 4ce7ff6e | aurel32 | } |
154 | 4ce7ff6e | aurel32 | env = cpu_init(cpu_model); |
155 | 4ce7ff6e | aurel32 | if (!env) {
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156 | 4ce7ff6e | aurel32 | fprintf(stderr, "Unable to find CPU definition\n");
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157 | 4ce7ff6e | aurel32 | exit(1);
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158 | 4ce7ff6e | aurel32 | } |
159 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, env); |
160 | 4ce7ff6e | aurel32 | |
161 | 4ce7ff6e | aurel32 | /* allocate RAM */
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162 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size); |
163 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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164 | dcac9679 | pbrook | |
165 | 1724f049 | Alex Williamson | bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
166 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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167 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
168 | dcac9679 | pbrook | cpu_register_physical_memory(0xfff00000LL,
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169 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
170 | 4ce7ff6e | aurel32 | |
171 | 4ce7ff6e | aurel32 | /* load the BIOS image. */
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172 | c6945b15 | aurel32 | if (bios_name == NULL) |
173 | c6945b15 | aurel32 | bios_name = BIOS_FILENAME; |
174 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
175 | 5cea8590 | Paul Brook | if (filename) {
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176 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0xfff00000LL,
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177 | 5cea8590 | Paul Brook | MAGNUM_BIOS_SIZE); |
178 | 5cea8590 | Paul Brook | qemu_free(filename); |
179 | 5cea8590 | Paul Brook | } else {
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180 | 5cea8590 | Paul Brook | bios_size = -1;
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181 | 5cea8590 | Paul Brook | } |
182 | 4ce7ff6e | aurel32 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
183 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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184 | 5cea8590 | Paul Brook | bios_name); |
185 | 4ce7ff6e | aurel32 | exit(1);
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186 | 4ce7ff6e | aurel32 | } |
187 | 4ce7ff6e | aurel32 | |
188 | 4ce7ff6e | aurel32 | /* Init CPU internal devices */
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189 | 4ce7ff6e | aurel32 | cpu_mips_irq_init_cpu(env); |
190 | 4ce7ff6e | aurel32 | cpu_mips_clock_init(env); |
191 | 4ce7ff6e | aurel32 | |
192 | 4ce7ff6e | aurel32 | /* Chipset */
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193 | 68238a9e | aurel32 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
194 | 1eed09cb | Avi Kivity | s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
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195 | c6945b15 | aurel32 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
196 | 4ce7ff6e | aurel32 | |
197 | 4ce7ff6e | aurel32 | /* ISA devices */
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198 | 4ce7ff6e | aurel32 | i8259 = i8259_init(env->irq[4]);
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199 | 5041fccd | Roy Tam | isa_bus_new(NULL);
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200 | 5041fccd | Roy Tam | isa_bus_irqs(i8259); |
201 | 4556bd8b | Blue Swirl | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
202 | 4556bd8b | Blue Swirl | DMA_init(0, cpu_exit_irq);
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203 | 4ce7ff6e | aurel32 | pit = pit_init(0x40, i8259[0]); |
204 | 4ce7ff6e | aurel32 | pcspk_init(pit); |
205 | 4ce7ff6e | aurel32 | |
206 | 4ce7ff6e | aurel32 | /* ISA IO space at 0x90000000 */
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207 | 84108e12 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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208 | 84108e12 | Blue Swirl | isa_mmio_init(0x90000000, 0x01000000, 1); |
209 | 84108e12 | Blue Swirl | #else
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210 | 84108e12 | Blue Swirl | isa_mmio_init(0x90000000, 0x01000000, 0); |
211 | 84108e12 | Blue Swirl | #endif
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212 | 84108e12 | Blue Swirl | |
213 | 4ce7ff6e | aurel32 | isa_mem_base = 0x11000000;
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214 | 4ce7ff6e | aurel32 | |
215 | 4ce7ff6e | aurel32 | /* Video card */
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216 | 4ce7ff6e | aurel32 | switch (jazz_model) {
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217 | 4ce7ff6e | aurel32 | case JAZZ_MAGNUM:
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218 | fbe1b595 | Paul Brook | g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); |
219 | 4ce7ff6e | aurel32 | break;
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220 | c171148c | aurel32 | case JAZZ_PICA61:
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221 | fbe1b595 | Paul Brook | isa_vga_mm_init(0x40000000, 0x60000000, 0); |
222 | c171148c | aurel32 | break;
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223 | 4ce7ff6e | aurel32 | default:
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224 | 4ce7ff6e | aurel32 | break;
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225 | 4ce7ff6e | aurel32 | } |
226 | 4ce7ff6e | aurel32 | |
227 | 4ce7ff6e | aurel32 | /* Network controller */
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228 | a65f56ee | aurel32 | for (n = 0; n < nb_nics; n++) { |
229 | a65f56ee | aurel32 | nd = &nd_table[n]; |
230 | a65f56ee | aurel32 | if (!nd->model)
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231 | 9203f520 | Mark McLoughlin | nd->model = qemu_strdup("dp83932");
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232 | a65f56ee | aurel32 | if (strcmp(nd->model, "dp83932") == 0) { |
233 | a65f56ee | aurel32 | dp83932_init(nd, 0x80001000, 2, rc4030[4], |
234 | a65f56ee | aurel32 | rc4030_opaque, rc4030_dma_memory_rw); |
235 | a65f56ee | aurel32 | break;
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236 | a65f56ee | aurel32 | } else if (strcmp(nd->model, "?") == 0) { |
237 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Supported NICs: dp83932\n");
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238 | a65f56ee | aurel32 | exit(1);
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239 | a65f56ee | aurel32 | } else {
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240 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
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241 | a65f56ee | aurel32 | exit(1);
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242 | a65f56ee | aurel32 | } |
243 | a65f56ee | aurel32 | } |
244 | 4ce7ff6e | aurel32 | |
245 | 4ce7ff6e | aurel32 | /* SCSI adapter */
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246 | cfb9de9c | Paul Brook | esp_init(0x80002000, 0, |
247 | cfb9de9c | Paul Brook | rc4030_dma_read, rc4030_dma_write, dmas[0],
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248 | 73d74342 | Blue Swirl | rc4030[5], &esp_reset, &dma_enable);
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249 | 4ce7ff6e | aurel32 | |
250 | 4ce7ff6e | aurel32 | /* Floppy */
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251 | 4ce7ff6e | aurel32 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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252 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: too many floppy drives\n");
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253 | 4ce7ff6e | aurel32 | exit(1);
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254 | 4ce7ff6e | aurel32 | } |
255 | 4ce7ff6e | aurel32 | for (n = 0; n < MAX_FD; n++) { |
256 | fd8014e1 | Gerd Hoffmann | fds[n] = drive_get(IF_FLOPPY, 0, n);
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257 | 4ce7ff6e | aurel32 | } |
258 | 2091ba23 | Gerd Hoffmann | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
259 | 4ce7ff6e | aurel32 | |
260 | 4ce7ff6e | aurel32 | /* Real time clock */
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261 | 7d932dfd | Jan Kiszka | rtc_init(1980, NULL); |
262 | afcea8cb | Blue Swirl | s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
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263 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
264 | 4ce7ff6e | aurel32 | |
265 | 4ce7ff6e | aurel32 | /* Keyboard (i8042) */
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266 | 4efbe58f | aurel32 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
267 | 4ce7ff6e | aurel32 | |
268 | 4ce7ff6e | aurel32 | /* Serial ports */
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269 | 2d48377a | Blue Swirl | if (serial_hds[0]) { |
270 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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271 | 2d48377a | Blue Swirl | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); |
272 | 2d48377a | Blue Swirl | #else
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273 | 2d48377a | Blue Swirl | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0); |
274 | 2d48377a | Blue Swirl | #endif
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275 | 2d48377a | Blue Swirl | } |
276 | 2d48377a | Blue Swirl | if (serial_hds[1]) { |
277 | 2d48377a | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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278 | 2d48377a | Blue Swirl | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); |
279 | 2d48377a | Blue Swirl | #else
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280 | 2d48377a | Blue Swirl | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0); |
281 | 2d48377a | Blue Swirl | #endif
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282 | 2d48377a | Blue Swirl | } |
283 | 4ce7ff6e | aurel32 | |
284 | 4ce7ff6e | aurel32 | /* Parallel port */
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285 | 4ce7ff6e | aurel32 | if (parallel_hds[0]) |
286 | 4ce7ff6e | aurel32 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); |
287 | 4ce7ff6e | aurel32 | |
288 | 4ce7ff6e | aurel32 | /* Sound card */
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289 | 4ce7ff6e | aurel32 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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290 | 4ce7ff6e | aurel32 | audio_init(i8259); |
291 | 4ce7ff6e | aurel32 | |
292 | 4ce7ff6e | aurel32 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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293 | 4ce7ff6e | aurel32 | ds1225y_init(0x80009000, "nvram"); |
294 | 4ce7ff6e | aurel32 | |
295 | 4ce7ff6e | aurel32 | /* LED indicator */
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296 | 3023f332 | aliguori | jazz_led_init(0x8000f000);
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297 | 4ce7ff6e | aurel32 | } |
298 | 4ce7ff6e | aurel32 | |
299 | 4ce7ff6e | aurel32 | static
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300 | c227f099 | Anthony Liguori | void mips_magnum_init (ram_addr_t ram_size,
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301 | 3023f332 | aliguori | const char *boot_device, |
302 | 4ce7ff6e | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
303 | 4ce7ff6e | aurel32 | const char *initrd_filename, const char *cpu_model) |
304 | 4ce7ff6e | aurel32 | { |
305 | fbe1b595 | Paul Brook | mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM); |
306 | 4ce7ff6e | aurel32 | } |
307 | 4ce7ff6e | aurel32 | |
308 | c171148c | aurel32 | static
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309 | c227f099 | Anthony Liguori | void mips_pica61_init (ram_addr_t ram_size,
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310 | 3023f332 | aliguori | const char *boot_device, |
311 | c171148c | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
312 | c171148c | aurel32 | const char *initrd_filename, const char *cpu_model) |
313 | c171148c | aurel32 | { |
314 | fbe1b595 | Paul Brook | mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61); |
315 | c171148c | aurel32 | } |
316 | c171148c | aurel32 | |
317 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_magnum_machine = {
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318 | eec2743e | ths | .name = "magnum",
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319 | eec2743e | ths | .desc = "MIPS Magnum",
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320 | eec2743e | ths | .init = mips_magnum_init, |
321 | c6945b15 | aurel32 | .use_scsi = 1,
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322 | 4ce7ff6e | aurel32 | }; |
323 | c171148c | aurel32 | |
324 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_pica61_machine = {
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325 | eec2743e | ths | .name = "pica61",
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326 | eec2743e | ths | .desc = "Acer Pica 61",
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327 | eec2743e | ths | .init = mips_pica61_init, |
328 | c6945b15 | aurel32 | .use_scsi = 1,
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329 | c171148c | aurel32 | }; |
330 | f80f9ec9 | Anthony Liguori | |
331 | f80f9ec9 | Anthony Liguori | static void mips_jazz_machine_init(void) |
332 | f80f9ec9 | Anthony Liguori | { |
333 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_magnum_machine); |
334 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_pica61_machine); |
335 | f80f9ec9 | Anthony Liguori | } |
336 | f80f9ec9 | Anthony Liguori | |
337 | f80f9ec9 | Anthony Liguori | machine_init(mips_jazz_machine_init); |