Archipelago » qemu

     /* memory #0 LFB */

     /* memory #1 memory-mapped I/O */

     /* XXX: s->vga.vram_size must be a power of two */

                      PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map);

     if (device_id == CIRRUS_ID_CLGD5446) {

                          PCI_BASE_ADDRESS_SPACE_MEMORY, cirrus_pci_mmio_map);

     }

     return 0;

    d->mmio_index = cpu_register_io_memory(e1000_mmio_read,

            e1000_mmio_write, d);

                           PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);

                           PCI_BASE_ADDRESS_SPACE_IO, ioport_map);

    memmove(d->eeprom_data, e1000_eeprom_template,

    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);

    qemu_register_reset(via_reset, d);

                           PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);

    vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);

    s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,

                                            lsi_ram_writefn, s);

                           PCI_BASE_ADDRESS_SPACE_IO, lsi_io_mapfunc);

                           PCI_BASE_ADDRESS_SPACE_MEMORY, lsi_mmio_mapfunc);

                           PCI_BASE_ADDRESS_SPACE_MEMORY, lsi_ram_mapfunc);

    QTAILQ_INIT(&s->queue);

        pci_conf[0x3d] = 0x00; // no interrupt pin

        /* Register I/O spaces */

                               PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map);

    } else {

        opp = qemu_mallocz(sizeof(openpic_t));

    ohci->state.irq = ohci->pci_dev.irq[0];

    /* TODO: avoid cast below by using dev */

                           PCI_BASE_ADDRESS_SPACE_MEMORY, ohci_mapfunc);

    return 0;

}