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1 | a1bb27b1 | pbrook | /*
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2 | a1bb27b1 | pbrook | * Arm PrimeCell PL181 MultiMedia Card Interface
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3 | a1bb27b1 | pbrook | *
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4 | a1bb27b1 | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | a1bb27b1 | pbrook | * Written by Paul Brook
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6 | a1bb27b1 | pbrook | *
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7 | a1bb27b1 | pbrook | * This code is licenced under the GPL.
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8 | a1bb27b1 | pbrook | */
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9 | a1bb27b1 | pbrook | |
10 | a1bb27b1 | pbrook | #include "vl.h" |
11 | a1bb27b1 | pbrook | #include "sd.h" |
12 | a1bb27b1 | pbrook | |
13 | a1bb27b1 | pbrook | //#define DEBUG_PL181 1
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14 | a1bb27b1 | pbrook | |
15 | a1bb27b1 | pbrook | #ifdef DEBUG_PL181
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16 | a1bb27b1 | pbrook | #define DPRINTF(fmt, args...) \
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17 | a1bb27b1 | pbrook | do { printf("pl181: " fmt , ##args); } while (0) |
18 | a1bb27b1 | pbrook | #else
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19 | a1bb27b1 | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
20 | a1bb27b1 | pbrook | #endif
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21 | a1bb27b1 | pbrook | |
22 | a1bb27b1 | pbrook | #define PL181_FIFO_LEN 16 |
23 | a1bb27b1 | pbrook | |
24 | a1bb27b1 | pbrook | typedef struct { |
25 | 42a10898 | pbrook | SDState *card; |
26 | a1bb27b1 | pbrook | uint32_t base; |
27 | a1bb27b1 | pbrook | uint32_t clock; |
28 | a1bb27b1 | pbrook | uint32_t power; |
29 | a1bb27b1 | pbrook | uint32_t cmdarg; |
30 | a1bb27b1 | pbrook | uint32_t cmd; |
31 | a1bb27b1 | pbrook | uint32_t datatimer; |
32 | a1bb27b1 | pbrook | uint32_t datalength; |
33 | a1bb27b1 | pbrook | uint32_t respcmd; |
34 | a1bb27b1 | pbrook | uint32_t response[4];
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35 | a1bb27b1 | pbrook | uint32_t datactrl; |
36 | a1bb27b1 | pbrook | uint32_t datacnt; |
37 | a1bb27b1 | pbrook | uint32_t status; |
38 | a1bb27b1 | pbrook | uint32_t mask[2];
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39 | a1bb27b1 | pbrook | uint32_t fifocnt; |
40 | a1bb27b1 | pbrook | int fifo_pos;
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41 | a1bb27b1 | pbrook | int fifo_len;
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42 | a1bb27b1 | pbrook | uint32_t fifo[PL181_FIFO_LEN]; |
43 | d537cf6c | pbrook | qemu_irq irq[2];
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44 | a1bb27b1 | pbrook | } pl181_state; |
45 | a1bb27b1 | pbrook | |
46 | a1bb27b1 | pbrook | #define PL181_CMD_INDEX 0x3f |
47 | a1bb27b1 | pbrook | #define PL181_CMD_RESPONSE (1 << 6) |
48 | a1bb27b1 | pbrook | #define PL181_CMD_LONGRESP (1 << 7) |
49 | a1bb27b1 | pbrook | #define PL181_CMD_INTERRUPT (1 << 8) |
50 | a1bb27b1 | pbrook | #define PL181_CMD_PENDING (1 << 9) |
51 | a1bb27b1 | pbrook | #define PL181_CMD_ENABLE (1 << 10) |
52 | a1bb27b1 | pbrook | |
53 | a1bb27b1 | pbrook | #define PL181_DATA_ENABLE (1 << 0) |
54 | a1bb27b1 | pbrook | #define PL181_DATA_DIRECTION (1 << 1) |
55 | a1bb27b1 | pbrook | #define PL181_DATA_MODE (1 << 2) |
56 | a1bb27b1 | pbrook | #define PL181_DATA_DMAENABLE (1 << 3) |
57 | a1bb27b1 | pbrook | |
58 | a1bb27b1 | pbrook | #define PL181_STATUS_CMDCRCFAIL (1 << 0) |
59 | a1bb27b1 | pbrook | #define PL181_STATUS_DATACRCFAIL (1 << 1) |
60 | a1bb27b1 | pbrook | #define PL181_STATUS_CMDTIMEOUT (1 << 2) |
61 | a1bb27b1 | pbrook | #define PL181_STATUS_DATATIMEOUT (1 << 3) |
62 | a1bb27b1 | pbrook | #define PL181_STATUS_TXUNDERRUN (1 << 4) |
63 | a1bb27b1 | pbrook | #define PL181_STATUS_RXOVERRUN (1 << 5) |
64 | a1bb27b1 | pbrook | #define PL181_STATUS_CMDRESPEND (1 << 6) |
65 | a1bb27b1 | pbrook | #define PL181_STATUS_CMDSENT (1 << 7) |
66 | a1bb27b1 | pbrook | #define PL181_STATUS_DATAEND (1 << 8) |
67 | a1bb27b1 | pbrook | #define PL181_STATUS_DATABLOCKEND (1 << 10) |
68 | a1bb27b1 | pbrook | #define PL181_STATUS_CMDACTIVE (1 << 11) |
69 | a1bb27b1 | pbrook | #define PL181_STATUS_TXACTIVE (1 << 12) |
70 | a1bb27b1 | pbrook | #define PL181_STATUS_RXACTIVE (1 << 13) |
71 | a1bb27b1 | pbrook | #define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14) |
72 | a1bb27b1 | pbrook | #define PL181_STATUS_RXFIFOHALFFULL (1 << 15) |
73 | a1bb27b1 | pbrook | #define PL181_STATUS_TXFIFOFULL (1 << 16) |
74 | a1bb27b1 | pbrook | #define PL181_STATUS_RXFIFOFULL (1 << 17) |
75 | a1bb27b1 | pbrook | #define PL181_STATUS_TXFIFOEMPTY (1 << 18) |
76 | a1bb27b1 | pbrook | #define PL181_STATUS_RXFIFOEMPTY (1 << 19) |
77 | a1bb27b1 | pbrook | #define PL181_STATUS_TXDATAAVLBL (1 << 20) |
78 | a1bb27b1 | pbrook | #define PL181_STATUS_RXDATAAVLBL (1 << 21) |
79 | a1bb27b1 | pbrook | |
80 | a1bb27b1 | pbrook | #define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \
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81 | a1bb27b1 | pbrook | |PL181_STATUS_TXFIFOHALFEMPTY \ |
82 | a1bb27b1 | pbrook | |PL181_STATUS_TXFIFOFULL \ |
83 | a1bb27b1 | pbrook | |PL181_STATUS_TXFIFOEMPTY \ |
84 | a1bb27b1 | pbrook | |PL181_STATUS_TXDATAAVLBL) |
85 | a1bb27b1 | pbrook | #define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \
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86 | a1bb27b1 | pbrook | |PL181_STATUS_RXFIFOHALFFULL \ |
87 | a1bb27b1 | pbrook | |PL181_STATUS_RXFIFOFULL \ |
88 | a1bb27b1 | pbrook | |PL181_STATUS_RXFIFOEMPTY \ |
89 | a1bb27b1 | pbrook | |PL181_STATUS_RXDATAAVLBL) |
90 | a1bb27b1 | pbrook | |
91 | a1bb27b1 | pbrook | static const unsigned char pl181_id[] = |
92 | a1bb27b1 | pbrook | { 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
93 | a1bb27b1 | pbrook | |
94 | a1bb27b1 | pbrook | static void pl181_update(pl181_state *s) |
95 | a1bb27b1 | pbrook | { |
96 | a1bb27b1 | pbrook | int i;
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97 | a1bb27b1 | pbrook | for (i = 0; i < 2; i++) { |
98 | d537cf6c | pbrook | qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);
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99 | a1bb27b1 | pbrook | } |
100 | a1bb27b1 | pbrook | } |
101 | a1bb27b1 | pbrook | |
102 | a1bb27b1 | pbrook | static void pl181_fifo_push(pl181_state *s, uint32_t value) |
103 | a1bb27b1 | pbrook | { |
104 | a1bb27b1 | pbrook | int n;
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105 | a1bb27b1 | pbrook | |
106 | a1bb27b1 | pbrook | if (s->fifo_len == PL181_FIFO_LEN) {
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107 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: FIFO overflow\n");
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108 | a1bb27b1 | pbrook | return;
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109 | a1bb27b1 | pbrook | } |
110 | a1bb27b1 | pbrook | n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1);
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111 | a1bb27b1 | pbrook | s->fifo_len++; |
112 | a1bb27b1 | pbrook | s->fifo[n] = value; |
113 | a1bb27b1 | pbrook | DPRINTF("FIFO push %08x\n", (int)value); |
114 | a1bb27b1 | pbrook | } |
115 | a1bb27b1 | pbrook | |
116 | a1bb27b1 | pbrook | static uint32_t pl181_fifo_pop(pl181_state *s)
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117 | a1bb27b1 | pbrook | { |
118 | a1bb27b1 | pbrook | uint32_t value; |
119 | a1bb27b1 | pbrook | |
120 | a1bb27b1 | pbrook | if (s->fifo_len == 0) { |
121 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: FIFO underflow\n");
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122 | a1bb27b1 | pbrook | return 0; |
123 | a1bb27b1 | pbrook | } |
124 | a1bb27b1 | pbrook | value = s->fifo[s->fifo_pos]; |
125 | a1bb27b1 | pbrook | s->fifo_len--; |
126 | a1bb27b1 | pbrook | s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1); |
127 | a1bb27b1 | pbrook | DPRINTF("FIFO pop %08x\n", (int)value); |
128 | a1bb27b1 | pbrook | return value;
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129 | a1bb27b1 | pbrook | } |
130 | a1bb27b1 | pbrook | |
131 | a1bb27b1 | pbrook | static void pl181_send_command(pl181_state *s) |
132 | a1bb27b1 | pbrook | { |
133 | a1bb27b1 | pbrook | struct sd_request_s request;
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134 | a1bb27b1 | pbrook | uint8_t response[16];
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135 | a1bb27b1 | pbrook | int rlen;
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136 | a1bb27b1 | pbrook | |
137 | a1bb27b1 | pbrook | request.cmd = s->cmd & PL181_CMD_INDEX; |
138 | a1bb27b1 | pbrook | request.arg = s->cmdarg; |
139 | a1bb27b1 | pbrook | DPRINTF("Command %d %08x\n", request.cmd, request.arg);
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140 | a1bb27b1 | pbrook | rlen = sd_do_command(s->card, &request, response); |
141 | a1bb27b1 | pbrook | if (rlen < 0) |
142 | a1bb27b1 | pbrook | goto error;
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143 | a1bb27b1 | pbrook | if (s->cmd & PL181_CMD_RESPONSE) {
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144 | a1bb27b1 | pbrook | #define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \ |
145 | a1bb27b1 | pbrook | | (response[n + 2] << 8) | response[n + 3]) |
146 | a1bb27b1 | pbrook | if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP))) |
147 | a1bb27b1 | pbrook | goto error;
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148 | a1bb27b1 | pbrook | if (rlen != 4 && rlen != 16) |
149 | a1bb27b1 | pbrook | goto error;
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150 | a1bb27b1 | pbrook | s->response[0] = RWORD(0); |
151 | a1bb27b1 | pbrook | if (rlen == 4) { |
152 | a1bb27b1 | pbrook | s->response[1] = s->response[2] = s->response[3] = 0; |
153 | a1bb27b1 | pbrook | } else {
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154 | a1bb27b1 | pbrook | s->response[1] = RWORD(4); |
155 | a1bb27b1 | pbrook | s->response[2] = RWORD(8); |
156 | a1bb27b1 | pbrook | s->response[3] = RWORD(12) & ~1; |
157 | a1bb27b1 | pbrook | } |
158 | a1bb27b1 | pbrook | DPRINTF("Response recieved\n");
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159 | a1bb27b1 | pbrook | s->status |= PL181_STATUS_CMDRESPEND; |
160 | a1bb27b1 | pbrook | #undef RWORD
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161 | a1bb27b1 | pbrook | } else {
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162 | a1bb27b1 | pbrook | DPRINTF("Command sent\n");
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163 | a1bb27b1 | pbrook | s->status |= PL181_STATUS_CMDSENT; |
164 | a1bb27b1 | pbrook | } |
165 | a1bb27b1 | pbrook | return;
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166 | a1bb27b1 | pbrook | |
167 | a1bb27b1 | pbrook | error:
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168 | a1bb27b1 | pbrook | DPRINTF("Timeout\n");
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169 | a1bb27b1 | pbrook | s->status |= PL181_STATUS_CMDTIMEOUT; |
170 | a1bb27b1 | pbrook | } |
171 | a1bb27b1 | pbrook | |
172 | a1bb27b1 | pbrook | /* Transfer data between teh card and the FIFO. This is complicated by
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173 | a1bb27b1 | pbrook | the FIFO holding 32-bit words and the card taking data in single byte
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174 | a1bb27b1 | pbrook | chunks. FIFO bytes are transferred in little-endian order. */
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175 | a1bb27b1 | pbrook | |
176 | a1bb27b1 | pbrook | static void pl181_fifo_run(pl181_state *s) |
177 | a1bb27b1 | pbrook | { |
178 | a1bb27b1 | pbrook | uint32_t bits; |
179 | a1bb27b1 | pbrook | uint32_t value; |
180 | a1bb27b1 | pbrook | int n;
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181 | a1bb27b1 | pbrook | int limit;
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182 | a1bb27b1 | pbrook | int is_read;
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183 | a1bb27b1 | pbrook | |
184 | a1bb27b1 | pbrook | is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;
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185 | a1bb27b1 | pbrook | if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card))) { |
186 | a1bb27b1 | pbrook | limit = is_read ? PL181_FIFO_LEN : 0;
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187 | a1bb27b1 | pbrook | n = 0;
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188 | a1bb27b1 | pbrook | value = 0;
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189 | a1bb27b1 | pbrook | while (s->datacnt && s->fifo_len != limit) {
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190 | a1bb27b1 | pbrook | if (is_read) {
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191 | a1bb27b1 | pbrook | value |= (uint32_t)sd_read_data(s->card) << (n * 8);
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192 | a1bb27b1 | pbrook | n++; |
193 | a1bb27b1 | pbrook | if (n == 4) { |
194 | a1bb27b1 | pbrook | pl181_fifo_push(s, value); |
195 | a1bb27b1 | pbrook | value = 0;
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196 | a1bb27b1 | pbrook | n = 0;
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197 | a1bb27b1 | pbrook | } |
198 | a1bb27b1 | pbrook | } else {
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199 | a1bb27b1 | pbrook | if (n == 0) { |
200 | a1bb27b1 | pbrook | value = pl181_fifo_pop(s); |
201 | a1bb27b1 | pbrook | n = 4;
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202 | a1bb27b1 | pbrook | } |
203 | a1bb27b1 | pbrook | sd_write_data(s->card, value & 0xff);
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204 | a1bb27b1 | pbrook | value >>= 8;
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205 | a1bb27b1 | pbrook | n--; |
206 | a1bb27b1 | pbrook | } |
207 | a1bb27b1 | pbrook | s->datacnt--; |
208 | a1bb27b1 | pbrook | } |
209 | a1bb27b1 | pbrook | if (n && is_read) {
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210 | a1bb27b1 | pbrook | pl181_fifo_push(s, value); |
211 | a1bb27b1 | pbrook | } |
212 | a1bb27b1 | pbrook | } |
213 | a1bb27b1 | pbrook | s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO); |
214 | a1bb27b1 | pbrook | if (s->datacnt == 0) { |
215 | a1bb27b1 | pbrook | s->status |= PL181_STATUS_DATAEND; |
216 | a1bb27b1 | pbrook | /* HACK: */
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217 | a1bb27b1 | pbrook | s->status |= PL181_STATUS_DATABLOCKEND; |
218 | a1bb27b1 | pbrook | DPRINTF("Transfer Complete\n");
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219 | a1bb27b1 | pbrook | } |
220 | a1bb27b1 | pbrook | if (s->datacnt == 0 && s->fifocnt == 0) { |
221 | a1bb27b1 | pbrook | s->datactrl &= ~PL181_DATA_ENABLE; |
222 | a1bb27b1 | pbrook | DPRINTF("Data engine idle\n");
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223 | a1bb27b1 | pbrook | } else {
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224 | a1bb27b1 | pbrook | /* Update FIFO bits. */
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225 | a1bb27b1 | pbrook | bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE; |
226 | a1bb27b1 | pbrook | if (s->fifo_len == 0) { |
227 | a1bb27b1 | pbrook | bits |= PL181_STATUS_TXFIFOEMPTY; |
228 | a1bb27b1 | pbrook | bits |= PL181_STATUS_RXFIFOEMPTY; |
229 | a1bb27b1 | pbrook | } else {
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230 | a1bb27b1 | pbrook | bits |= PL181_STATUS_TXDATAAVLBL; |
231 | a1bb27b1 | pbrook | bits |= PL181_STATUS_RXDATAAVLBL; |
232 | a1bb27b1 | pbrook | } |
233 | a1bb27b1 | pbrook | if (s->fifo_len == 16) { |
234 | a1bb27b1 | pbrook | bits |= PL181_STATUS_TXFIFOFULL; |
235 | a1bb27b1 | pbrook | bits |= PL181_STATUS_RXFIFOFULL; |
236 | a1bb27b1 | pbrook | } |
237 | a1bb27b1 | pbrook | if (s->fifo_len <= 8) { |
238 | a1bb27b1 | pbrook | bits |= PL181_STATUS_TXFIFOHALFEMPTY; |
239 | a1bb27b1 | pbrook | } |
240 | a1bb27b1 | pbrook | if (s->fifo_len >= 8) { |
241 | a1bb27b1 | pbrook | bits |= PL181_STATUS_RXFIFOHALFFULL; |
242 | a1bb27b1 | pbrook | } |
243 | a1bb27b1 | pbrook | if (s->datactrl & PL181_DATA_DIRECTION) {
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244 | a1bb27b1 | pbrook | bits &= PL181_STATUS_RX_FIFO; |
245 | a1bb27b1 | pbrook | } else {
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246 | a1bb27b1 | pbrook | bits &= PL181_STATUS_TX_FIFO; |
247 | a1bb27b1 | pbrook | } |
248 | a1bb27b1 | pbrook | s->status |= bits; |
249 | a1bb27b1 | pbrook | } |
250 | a1bb27b1 | pbrook | } |
251 | a1bb27b1 | pbrook | |
252 | a1bb27b1 | pbrook | static uint32_t pl181_read(void *opaque, target_phys_addr_t offset) |
253 | a1bb27b1 | pbrook | { |
254 | a1bb27b1 | pbrook | pl181_state *s = (pl181_state *)opaque; |
255 | a1bb27b1 | pbrook | |
256 | a1bb27b1 | pbrook | offset -= s->base; |
257 | a1bb27b1 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) { |
258 | a1bb27b1 | pbrook | return pl181_id[(offset - 0xfe0) >> 2]; |
259 | a1bb27b1 | pbrook | } |
260 | a1bb27b1 | pbrook | switch (offset) {
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261 | a1bb27b1 | pbrook | case 0x00: /* Power */ |
262 | a1bb27b1 | pbrook | return s->power;
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263 | a1bb27b1 | pbrook | case 0x04: /* Clock */ |
264 | a1bb27b1 | pbrook | return s->clock;
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265 | a1bb27b1 | pbrook | case 0x08: /* Argument */ |
266 | a1bb27b1 | pbrook | return s->cmdarg;
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267 | a1bb27b1 | pbrook | case 0x0c: /* Command */ |
268 | a1bb27b1 | pbrook | return s->cmd;
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269 | a1bb27b1 | pbrook | case 0x10: /* RespCmd */ |
270 | a1bb27b1 | pbrook | return s->respcmd;
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271 | a1bb27b1 | pbrook | case 0x14: /* Response0 */ |
272 | a1bb27b1 | pbrook | return s->response[0]; |
273 | a1bb27b1 | pbrook | case 0x18: /* Response1 */ |
274 | a1bb27b1 | pbrook | return s->response[1]; |
275 | a1bb27b1 | pbrook | case 0x1c: /* Response2 */ |
276 | a1bb27b1 | pbrook | return s->response[2]; |
277 | a1bb27b1 | pbrook | case 0x20: /* Response3 */ |
278 | a1bb27b1 | pbrook | return s->response[3]; |
279 | a1bb27b1 | pbrook | case 0x24: /* DataTimer */ |
280 | a1bb27b1 | pbrook | return s->datatimer;
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281 | a1bb27b1 | pbrook | case 0x28: /* DataLength */ |
282 | a1bb27b1 | pbrook | return s->datalength;
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283 | a1bb27b1 | pbrook | case 0x2c: /* DataCtrl */ |
284 | a1bb27b1 | pbrook | return s->datactrl;
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285 | a1bb27b1 | pbrook | case 0x30: /* DataCnt */ |
286 | a1bb27b1 | pbrook | return s->datacnt;
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287 | a1bb27b1 | pbrook | case 0x34: /* Status */ |
288 | a1bb27b1 | pbrook | return s->status;
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289 | a1bb27b1 | pbrook | case 0x3c: /* Mask0 */ |
290 | a1bb27b1 | pbrook | return s->mask[0]; |
291 | a1bb27b1 | pbrook | case 0x40: /* Mask1 */ |
292 | a1bb27b1 | pbrook | return s->mask[1]; |
293 | a1bb27b1 | pbrook | case 0x48: /* FifoCnt */ |
294 | a1bb27b1 | pbrook | return s->fifocnt;
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295 | a1bb27b1 | pbrook | case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
296 | a1bb27b1 | pbrook | case 0x90: case 0x94: case 0x98: case 0x9c: |
297 | a1bb27b1 | pbrook | case 0xa0: case 0xa4: case 0xa8: case 0xac: |
298 | a1bb27b1 | pbrook | case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
299 | a1bb27b1 | pbrook | if (s->fifocnt == 0) { |
300 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: Unexpected FIFO read\n");
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301 | a1bb27b1 | pbrook | return 0; |
302 | a1bb27b1 | pbrook | } else {
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303 | a1bb27b1 | pbrook | uint32_t value; |
304 | a1bb27b1 | pbrook | s->fifocnt--; |
305 | a1bb27b1 | pbrook | value = pl181_fifo_pop(s); |
306 | a1bb27b1 | pbrook | pl181_fifo_run(s); |
307 | a1bb27b1 | pbrook | pl181_update(s); |
308 | a1bb27b1 | pbrook | return value;
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309 | a1bb27b1 | pbrook | } |
310 | a1bb27b1 | pbrook | default:
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311 | a1bb27b1 | pbrook | cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
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312 | a1bb27b1 | pbrook | return 0; |
313 | a1bb27b1 | pbrook | } |
314 | a1bb27b1 | pbrook | } |
315 | a1bb27b1 | pbrook | |
316 | a1bb27b1 | pbrook | static void pl181_write(void *opaque, target_phys_addr_t offset, |
317 | a1bb27b1 | pbrook | uint32_t value) |
318 | a1bb27b1 | pbrook | { |
319 | a1bb27b1 | pbrook | pl181_state *s = (pl181_state *)opaque; |
320 | a1bb27b1 | pbrook | |
321 | a1bb27b1 | pbrook | offset -= s->base; |
322 | a1bb27b1 | pbrook | switch (offset) {
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323 | a1bb27b1 | pbrook | case 0x00: /* Power */ |
324 | a1bb27b1 | pbrook | s->power = value & 0xff;
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325 | a1bb27b1 | pbrook | break;
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326 | a1bb27b1 | pbrook | case 0x04: /* Clock */ |
327 | a1bb27b1 | pbrook | s->clock = value & 0xff;
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328 | a1bb27b1 | pbrook | break;
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329 | a1bb27b1 | pbrook | case 0x08: /* Argument */ |
330 | a1bb27b1 | pbrook | s->cmdarg = value; |
331 | a1bb27b1 | pbrook | break;
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332 | a1bb27b1 | pbrook | case 0x0c: /* Command */ |
333 | a1bb27b1 | pbrook | s->cmd = value; |
334 | a1bb27b1 | pbrook | if (s->cmd & PL181_CMD_ENABLE) {
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335 | a1bb27b1 | pbrook | if (s->cmd & PL181_CMD_INTERRUPT) {
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336 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: Interrupt mode not implemented\n");
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337 | a1bb27b1 | pbrook | abort(); |
338 | a1bb27b1 | pbrook | } if (s->cmd & PL181_CMD_PENDING) {
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339 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: Pending commands not implemented\n");
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340 | a1bb27b1 | pbrook | abort(); |
341 | a1bb27b1 | pbrook | } else {
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342 | a1bb27b1 | pbrook | pl181_send_command(s); |
343 | a1bb27b1 | pbrook | pl181_fifo_run(s); |
344 | a1bb27b1 | pbrook | } |
345 | a1bb27b1 | pbrook | /* The command has completed one way or the other. */
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346 | a1bb27b1 | pbrook | s->cmd &= ~PL181_CMD_ENABLE; |
347 | a1bb27b1 | pbrook | } |
348 | a1bb27b1 | pbrook | break;
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349 | a1bb27b1 | pbrook | case 0x24: /* DataTimer */ |
350 | a1bb27b1 | pbrook | s->datatimer = value; |
351 | a1bb27b1 | pbrook | break;
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352 | a1bb27b1 | pbrook | case 0x28: /* DataLength */ |
353 | a1bb27b1 | pbrook | s->datalength = value & 0xffff;
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354 | a1bb27b1 | pbrook | break;
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355 | a1bb27b1 | pbrook | case 0x2c: /* DataCtrl */ |
356 | a1bb27b1 | pbrook | s->datactrl = value & 0xff;
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357 | a1bb27b1 | pbrook | if (value & PL181_DATA_ENABLE) {
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358 | a1bb27b1 | pbrook | s->datacnt = s->datalength; |
359 | a1bb27b1 | pbrook | s->fifocnt = (s->datalength + 3) >> 2; |
360 | a1bb27b1 | pbrook | pl181_fifo_run(s); |
361 | a1bb27b1 | pbrook | } |
362 | a1bb27b1 | pbrook | break;
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363 | a1bb27b1 | pbrook | case 0x38: /* Clear */ |
364 | a1bb27b1 | pbrook | s->status &= ~(value & 0x7ff);
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365 | a1bb27b1 | pbrook | break;
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366 | a1bb27b1 | pbrook | case 0x3c: /* Mask0 */ |
367 | a1bb27b1 | pbrook | s->mask[0] = value;
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368 | a1bb27b1 | pbrook | break;
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369 | a1bb27b1 | pbrook | case 0x40: /* Mask1 */ |
370 | a1bb27b1 | pbrook | s->mask[1] = value;
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371 | a1bb27b1 | pbrook | break;
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372 | a1bb27b1 | pbrook | case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
373 | a1bb27b1 | pbrook | case 0x90: case 0x94: case 0x98: case 0x9c: |
374 | a1bb27b1 | pbrook | case 0xa0: case 0xa4: case 0xa8: case 0xac: |
375 | a1bb27b1 | pbrook | case 0xb0: case 0xb4: case 0xb8: case 0xbc: |
376 | a1bb27b1 | pbrook | if (s->fifocnt == 0) { |
377 | a1bb27b1 | pbrook | fprintf(stderr, "pl181: Unexpected FIFO write\n");
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378 | a1bb27b1 | pbrook | } else {
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379 | a1bb27b1 | pbrook | s->fifocnt--; |
380 | a1bb27b1 | pbrook | pl181_fifo_push(s, value); |
381 | a1bb27b1 | pbrook | pl181_fifo_run(s); |
382 | a1bb27b1 | pbrook | } |
383 | a1bb27b1 | pbrook | break;
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384 | a1bb27b1 | pbrook | default:
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385 | a1bb27b1 | pbrook | cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
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386 | a1bb27b1 | pbrook | } |
387 | a1bb27b1 | pbrook | pl181_update(s); |
388 | a1bb27b1 | pbrook | } |
389 | a1bb27b1 | pbrook | |
390 | a1bb27b1 | pbrook | static CPUReadMemoryFunc *pl181_readfn[] = {
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391 | a1bb27b1 | pbrook | pl181_read, |
392 | a1bb27b1 | pbrook | pl181_read, |
393 | a1bb27b1 | pbrook | pl181_read |
394 | a1bb27b1 | pbrook | }; |
395 | a1bb27b1 | pbrook | |
396 | a1bb27b1 | pbrook | static CPUWriteMemoryFunc *pl181_writefn[] = {
|
397 | a1bb27b1 | pbrook | pl181_write, |
398 | a1bb27b1 | pbrook | pl181_write, |
399 | a1bb27b1 | pbrook | pl181_write |
400 | a1bb27b1 | pbrook | }; |
401 | a1bb27b1 | pbrook | |
402 | a1bb27b1 | pbrook | static void pl181_reset(void *opaque) |
403 | a1bb27b1 | pbrook | { |
404 | a1bb27b1 | pbrook | pl181_state *s = (pl181_state *)opaque; |
405 | a1bb27b1 | pbrook | |
406 | a1bb27b1 | pbrook | s->power = 0;
|
407 | a1bb27b1 | pbrook | s->cmdarg = 0;
|
408 | a1bb27b1 | pbrook | s->cmd = 0;
|
409 | a1bb27b1 | pbrook | s->datatimer = 0;
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410 | a1bb27b1 | pbrook | s->datalength = 0;
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411 | a1bb27b1 | pbrook | s->respcmd = 0;
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412 | a1bb27b1 | pbrook | s->response[0] = 0; |
413 | a1bb27b1 | pbrook | s->response[1] = 0; |
414 | a1bb27b1 | pbrook | s->response[2] = 0; |
415 | a1bb27b1 | pbrook | s->response[3] = 0; |
416 | a1bb27b1 | pbrook | s->datatimer = 0;
|
417 | a1bb27b1 | pbrook | s->datalength = 0;
|
418 | a1bb27b1 | pbrook | s->datactrl = 0;
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419 | a1bb27b1 | pbrook | s->datacnt = 0;
|
420 | a1bb27b1 | pbrook | s->status = 0;
|
421 | a1bb27b1 | pbrook | s->mask[0] = 0; |
422 | a1bb27b1 | pbrook | s->mask[1] = 0; |
423 | a1bb27b1 | pbrook | s->fifocnt = 0;
|
424 | a1bb27b1 | pbrook | } |
425 | a1bb27b1 | pbrook | |
426 | a1bb27b1 | pbrook | void pl181_init(uint32_t base, BlockDriverState *bd,
|
427 | d537cf6c | pbrook | qemu_irq irq0, qemu_irq irq1) |
428 | a1bb27b1 | pbrook | { |
429 | a1bb27b1 | pbrook | int iomemtype;
|
430 | a1bb27b1 | pbrook | pl181_state *s; |
431 | a1bb27b1 | pbrook | |
432 | a1bb27b1 | pbrook | s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
|
433 | a1bb27b1 | pbrook | iomemtype = cpu_register_io_memory(0, pl181_readfn,
|
434 | a1bb27b1 | pbrook | pl181_writefn, s); |
435 | a1bb27b1 | pbrook | cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
436 | a1bb27b1 | pbrook | s->base = base; |
437 | a1bb27b1 | pbrook | s->card = sd_init(bd); |
438 | a1bb27b1 | pbrook | s->irq[0] = irq0;
|
439 | a1bb27b1 | pbrook | s->irq[1] = irq1;
|
440 | a1bb27b1 | pbrook | qemu_register_reset(pl181_reset, s); |
441 | a1bb27b1 | pbrook | pl181_reset(s); |
442 | a1bb27b1 | pbrook | /* ??? Save/restore. */
|
443 | a1bb27b1 | pbrook | } |