Revision b9d38e95 hw/omap1.c
| b/hw/omap1.c | ||
|---|---|---|
| 436 | 436 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 437 | 437 |
int offset = addr; |
| 438 | 438 |
int bank_no, line_no; |
| 439 |
struct omap_intr_handler_bank_s *bank = 0;
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| 439 |
struct omap_intr_handler_bank_s *bank = NULL;
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| 440 | 440 |
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| 441 | 441 |
if ((offset & 0xf80) == 0x80) {
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| 442 | 442 |
bank_no = (offset & 0x60) >> 5; |
| ... | ... | |
| 514 | 514 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
| 515 | 515 |
int offset = addr; |
| 516 | 516 |
int bank_no, line_no; |
| 517 |
struct omap_intr_handler_bank_s *bank = 0;
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| 517 |
struct omap_intr_handler_bank_s *bank = NULL;
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| 518 | 518 |
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| 519 | 519 |
if ((offset & 0xf80) == 0x80) {
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| 520 | 520 |
bank_no = (offset & 0x60) >> 5; |
| ... | ... | |
| 4731 | 4731 |
omap_findclk(s, "uart2_ck"), |
| 4732 | 4732 |
omap_findclk(s, "uart2_ck"), |
| 4733 | 4733 |
s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
| 4734 |
serial_hds[0] ? serial_hds[1] : 0);
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| 4734 |
serial_hds[0] ? serial_hds[1] : NULL);
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| 4735 | 4735 |
s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3], |
| 4736 | 4736 |
omap_findclk(s, "uart3_ck"), |
| 4737 | 4737 |
omap_findclk(s, "uart3_ck"), |
| 4738 | 4738 |
s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
| 4739 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
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| 4739 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
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| 4740 | 4740 |
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| 4741 | 4741 |
omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
| 4742 | 4742 |
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
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