Revision ba158029 hw/omap_sx1.c
| b/hw/omap_sx1.c | ||
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| 59 | 59 |
* - 1 RTC |
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*/ |
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static uint32_t static_readb(void *opaque, target_phys_addr_t offset) |
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static uint64_t static_read(void *opaque, target_phys_addr_t offset, |
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unsigned size) |
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{
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uint32_t *val = (uint32_t *) opaque; |
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uint32_t mask = (4 / size) - 1; |
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return *val >> ((offset & 3) << 3); |
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} |
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static uint32_t static_readh(void *opaque, target_phys_addr_t offset) |
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{
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uint32_t *val = (uint32_t *) opaque; |
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return *val >> ((offset & 1) << 3); |
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} |
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static uint32_t static_readw(void *opaque, target_phys_addr_t offset) |
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{
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uint32_t *val = (uint32_t *) opaque; |
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return *val >> ((offset & 0) << 3); |
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return *val >> ((offset & mask) << 3); |
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} |
| 82 | 70 |
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static void static_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value)
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uint64_t value, unsigned size)
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{
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#ifdef SPY |
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printf("%s: value %08lx written at " PA_FMT "\n",
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__FUNCTION__, value, offset);
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printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
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__func__, value, size, (int)offset);
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#endif |
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} |
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static CPUReadMemoryFunc * const static_readfn[] = {
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static_readb, |
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static_readh, |
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static_readw, |
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}; |
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static CPUWriteMemoryFunc * const static_writefn[] = {
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static_write, |
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static_write, |
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static_write, |
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static const MemoryRegionOps static_ops = {
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.read = static_read, |
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.write = static_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
| 103 | 85 |
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#define sdram_size 0x02000000 |
| ... | ... | |
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{
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struct omap_mpu_state_s *cpu; |
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MemoryRegion *address_space = get_system_memory(); |
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int io; |
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MemoryRegion *flash = g_new(MemoryRegion, 1); |
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MemoryRegion *flash_1 = g_new(MemoryRegion, 1); |
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MemoryRegion *cs = g_new(MemoryRegion, 4); |
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static uint32_t cs0val = 0x00213090; |
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static uint32_t cs1val = 0x00215070; |
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static uint32_t cs2val = 0x00001139; |
| ... | ... | |
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cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model); |
| 141 | 125 |
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/* External Flash (EMIFS) */ |
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cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, |
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qemu_ram_alloc(NULL, "omap_sx1.flash0-0", |
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flash_size) | IO_MEM_ROM); |
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io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val, |
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DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, |
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OMAP_CS0_SIZE - flash_size, io); |
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io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val, |
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DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); |
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io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val, |
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DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); |
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memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size); |
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memory_region_set_readonly(flash, true); |
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memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash); |
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memory_region_init_io(&cs[0], &static_ops, &cs0val, |
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"sx1.cs0", OMAP_CS0_SIZE - flash_size); |
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memory_region_add_subregion(address_space, |
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OMAP_CS0_BASE + flash_size, &cs[0]); |
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memory_region_init_io(&cs[2], &static_ops, &cs2val, |
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"sx1.cs2", OMAP_CS2_SIZE); |
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memory_region_add_subregion(address_space, |
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OMAP_CS2_BASE, &cs[2]); |
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memory_region_init_io(&cs[3], &static_ops, &cs3val, |
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"sx1.cs3", OMAP_CS3_SIZE); |
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memory_region_add_subregion(address_space, |
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OMAP_CS2_BASE, &cs[3]); |
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fl_idx = 0; |
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#ifdef TARGET_WORDS_BIGENDIAN |
| ... | ... | |
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if ((version == 1) && |
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(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
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cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, |
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qemu_ram_alloc(NULL, "omap_sx1.flash1-0", |
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flash1_size) | IO_MEM_ROM); |
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io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, |
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DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, |
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OMAP_CS1_SIZE - flash1_size, io); |
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memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size); |
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memory_region_set_readonly(flash_1, true); |
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memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1); |
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memory_region_init_io(&cs[1], &static_ops, &cs1val, |
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"sx1.cs1", OMAP_CS1_SIZE - flash1_size); |
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memory_region_add_subregion(address_space, |
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OMAP_CS1_BASE + flash1_size, &cs[1]); |
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if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL, |
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"omap_sx1.flash1-1", flash1_size, |
| ... | ... | |
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} |
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fl_idx++; |
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} else {
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io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val, |
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DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); |
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memory_region_init_io(&cs[1], &static_ops, &cs1val, |
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"sx1.cs1", OMAP_CS1_SIZE); |
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memory_region_add_subregion(address_space, |
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OMAP_CS1_BASE, &cs[1]); |
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} |
| 201 | 192 |
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if (!kernel_filename && !fl_idx) {
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