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1 | 2c0262af | bellard | /*
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2 | 5fafdf24 | ths | * i386 execution defines
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 7d3505c5 | bellard | #include "config.h" |
21 | 2c0262af | bellard | #include "dyngen-exec.h" |
22 | 2c0262af | bellard | |
23 | 14ce26e7 | bellard | /* XXX: factorize this mess */
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24 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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25 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
26 | 14ce26e7 | bellard | #else
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27 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 32 |
28 | 14ce26e7 | bellard | #endif
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29 | 14ce26e7 | bellard | |
30 | d785e6be | bellard | #include "cpu-defs.h" |
31 | d785e6be | bellard | |
32 | 0d1a29f9 | bellard | /* at least 4 register variables are defined */
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33 | 2c0262af | bellard | register struct CPUX86State *env asm(AREG0); |
34 | 14ce26e7 | bellard | |
35 | d785e6be | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
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36 | d785e6be | bellard | |
37 | d785e6be | bellard | /* no registers can be used */
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38 | d785e6be | bellard | #define T0 (env->t0)
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39 | d785e6be | bellard | #define T1 (env->t1)
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40 | d785e6be | bellard | #define T2 (env->t2)
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41 | 14ce26e7 | bellard | |
42 | d785e6be | bellard | #else
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43 | d785e6be | bellard | |
44 | d785e6be | bellard | /* XXX: use unsigned long instead of target_ulong - better code will
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45 | d785e6be | bellard | be generated for 64 bit CPUs */
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46 | d785e6be | bellard | register target_ulong T0 asm(AREG1); |
47 | d785e6be | bellard | register target_ulong T1 asm(AREG2); |
48 | d785e6be | bellard | register target_ulong T2 asm(AREG3); |
49 | 2c0262af | bellard | |
50 | 2c0262af | bellard | /* if more registers are available, we define some registers too */
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51 | 2c0262af | bellard | #ifdef AREG4
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52 | d785e6be | bellard | register target_ulong EAX asm(AREG4); |
53 | 2c0262af | bellard | #define reg_EAX
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54 | 2c0262af | bellard | #endif
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55 | 2c0262af | bellard | |
56 | 2c0262af | bellard | #ifdef AREG5
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57 | d785e6be | bellard | register target_ulong ESP asm(AREG5); |
58 | 2c0262af | bellard | #define reg_ESP
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59 | 2c0262af | bellard | #endif
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60 | 2c0262af | bellard | |
61 | 2c0262af | bellard | #ifdef AREG6
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62 | d785e6be | bellard | register target_ulong EBP asm(AREG6); |
63 | 2c0262af | bellard | #define reg_EBP
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64 | 2c0262af | bellard | #endif
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65 | 2c0262af | bellard | |
66 | 2c0262af | bellard | #ifdef AREG7
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67 | d785e6be | bellard | register target_ulong ECX asm(AREG7); |
68 | 2c0262af | bellard | #define reg_ECX
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69 | 2c0262af | bellard | #endif
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70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | #ifdef AREG8
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72 | d785e6be | bellard | register target_ulong EDX asm(AREG8); |
73 | 2c0262af | bellard | #define reg_EDX
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74 | 2c0262af | bellard | #endif
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75 | 2c0262af | bellard | |
76 | 2c0262af | bellard | #ifdef AREG9
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77 | d785e6be | bellard | register target_ulong EBX asm(AREG9); |
78 | 2c0262af | bellard | #define reg_EBX
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79 | 2c0262af | bellard | #endif
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80 | 2c0262af | bellard | |
81 | 2c0262af | bellard | #ifdef AREG10
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82 | d785e6be | bellard | register target_ulong ESI asm(AREG10); |
83 | 2c0262af | bellard | #define reg_ESI
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84 | 2c0262af | bellard | #endif
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85 | 2c0262af | bellard | |
86 | 2c0262af | bellard | #ifdef AREG11
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87 | d785e6be | bellard | register target_ulong EDI asm(AREG11); |
88 | 2c0262af | bellard | #define reg_EDI
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89 | 2c0262af | bellard | #endif
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90 | 2c0262af | bellard | |
91 | d785e6be | bellard | #endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */ |
92 | 14ce26e7 | bellard | |
93 | 14ce26e7 | bellard | #define A0 T2
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94 | 14ce26e7 | bellard | |
95 | 2c0262af | bellard | extern FILE *logfile;
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96 | 2c0262af | bellard | extern int loglevel; |
97 | 2c0262af | bellard | |
98 | 2c0262af | bellard | #ifndef reg_EAX
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99 | 2c0262af | bellard | #define EAX (env->regs[R_EAX])
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100 | 2c0262af | bellard | #endif
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101 | 2c0262af | bellard | #ifndef reg_ECX
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102 | 2c0262af | bellard | #define ECX (env->regs[R_ECX])
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103 | 2c0262af | bellard | #endif
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104 | 2c0262af | bellard | #ifndef reg_EDX
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105 | 2c0262af | bellard | #define EDX (env->regs[R_EDX])
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106 | 2c0262af | bellard | #endif
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107 | 2c0262af | bellard | #ifndef reg_EBX
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108 | 2c0262af | bellard | #define EBX (env->regs[R_EBX])
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109 | 2c0262af | bellard | #endif
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110 | 2c0262af | bellard | #ifndef reg_ESP
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111 | 2c0262af | bellard | #define ESP (env->regs[R_ESP])
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112 | 2c0262af | bellard | #endif
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113 | 2c0262af | bellard | #ifndef reg_EBP
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114 | 2c0262af | bellard | #define EBP (env->regs[R_EBP])
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115 | 2c0262af | bellard | #endif
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116 | 2c0262af | bellard | #ifndef reg_ESI
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117 | 2c0262af | bellard | #define ESI (env->regs[R_ESI])
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118 | 2c0262af | bellard | #endif
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119 | 2c0262af | bellard | #ifndef reg_EDI
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120 | 2c0262af | bellard | #define EDI (env->regs[R_EDI])
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121 | 2c0262af | bellard | #endif
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122 | 2c0262af | bellard | #define EIP (env->eip)
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123 | 2c0262af | bellard | #define DF (env->df)
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124 | 2c0262af | bellard | |
125 | 2c0262af | bellard | #define CC_SRC (env->cc_src)
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126 | 2c0262af | bellard | #define CC_DST (env->cc_dst)
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127 | 2c0262af | bellard | #define CC_OP (env->cc_op)
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128 | 2c0262af | bellard | |
129 | 2c0262af | bellard | /* float macros */
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130 | 2c0262af | bellard | #define FT0 (env->ft0)
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131 | 664e0f19 | bellard | #define ST0 (env->fpregs[env->fpstt].d)
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132 | 664e0f19 | bellard | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
133 | 2c0262af | bellard | #define ST1 ST(1) |
134 | 2c0262af | bellard | |
135 | 2c0262af | bellard | #ifdef USE_FP_CONVERT
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136 | 2c0262af | bellard | #define FP_CONVERT (env->fp_convert)
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137 | 2c0262af | bellard | #endif
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138 | 2c0262af | bellard | |
139 | 2c0262af | bellard | #include "cpu.h" |
140 | 2c0262af | bellard | #include "exec-all.h" |
141 | 2c0262af | bellard | |
142 | 2c0262af | bellard | typedef struct CCTable { |
143 | 2c0262af | bellard | int (*compute_all)(void); /* return all the flags */ |
144 | 2c0262af | bellard | int (*compute_c)(void); /* return the C flag */ |
145 | 2c0262af | bellard | } CCTable; |
146 | 2c0262af | bellard | |
147 | 2c0262af | bellard | extern CCTable cc_table[];
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148 | 2c0262af | bellard | |
149 | 8e682019 | bellard | void load_seg(int seg_reg, int selector); |
150 | 08cea4ee | bellard | void helper_ljmp_protected_T0_T1(int next_eip); |
151 | 2c0262af | bellard | void helper_lcall_real_T0_T1(int shift, int next_eip); |
152 | 2c0262af | bellard | void helper_lcall_protected_T0_T1(int shift, int next_eip); |
153 | 2c0262af | bellard | void helper_iret_real(int shift); |
154 | 08cea4ee | bellard | void helper_iret_protected(int shift, int next_eip); |
155 | 2c0262af | bellard | void helper_lret_protected(int shift, int addend); |
156 | 2c0262af | bellard | void helper_lldt_T0(void); |
157 | 2c0262af | bellard | void helper_ltr_T0(void); |
158 | 2c0262af | bellard | void helper_movl_crN_T0(int reg); |
159 | 2c0262af | bellard | void helper_movl_drN_T0(int reg); |
160 | 8f091a59 | bellard | void helper_invlpg(target_ulong addr);
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161 | 1ac157da | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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162 | 14ce26e7 | bellard | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
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163 | 1ac157da | bellard | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
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164 | 8f091a59 | bellard | void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
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165 | 5fafdf24 | ths | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
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166 | 6ebbf390 | j_mayer | int is_write, int mmu_idx, int is_softmmu); |
167 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
168 | 61382a50 | bellard | void *retaddr);
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169 | 2c0262af | bellard | void __hidden cpu_lock(void); |
170 | 2c0262af | bellard | void __hidden cpu_unlock(void); |
171 | 5fafdf24 | ths | void do_interrupt(int intno, int is_int, int error_code, |
172 | 14ce26e7 | bellard | target_ulong next_eip, int is_hw);
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173 | 5fafdf24 | ths | void do_interrupt_user(int intno, int is_int, int error_code, |
174 | 14ce26e7 | bellard | target_ulong next_eip); |
175 | 5fafdf24 | ths | void raise_interrupt(int intno, int is_int, int error_code, |
176 | a8ede8ba | bellard | int next_eip_addend);
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177 | 2c0262af | bellard | void raise_exception_err(int exception_index, int error_code); |
178 | 2c0262af | bellard | void raise_exception(int exception_index); |
179 | 3b21e03e | bellard | void do_smm_enter(void); |
180 | 2c0262af | bellard | void __hidden cpu_loop_exit(void); |
181 | 2c0262af | bellard | |
182 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void); |
183 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void); |
184 | 57fec1fe | bellard | |
185 | 57fec1fe | bellard | #include "helper.h" |
186 | 57fec1fe | bellard | |
187 | 14ce26e7 | bellard | void helper_mulq_EAX_T0(void); |
188 | 14ce26e7 | bellard | void helper_imulq_EAX_T0(void); |
189 | 14ce26e7 | bellard | void helper_imulq_T0_T1(void); |
190 | 14ce26e7 | bellard | void helper_divq_EAX_T0(void); |
191 | 14ce26e7 | bellard | void helper_idivq_EAX_T0(void); |
192 | 68cae3d8 | bellard | void helper_bswapq_T0(void); |
193 | 2c0262af | bellard | void helper_cmpxchg8b(void); |
194 | 88fe8a41 | ths | void helper_single_step(void); |
195 | 2c0262af | bellard | void helper_cpuid(void); |
196 | 61a8c4ec | bellard | void helper_enter_level(int level, int data32); |
197 | 8f091a59 | bellard | void helper_enter64_level(int level, int data64); |
198 | 023fe10d | bellard | void helper_sysenter(void); |
199 | 023fe10d | bellard | void helper_sysexit(void); |
200 | 06c2f506 | bellard | void helper_syscall(int next_eip_addend); |
201 | 14ce26e7 | bellard | void helper_sysret(int dflag); |
202 | 2c0262af | bellard | void helper_rdtsc(void); |
203 | df01e0fc | balrog | void helper_rdpmc(void); |
204 | 2c0262af | bellard | void helper_rdmsr(void); |
205 | 2c0262af | bellard | void helper_wrmsr(void); |
206 | 2c0262af | bellard | void helper_lsl(void); |
207 | 2c0262af | bellard | void helper_lar(void); |
208 | 3ab493de | bellard | void helper_verr(void); |
209 | 3ab493de | bellard | void helper_verw(void); |
210 | 3b21e03e | bellard | void helper_rsm(void); |
211 | 2c0262af | bellard | |
212 | 3e25f951 | bellard | void check_iob_T0(void); |
213 | 3e25f951 | bellard | void check_iow_T0(void); |
214 | 3e25f951 | bellard | void check_iol_T0(void); |
215 | 3e25f951 | bellard | void check_iob_DX(void); |
216 | 3e25f951 | bellard | void check_iow_DX(void); |
217 | 3e25f951 | bellard | void check_iol_DX(void); |
218 | 3e25f951 | bellard | |
219 | 9951bf39 | bellard | #if !defined(CONFIG_USER_ONLY)
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220 | 9951bf39 | bellard | |
221 | a9049a07 | bellard | #include "softmmu_exec.h" |
222 | 9951bf39 | bellard | |
223 | 14ce26e7 | bellard | static inline double ldfq(target_ulong ptr) |
224 | 9951bf39 | bellard | { |
225 | 9951bf39 | bellard | union {
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226 | 9951bf39 | bellard | double d;
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227 | 9951bf39 | bellard | uint64_t i; |
228 | 9951bf39 | bellard | } u; |
229 | 9951bf39 | bellard | u.i = ldq(ptr); |
230 | 9951bf39 | bellard | return u.d;
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231 | 9951bf39 | bellard | } |
232 | 9951bf39 | bellard | |
233 | 14ce26e7 | bellard | static inline void stfq(target_ulong ptr, double v) |
234 | 9951bf39 | bellard | { |
235 | 9951bf39 | bellard | union {
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236 | 9951bf39 | bellard | double d;
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237 | 9951bf39 | bellard | uint64_t i; |
238 | 9951bf39 | bellard | } u; |
239 | 9951bf39 | bellard | u.d = v; |
240 | 9951bf39 | bellard | stq(ptr, u.i); |
241 | 9951bf39 | bellard | } |
242 | 9951bf39 | bellard | |
243 | 14ce26e7 | bellard | static inline float ldfl(target_ulong ptr) |
244 | 9951bf39 | bellard | { |
245 | 9951bf39 | bellard | union {
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246 | 9951bf39 | bellard | float f;
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247 | 9951bf39 | bellard | uint32_t i; |
248 | 9951bf39 | bellard | } u; |
249 | 9951bf39 | bellard | u.i = ldl(ptr); |
250 | 9951bf39 | bellard | return u.f;
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251 | 9951bf39 | bellard | } |
252 | 9951bf39 | bellard | |
253 | 14ce26e7 | bellard | static inline void stfl(target_ulong ptr, float v) |
254 | 9951bf39 | bellard | { |
255 | 9951bf39 | bellard | union {
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256 | 9951bf39 | bellard | float f;
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257 | 9951bf39 | bellard | uint32_t i; |
258 | 9951bf39 | bellard | } u; |
259 | 9951bf39 | bellard | u.f = v; |
260 | 9951bf39 | bellard | stl(ptr, u.i); |
261 | 9951bf39 | bellard | } |
262 | 9951bf39 | bellard | |
263 | 9951bf39 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
264 | 9951bf39 | bellard | |
265 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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266 | 2c0262af | bellard | /* use long double functions */
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267 | 7a0e1f41 | bellard | #define floatx_to_int32 floatx80_to_int32
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268 | 7a0e1f41 | bellard | #define floatx_to_int64 floatx80_to_int64
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269 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
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270 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
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271 | 7a0e1f41 | bellard | #define floatx_abs floatx80_abs
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272 | 7a0e1f41 | bellard | #define floatx_chs floatx80_chs
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273 | 7a0e1f41 | bellard | #define floatx_round_to_int floatx80_round_to_int
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274 | 8422b113 | bellard | #define floatx_compare floatx80_compare
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275 | 8422b113 | bellard | #define floatx_compare_quiet floatx80_compare_quiet
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276 | 2c0262af | bellard | #define sin sinl
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277 | 2c0262af | bellard | #define cos cosl
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278 | 2c0262af | bellard | #define sqrt sqrtl
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279 | 2c0262af | bellard | #define pow powl
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280 | 2c0262af | bellard | #define log logl
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281 | 2c0262af | bellard | #define tan tanl
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282 | 2c0262af | bellard | #define atan2 atan2l
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283 | 2c0262af | bellard | #define floor floorl
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284 | 2c0262af | bellard | #define ceil ceill
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285 | 57e4c06e | bellard | #define ldexp ldexpl
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286 | 7d3505c5 | bellard | #else
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287 | 7a0e1f41 | bellard | #define floatx_to_int32 float64_to_int32
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288 | 7a0e1f41 | bellard | #define floatx_to_int64 float64_to_int64
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289 | 465e9838 | bellard | #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
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290 | 465e9838 | bellard | #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
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291 | 7a0e1f41 | bellard | #define floatx_abs float64_abs
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292 | 7a0e1f41 | bellard | #define floatx_chs float64_chs
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293 | 7a0e1f41 | bellard | #define floatx_round_to_int float64_round_to_int
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294 | 8422b113 | bellard | #define floatx_compare float64_compare
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295 | 8422b113 | bellard | #define floatx_compare_quiet float64_compare_quiet
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296 | 7d3505c5 | bellard | #endif
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297 | 7a0e1f41 | bellard | |
298 | 2c0262af | bellard | extern CPU86_LDouble sin(CPU86_LDouble x);
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299 | 2c0262af | bellard | extern CPU86_LDouble cos(CPU86_LDouble x);
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300 | 2c0262af | bellard | extern CPU86_LDouble sqrt(CPU86_LDouble x);
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301 | 2c0262af | bellard | extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
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302 | 2c0262af | bellard | extern CPU86_LDouble log(CPU86_LDouble x);
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303 | 2c0262af | bellard | extern CPU86_LDouble tan(CPU86_LDouble x);
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304 | 2c0262af | bellard | extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
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305 | 2c0262af | bellard | extern CPU86_LDouble floor(CPU86_LDouble x);
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306 | 2c0262af | bellard | extern CPU86_LDouble ceil(CPU86_LDouble x);
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307 | 2c0262af | bellard | |
308 | 2c0262af | bellard | #define RC_MASK 0xc00 |
309 | 2c0262af | bellard | #define RC_NEAR 0x000 |
310 | 2c0262af | bellard | #define RC_DOWN 0x400 |
311 | 2c0262af | bellard | #define RC_UP 0x800 |
312 | 2c0262af | bellard | #define RC_CHOP 0xc00 |
313 | 2c0262af | bellard | |
314 | 2c0262af | bellard | #define MAXTAN 9223372036854775808.0 |
315 | 2c0262af | bellard | |
316 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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317 | 2c0262af | bellard | |
318 | 2c0262af | bellard | /* only for x86 */
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319 | 2c0262af | bellard | typedef union { |
320 | 2c0262af | bellard | long double d; |
321 | 2c0262af | bellard | struct {
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322 | 2c0262af | bellard | unsigned long long lower; |
323 | 2c0262af | bellard | unsigned short upper; |
324 | 2c0262af | bellard | } l; |
325 | 2c0262af | bellard | } CPU86_LDoubleU; |
326 | 2c0262af | bellard | |
327 | 2c0262af | bellard | /* the following deal with x86 long double-precision numbers */
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328 | 2c0262af | bellard | #define MAXEXPD 0x7fff |
329 | 2c0262af | bellard | #define EXPBIAS 16383 |
330 | 2c0262af | bellard | #define EXPD(fp) (fp.l.upper & 0x7fff) |
331 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
332 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower)
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333 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
334 | 2c0262af | bellard | |
335 | 2c0262af | bellard | #else
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336 | 2c0262af | bellard | |
337 | 2c0262af | bellard | /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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338 | 2c0262af | bellard | typedef union { |
339 | 2c0262af | bellard | double d;
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340 | 2c0262af | bellard | #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
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341 | 2c0262af | bellard | struct {
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342 | 2c0262af | bellard | uint32_t lower; |
343 | 2c0262af | bellard | int32_t upper; |
344 | 2c0262af | bellard | } l; |
345 | 2c0262af | bellard | #else
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346 | 2c0262af | bellard | struct {
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347 | 2c0262af | bellard | int32_t upper; |
348 | 2c0262af | bellard | uint32_t lower; |
349 | 2c0262af | bellard | } l; |
350 | 2c0262af | bellard | #endif
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351 | 2c0262af | bellard | #ifndef __arm__
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352 | 2c0262af | bellard | int64_t ll; |
353 | 2c0262af | bellard | #endif
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354 | 2c0262af | bellard | } CPU86_LDoubleU; |
355 | 2c0262af | bellard | |
356 | 2c0262af | bellard | /* the following deal with IEEE double-precision numbers */
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357 | 2c0262af | bellard | #define MAXEXPD 0x7ff |
358 | 2c0262af | bellard | #define EXPBIAS 1023 |
359 | 2c0262af | bellard | #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF) |
360 | 2c0262af | bellard | #define SIGND(fp) ((fp.l.upper) & 0x80000000) |
361 | 2c0262af | bellard | #ifdef __arm__
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362 | 2c0262af | bellard | #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32)) |
363 | 2c0262af | bellard | #else
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364 | 2c0262af | bellard | #define MANTD(fp) (fp.ll & ((1LL << 52) - 1)) |
365 | 2c0262af | bellard | #endif
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366 | 2c0262af | bellard | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20) |
367 | 2c0262af | bellard | #endif
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368 | 2c0262af | bellard | |
369 | 2c0262af | bellard | static inline void fpush(void) |
370 | 2c0262af | bellard | { |
371 | 2c0262af | bellard | env->fpstt = (env->fpstt - 1) & 7; |
372 | 2c0262af | bellard | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
373 | 2c0262af | bellard | } |
374 | 2c0262af | bellard | |
375 | 2c0262af | bellard | static inline void fpop(void) |
376 | 2c0262af | bellard | { |
377 | 2c0262af | bellard | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
378 | 2c0262af | bellard | env->fpstt = (env->fpstt + 1) & 7; |
379 | 2c0262af | bellard | } |
380 | 2c0262af | bellard | |
381 | 2c0262af | bellard | #ifndef USE_X86LDOUBLE
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382 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
383 | 2c0262af | bellard | { |
384 | 2c0262af | bellard | CPU86_LDoubleU temp; |
385 | 2c0262af | bellard | int upper, e;
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386 | 2c0262af | bellard | uint64_t ll; |
387 | 2c0262af | bellard | |
388 | 2c0262af | bellard | /* mantissa */
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389 | 2c0262af | bellard | upper = lduw(ptr + 8);
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390 | 2c0262af | bellard | /* XXX: handle overflow ? */
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391 | 2c0262af | bellard | e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */ |
392 | 2c0262af | bellard | e |= (upper >> 4) & 0x800; /* sign */ |
393 | 2c0262af | bellard | ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1); |
394 | 2c0262af | bellard | #ifdef __arm__
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395 | 2c0262af | bellard | temp.l.upper = (e << 20) | (ll >> 32); |
396 | 2c0262af | bellard | temp.l.lower = ll; |
397 | 2c0262af | bellard | #else
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398 | 2c0262af | bellard | temp.ll = ll | ((uint64_t)e << 52);
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399 | 2c0262af | bellard | #endif
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400 | 2c0262af | bellard | return temp.d;
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401 | 2c0262af | bellard | } |
402 | 2c0262af | bellard | |
403 | 664e0f19 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
404 | 2c0262af | bellard | { |
405 | 2c0262af | bellard | CPU86_LDoubleU temp; |
406 | 2c0262af | bellard | int e;
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407 | 2c0262af | bellard | |
408 | 2c0262af | bellard | temp.d = f; |
409 | 2c0262af | bellard | /* mantissa */
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410 | 2c0262af | bellard | stq(ptr, (MANTD(temp) << 11) | (1LL << 63)); |
411 | 2c0262af | bellard | /* exponent + sign */
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412 | 2c0262af | bellard | e = EXPD(temp) - EXPBIAS + 16383;
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413 | 2c0262af | bellard | e |= SIGND(temp) >> 16;
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414 | 2c0262af | bellard | stw(ptr + 8, e);
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415 | 2c0262af | bellard | } |
416 | 9951bf39 | bellard | #else
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417 | 9951bf39 | bellard | |
418 | 9951bf39 | bellard | /* XXX: same endianness assumed */
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419 | 9951bf39 | bellard | |
420 | 9951bf39 | bellard | #ifdef CONFIG_USER_ONLY
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421 | 9951bf39 | bellard | |
422 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
423 | 9951bf39 | bellard | { |
424 | bd37ec21 | bellard | return *(CPU86_LDouble *)(unsigned long)ptr; |
425 | 9951bf39 | bellard | } |
426 | 9951bf39 | bellard | |
427 | 14ce26e7 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
428 | 9951bf39 | bellard | { |
429 | bd37ec21 | bellard | *(CPU86_LDouble *)(unsigned long)ptr = f; |
430 | 9951bf39 | bellard | } |
431 | 9951bf39 | bellard | |
432 | 9951bf39 | bellard | #else
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433 | 9951bf39 | bellard | |
434 | 9951bf39 | bellard | /* we use memory access macros */
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435 | 9951bf39 | bellard | |
436 | 14ce26e7 | bellard | static inline CPU86_LDouble helper_fldt(target_ulong ptr) |
437 | 9951bf39 | bellard | { |
438 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
439 | 9951bf39 | bellard | |
440 | 9951bf39 | bellard | temp.l.lower = ldq(ptr); |
441 | 9951bf39 | bellard | temp.l.upper = lduw(ptr + 8);
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442 | 9951bf39 | bellard | return temp.d;
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443 | 9951bf39 | bellard | } |
444 | 9951bf39 | bellard | |
445 | 14ce26e7 | bellard | static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr) |
446 | 9951bf39 | bellard | { |
447 | 9951bf39 | bellard | CPU86_LDoubleU temp; |
448 | 3b46e624 | ths | |
449 | 9951bf39 | bellard | temp.d = f; |
450 | 9951bf39 | bellard | stq(ptr, temp.l.lower); |
451 | 9951bf39 | bellard | stw(ptr + 8, temp.l.upper);
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452 | 9951bf39 | bellard | } |
453 | 9951bf39 | bellard | |
454 | 9951bf39 | bellard | #endif /* !CONFIG_USER_ONLY */ |
455 | 9951bf39 | bellard | |
456 | 9951bf39 | bellard | #endif /* USE_X86LDOUBLE */ |
457 | 2c0262af | bellard | |
458 | 2ee73ac3 | bellard | #define FPUS_IE (1 << 0) |
459 | 2ee73ac3 | bellard | #define FPUS_DE (1 << 1) |
460 | 2ee73ac3 | bellard | #define FPUS_ZE (1 << 2) |
461 | 2ee73ac3 | bellard | #define FPUS_OE (1 << 3) |
462 | 2ee73ac3 | bellard | #define FPUS_UE (1 << 4) |
463 | 2ee73ac3 | bellard | #define FPUS_PE (1 << 5) |
464 | 2ee73ac3 | bellard | #define FPUS_SF (1 << 6) |
465 | 2ee73ac3 | bellard | #define FPUS_SE (1 << 7) |
466 | 2ee73ac3 | bellard | #define FPUS_B (1 << 15) |
467 | 2ee73ac3 | bellard | |
468 | 2ee73ac3 | bellard | #define FPUC_EM 0x3f |
469 | 2ee73ac3 | bellard | |
470 | 83fb7adf | bellard | extern const CPU86_LDouble f15rk[7]; |
471 | 2c0262af | bellard | |
472 | 2c0262af | bellard | void helper_fldt_ST0_A0(void); |
473 | 2c0262af | bellard | void helper_fstt_ST0_A0(void); |
474 | 2ee73ac3 | bellard | void fpu_raise_exception(void); |
475 | 2ee73ac3 | bellard | CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b); |
476 | 2c0262af | bellard | void helper_fbld_ST0_A0(void); |
477 | 2c0262af | bellard | void helper_fbst_ST0_A0(void); |
478 | 2c0262af | bellard | void helper_f2xm1(void); |
479 | 2c0262af | bellard | void helper_fyl2x(void); |
480 | 2c0262af | bellard | void helper_fptan(void); |
481 | 2c0262af | bellard | void helper_fpatan(void); |
482 | 2c0262af | bellard | void helper_fxtract(void); |
483 | 2c0262af | bellard | void helper_fprem1(void); |
484 | 2c0262af | bellard | void helper_fprem(void); |
485 | 2c0262af | bellard | void helper_fyl2xp1(void); |
486 | 2c0262af | bellard | void helper_fsqrt(void); |
487 | 2c0262af | bellard | void helper_fsincos(void); |
488 | 2c0262af | bellard | void helper_frndint(void); |
489 | 2c0262af | bellard | void helper_fscale(void); |
490 | 2c0262af | bellard | void helper_fsin(void); |
491 | 2c0262af | bellard | void helper_fcos(void); |
492 | 2c0262af | bellard | void helper_fxam_ST0(void); |
493 | 14ce26e7 | bellard | void helper_fstenv(target_ulong ptr, int data32); |
494 | 14ce26e7 | bellard | void helper_fldenv(target_ulong ptr, int data32); |
495 | 14ce26e7 | bellard | void helper_fsave(target_ulong ptr, int data32); |
496 | 14ce26e7 | bellard | void helper_frstor(target_ulong ptr, int data32); |
497 | 14ce26e7 | bellard | void helper_fxsave(target_ulong ptr, int data64); |
498 | 14ce26e7 | bellard | void helper_fxrstor(target_ulong ptr, int data64); |
499 | 03857e31 | bellard | void restore_native_fp_state(CPUState *env);
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500 | 03857e31 | bellard | void save_native_fp_state(CPUState *env);
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501 | 664e0f19 | bellard | float approx_rsqrt(float a); |
502 | 664e0f19 | bellard | float approx_rcp(float a); |
503 | 7a0e1f41 | bellard | void update_fp_status(void); |
504 | 3d7374c5 | bellard | void helper_hlt(void); |
505 | 3d7374c5 | bellard | void helper_monitor(void); |
506 | 3d7374c5 | bellard | void helper_mwait(void); |
507 | 0573fbfc | ths | void helper_vmrun(target_ulong addr);
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508 | 0573fbfc | ths | void helper_vmmcall(void); |
509 | 0573fbfc | ths | void helper_vmload(target_ulong addr);
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510 | 0573fbfc | ths | void helper_vmsave(target_ulong addr);
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511 | 0573fbfc | ths | void helper_stgi(void); |
512 | 0573fbfc | ths | void helper_clgi(void); |
513 | 0573fbfc | ths | void helper_skinit(void); |
514 | 0573fbfc | ths | void helper_invlpga(void); |
515 | 0573fbfc | ths | void vmexit(uint64_t exit_code, uint64_t exit_info_1);
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516 | 2c0262af | bellard | |
517 | 83fb7adf | bellard | extern const uint8_t parity_table[256]; |
518 | 83fb7adf | bellard | extern const uint8_t rclw_table[32]; |
519 | 83fb7adf | bellard | extern const uint8_t rclb_table[32]; |
520 | 2c0262af | bellard | |
521 | 2c0262af | bellard | static inline uint32_t compute_eflags(void) |
522 | 2c0262af | bellard | { |
523 | 2c0262af | bellard | return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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524 | 2c0262af | bellard | } |
525 | 2c0262af | bellard | |
526 | 2c0262af | bellard | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
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527 | 2c0262af | bellard | static inline void load_eflags(int eflags, int update_mask) |
528 | 2c0262af | bellard | { |
529 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
530 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1)); |
531 | 5fafdf24 | ths | env->eflags = (env->eflags & ~update_mask) | |
532 | 2c0262af | bellard | (eflags & update_mask); |
533 | 2c0262af | bellard | } |
534 | 2c0262af | bellard | |
535 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
536 | 0d1a29f9 | bellard | { |
537 | 0d1a29f9 | bellard | #ifdef reg_EAX
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538 | 0d1a29f9 | bellard | EAX = env->regs[R_EAX]; |
539 | 0d1a29f9 | bellard | #endif
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540 | 0d1a29f9 | bellard | #ifdef reg_ECX
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541 | 0d1a29f9 | bellard | ECX = env->regs[R_ECX]; |
542 | 0d1a29f9 | bellard | #endif
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543 | 0d1a29f9 | bellard | #ifdef reg_EDX
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544 | 0d1a29f9 | bellard | EDX = env->regs[R_EDX]; |
545 | 0d1a29f9 | bellard | #endif
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546 | 0d1a29f9 | bellard | #ifdef reg_EBX
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547 | 0d1a29f9 | bellard | EBX = env->regs[R_EBX]; |
548 | 0d1a29f9 | bellard | #endif
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549 | 0d1a29f9 | bellard | #ifdef reg_ESP
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550 | 0d1a29f9 | bellard | ESP = env->regs[R_ESP]; |
551 | 0d1a29f9 | bellard | #endif
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552 | 0d1a29f9 | bellard | #ifdef reg_EBP
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553 | 0d1a29f9 | bellard | EBP = env->regs[R_EBP]; |
554 | 0d1a29f9 | bellard | #endif
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555 | 0d1a29f9 | bellard | #ifdef reg_ESI
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556 | 0d1a29f9 | bellard | ESI = env->regs[R_ESI]; |
557 | 0d1a29f9 | bellard | #endif
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558 | 0d1a29f9 | bellard | #ifdef reg_EDI
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559 | 0d1a29f9 | bellard | EDI = env->regs[R_EDI]; |
560 | 0d1a29f9 | bellard | #endif
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561 | 0d1a29f9 | bellard | } |
562 | 0d1a29f9 | bellard | |
563 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
564 | 0d1a29f9 | bellard | { |
565 | 0d1a29f9 | bellard | #ifdef reg_EAX
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566 | 0d1a29f9 | bellard | env->regs[R_EAX] = EAX; |
567 | 0d1a29f9 | bellard | #endif
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568 | 0d1a29f9 | bellard | #ifdef reg_ECX
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569 | 0d1a29f9 | bellard | env->regs[R_ECX] = ECX; |
570 | 0d1a29f9 | bellard | #endif
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571 | 0d1a29f9 | bellard | #ifdef reg_EDX
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572 | 0d1a29f9 | bellard | env->regs[R_EDX] = EDX; |
573 | 0d1a29f9 | bellard | #endif
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574 | 0d1a29f9 | bellard | #ifdef reg_EBX
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575 | 0d1a29f9 | bellard | env->regs[R_EBX] = EBX; |
576 | 0d1a29f9 | bellard | #endif
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577 | 0d1a29f9 | bellard | #ifdef reg_ESP
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578 | 0d1a29f9 | bellard | env->regs[R_ESP] = ESP; |
579 | 0d1a29f9 | bellard | #endif
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580 | 0d1a29f9 | bellard | #ifdef reg_EBP
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581 | 0d1a29f9 | bellard | env->regs[R_EBP] = EBP; |
582 | 0d1a29f9 | bellard | #endif
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583 | 0d1a29f9 | bellard | #ifdef reg_ESI
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584 | 0d1a29f9 | bellard | env->regs[R_ESI] = ESI; |
585 | 0d1a29f9 | bellard | #endif
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586 | 0d1a29f9 | bellard | #ifdef reg_EDI
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587 | 0d1a29f9 | bellard | env->regs[R_EDI] = EDI; |
588 | 0d1a29f9 | bellard | #endif
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589 | 0d1a29f9 | bellard | } |
590 | bfed01fc | ths | |
591 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
592 | bfed01fc | ths | /* handle exit of HALTED state */
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593 | d0bdf2a2 | ths | if (!(env->hflags & HF_HALTED_MASK))
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594 | bfed01fc | ths | return 0; |
595 | bfed01fc | ths | /* disable halt condition */
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596 | 474ea849 | aurel32 | if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
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597 | 474ea849 | aurel32 | (env->eflags & IF_MASK)) || |
598 | 474ea849 | aurel32 | (env->interrupt_request & CPU_INTERRUPT_NMI)) { |
599 | bfed01fc | ths | env->hflags &= ~HF_HALTED_MASK; |
600 | bfed01fc | ths | return 0; |
601 | bfed01fc | ths | } |
602 | bfed01fc | ths | return EXCP_HALTED;
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603 | bfed01fc | ths | } |