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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * OneNAND flash memories emulation.
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3 | 7e7c5e4c | balrog | *
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4 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 7e7c5e4c | balrog | *
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7 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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8 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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9 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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11 | 7e7c5e4c | balrog | *
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12 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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13 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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16 | 7e7c5e4c | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 7e7c5e4c | balrog | */
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20 | 7e7c5e4c | balrog | |
21 | 7e7c5e4c | balrog | #include "qemu-common.h" |
22 | 7e7c5e4c | balrog | #include "flash.h" |
23 | 7e7c5e4c | balrog | #include "irq.h" |
24 | 7e7c5e4c | balrog | #include "sysemu.h" |
25 | 7e7c5e4c | balrog | #include "block.h" |
26 | 7e7c5e4c | balrog | |
27 | 7e7c5e4c | balrog | /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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28 | 7e7c5e4c | balrog | #define PAGE_SHIFT 11 |
29 | 7e7c5e4c | balrog | |
30 | 7e7c5e4c | balrog | /* Fixed */
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31 | 7e7c5e4c | balrog | #define BLOCK_SHIFT (PAGE_SHIFT + 6) |
32 | 7e7c5e4c | balrog | |
33 | bc24a225 | Paul Brook | typedef struct { |
34 | 7e7c5e4c | balrog | uint32_t id; |
35 | 7e7c5e4c | balrog | int shift;
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36 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
37 | 7e7c5e4c | balrog | qemu_irq intr; |
38 | 7e7c5e4c | balrog | qemu_irq rdy; |
39 | 7e7c5e4c | balrog | BlockDriverState *bdrv; |
40 | 7e7c5e4c | balrog | BlockDriverState *bdrv_cur; |
41 | 7e7c5e4c | balrog | uint8_t *image; |
42 | 7e7c5e4c | balrog | uint8_t *otp; |
43 | 7e7c5e4c | balrog | uint8_t *current; |
44 | c227f099 | Anthony Liguori | ram_addr_t ram; |
45 | 7e7c5e4c | balrog | uint8_t *boot[2];
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46 | 7e7c5e4c | balrog | uint8_t *data[2][2]; |
47 | 7e7c5e4c | balrog | int iomemtype;
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48 | 7e7c5e4c | balrog | int cycle;
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49 | 7e7c5e4c | balrog | int otpmode;
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50 | 7e7c5e4c | balrog | |
51 | 7e7c5e4c | balrog | uint16_t addr[8];
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52 | 7e7c5e4c | balrog | uint16_t unladdr[8];
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53 | 7e7c5e4c | balrog | int bufaddr;
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54 | 7e7c5e4c | balrog | int count;
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55 | 7e7c5e4c | balrog | uint16_t command; |
56 | 7e7c5e4c | balrog | uint16_t config[2];
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57 | 7e7c5e4c | balrog | uint16_t status; |
58 | 7e7c5e4c | balrog | uint16_t intstatus; |
59 | 7e7c5e4c | balrog | uint16_t wpstatus; |
60 | 7e7c5e4c | balrog | |
61 | bc24a225 | Paul Brook | ECCState ecc; |
62 | 7e7c5e4c | balrog | |
63 | 7e7c5e4c | balrog | int density_mask;
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64 | 7e7c5e4c | balrog | int secs;
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65 | 7e7c5e4c | balrog | int secs_cur;
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66 | 7e7c5e4c | balrog | int blocks;
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67 | 7e7c5e4c | balrog | uint8_t *blockwp; |
68 | bc24a225 | Paul Brook | } OneNANDState; |
69 | 7e7c5e4c | balrog | |
70 | 7e7c5e4c | balrog | enum {
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71 | 7e7c5e4c | balrog | ONEN_BUF_BLOCK = 0,
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72 | 7e7c5e4c | balrog | ONEN_BUF_BLOCK2 = 1,
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73 | 7e7c5e4c | balrog | ONEN_BUF_DEST_BLOCK = 2,
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74 | 7e7c5e4c | balrog | ONEN_BUF_DEST_PAGE = 3,
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75 | 7e7c5e4c | balrog | ONEN_BUF_PAGE = 7,
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76 | 7e7c5e4c | balrog | }; |
77 | 7e7c5e4c | balrog | |
78 | 7e7c5e4c | balrog | enum {
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79 | 7e7c5e4c | balrog | ONEN_ERR_CMD = 1 << 10, |
80 | 7e7c5e4c | balrog | ONEN_ERR_ERASE = 1 << 11, |
81 | 7e7c5e4c | balrog | ONEN_ERR_PROG = 1 << 12, |
82 | 7e7c5e4c | balrog | ONEN_ERR_LOAD = 1 << 13, |
83 | 7e7c5e4c | balrog | }; |
84 | 7e7c5e4c | balrog | |
85 | 7e7c5e4c | balrog | enum {
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86 | 7e7c5e4c | balrog | ONEN_INT_RESET = 1 << 4, |
87 | 7e7c5e4c | balrog | ONEN_INT_ERASE = 1 << 5, |
88 | 7e7c5e4c | balrog | ONEN_INT_PROG = 1 << 6, |
89 | 7e7c5e4c | balrog | ONEN_INT_LOAD = 1 << 7, |
90 | 7e7c5e4c | balrog | ONEN_INT = 1 << 15, |
91 | 7e7c5e4c | balrog | }; |
92 | 7e7c5e4c | balrog | |
93 | 7e7c5e4c | balrog | enum {
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94 | 7e7c5e4c | balrog | ONEN_LOCK_LOCKTIGHTEN = 1 << 0, |
95 | 7e7c5e4c | balrog | ONEN_LOCK_LOCKED = 1 << 1, |
96 | 7e7c5e4c | balrog | ONEN_LOCK_UNLOCKED = 1 << 2, |
97 | 7e7c5e4c | balrog | }; |
98 | 7e7c5e4c | balrog | |
99 | c227f099 | Anthony Liguori | void onenand_base_update(void *opaque, target_phys_addr_t new) |
100 | 7e7c5e4c | balrog | { |
101 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) opaque; |
102 | 7e7c5e4c | balrog | |
103 | 7e7c5e4c | balrog | s->base = new; |
104 | 7e7c5e4c | balrog | |
105 | 7e7c5e4c | balrog | /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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106 | 7e7c5e4c | balrog | * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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107 | 7e7c5e4c | balrog | * write boot commands. Also take note of the BWPS bit. */
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108 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base + (0x0000 << s->shift),
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109 | 7e7c5e4c | balrog | 0x0200 << s->shift, s->iomemtype);
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110 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base + (0x0200 << s->shift),
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111 | 7e7c5e4c | balrog | 0xbe00 << s->shift,
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112 | 7e7c5e4c | balrog | (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
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113 | 7e7c5e4c | balrog | if (s->iomemtype)
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114 | 8da3ff18 | pbrook | cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
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115 | 8da3ff18 | pbrook | 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift)); |
116 | 7e7c5e4c | balrog | } |
117 | 7e7c5e4c | balrog | |
118 | 7e7c5e4c | balrog | void onenand_base_unmap(void *opaque) |
119 | 7e7c5e4c | balrog | { |
120 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) opaque; |
121 | 7e7c5e4c | balrog | |
122 | 7e7c5e4c | balrog | cpu_register_physical_memory(s->base, |
123 | 7e7c5e4c | balrog | 0x10000 << s->shift, IO_MEM_UNASSIGNED);
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124 | 7e7c5e4c | balrog | } |
125 | 7e7c5e4c | balrog | |
126 | bc24a225 | Paul Brook | static void onenand_intr_update(OneNANDState *s) |
127 | 7e7c5e4c | balrog | { |
128 | 7e7c5e4c | balrog | qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
129 | 7e7c5e4c | balrog | } |
130 | 7e7c5e4c | balrog | |
131 | 7e7c5e4c | balrog | /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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132 | bc24a225 | Paul Brook | static void onenand_reset(OneNANDState *s, int cold) |
133 | 7e7c5e4c | balrog | { |
134 | 7e7c5e4c | balrog | memset(&s->addr, 0, sizeof(s->addr)); |
135 | 7e7c5e4c | balrog | s->command = 0;
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136 | 7e7c5e4c | balrog | s->count = 1;
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137 | 7e7c5e4c | balrog | s->bufaddr = 0;
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138 | 7e7c5e4c | balrog | s->config[0] = 0x40c0; |
139 | 7e7c5e4c | balrog | s->config[1] = 0x0000; |
140 | 7e7c5e4c | balrog | onenand_intr_update(s); |
141 | 7e7c5e4c | balrog | qemu_irq_raise(s->rdy); |
142 | 7e7c5e4c | balrog | s->status = 0x0000;
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143 | 7e7c5e4c | balrog | s->intstatus = cold ? 0x8080 : 0x8010; |
144 | 7e7c5e4c | balrog | s->unladdr[0] = 0; |
145 | 7e7c5e4c | balrog | s->unladdr[1] = 0; |
146 | 7e7c5e4c | balrog | s->wpstatus = 0x0002;
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147 | 7e7c5e4c | balrog | s->cycle = 0;
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148 | 7e7c5e4c | balrog | s->otpmode = 0;
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149 | 7e7c5e4c | balrog | s->bdrv_cur = s->bdrv; |
150 | 7e7c5e4c | balrog | s->current = s->image; |
151 | 7e7c5e4c | balrog | s->secs_cur = s->secs; |
152 | 7e7c5e4c | balrog | |
153 | 7e7c5e4c | balrog | if (cold) {
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154 | 7e7c5e4c | balrog | /* Lock the whole flash */
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155 | 7e7c5e4c | balrog | memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); |
156 | 7e7c5e4c | balrog | |
157 | 7e7c5e4c | balrog | if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0) |
158 | 2ac71179 | Paul Brook | hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
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159 | 7e7c5e4c | balrog | } |
160 | 7e7c5e4c | balrog | } |
161 | 7e7c5e4c | balrog | |
162 | bc24a225 | Paul Brook | static inline int onenand_load_main(OneNANDState *s, int sec, int secn, |
163 | 7e7c5e4c | balrog | void *dest)
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164 | 7e7c5e4c | balrog | { |
165 | 7e7c5e4c | balrog | if (s->bdrv_cur)
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166 | 7e7c5e4c | balrog | return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0; |
167 | 7e7c5e4c | balrog | else if (sec + secn > s->secs_cur) |
168 | 7e7c5e4c | balrog | return 1; |
169 | 7e7c5e4c | balrog | |
170 | 7e7c5e4c | balrog | memcpy(dest, s->current + (sec << 9), secn << 9); |
171 | 7e7c5e4c | balrog | |
172 | 7e7c5e4c | balrog | return 0; |
173 | 7e7c5e4c | balrog | } |
174 | 7e7c5e4c | balrog | |
175 | bc24a225 | Paul Brook | static inline int onenand_prog_main(OneNANDState *s, int sec, int secn, |
176 | 7e7c5e4c | balrog | void *src)
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177 | 7e7c5e4c | balrog | { |
178 | 7e7c5e4c | balrog | if (s->bdrv_cur)
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179 | 7e7c5e4c | balrog | return bdrv_write(s->bdrv_cur, sec, src, secn) < 0; |
180 | 7e7c5e4c | balrog | else if (sec + secn > s->secs_cur) |
181 | 7e7c5e4c | balrog | return 1; |
182 | 7e7c5e4c | balrog | |
183 | 7e7c5e4c | balrog | memcpy(s->current + (sec << 9), src, secn << 9); |
184 | 7e7c5e4c | balrog | |
185 | 7e7c5e4c | balrog | return 0; |
186 | 7e7c5e4c | balrog | } |
187 | 7e7c5e4c | balrog | |
188 | bc24a225 | Paul Brook | static inline int onenand_load_spare(OneNANDState *s, int sec, int secn, |
189 | 7e7c5e4c | balrog | void *dest)
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190 | 7e7c5e4c | balrog | { |
191 | 7e7c5e4c | balrog | uint8_t buf[512];
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192 | 7e7c5e4c | balrog | |
193 | 7e7c5e4c | balrog | if (s->bdrv_cur) {
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194 | 7e7c5e4c | balrog | if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
195 | 7e7c5e4c | balrog | return 1; |
196 | 7e7c5e4c | balrog | memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
197 | 7e7c5e4c | balrog | } else if (sec + secn > s->secs_cur) |
198 | 7e7c5e4c | balrog | return 1; |
199 | 7e7c5e4c | balrog | else
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200 | 7e7c5e4c | balrog | memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
201 | 7e7c5e4c | balrog | |
202 | 7e7c5e4c | balrog | return 0; |
203 | 7e7c5e4c | balrog | } |
204 | 7e7c5e4c | balrog | |
205 | bc24a225 | Paul Brook | static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn, |
206 | 7e7c5e4c | balrog | void *src)
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207 | 7e7c5e4c | balrog | { |
208 | 7e7c5e4c | balrog | uint8_t buf[512];
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209 | 7e7c5e4c | balrog | |
210 | 7e7c5e4c | balrog | if (s->bdrv_cur) {
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211 | 7e7c5e4c | balrog | if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0) |
212 | 7e7c5e4c | balrog | return 1; |
213 | 7e7c5e4c | balrog | memcpy(buf + ((sec & 31) << 4), src, secn << 4); |
214 | 7e7c5e4c | balrog | return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0; |
215 | 7e7c5e4c | balrog | } else if (sec + secn > s->secs_cur) |
216 | 7e7c5e4c | balrog | return 1; |
217 | 7e7c5e4c | balrog | |
218 | 7e7c5e4c | balrog | memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4); |
219 | 7e7c5e4c | balrog | |
220 | 7e7c5e4c | balrog | return 0; |
221 | 7e7c5e4c | balrog | } |
222 | 7e7c5e4c | balrog | |
223 | bc24a225 | Paul Brook | static inline int onenand_erase(OneNANDState *s, int sec, int num) |
224 | 7e7c5e4c | balrog | { |
225 | 7e7c5e4c | balrog | /* TODO: optimise */
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226 | 7e7c5e4c | balrog | uint8_t buf[512];
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227 | 7e7c5e4c | balrog | |
228 | 7e7c5e4c | balrog | memset(buf, 0xff, sizeof(buf)); |
229 | 7e7c5e4c | balrog | for (; num > 0; num --, sec ++) { |
230 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, 1, buf)) |
231 | 7e7c5e4c | balrog | return 1; |
232 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, 1, buf)) |
233 | 7e7c5e4c | balrog | return 1; |
234 | 7e7c5e4c | balrog | } |
235 | 7e7c5e4c | balrog | |
236 | 7e7c5e4c | balrog | return 0; |
237 | 7e7c5e4c | balrog | } |
238 | 7e7c5e4c | balrog | |
239 | bc24a225 | Paul Brook | static void onenand_command(OneNANDState *s, int cmd) |
240 | 7e7c5e4c | balrog | { |
241 | 7e7c5e4c | balrog | int b;
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242 | 7e7c5e4c | balrog | int sec;
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243 | 7e7c5e4c | balrog | void *buf;
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244 | 7e7c5e4c | balrog | #define SETADDR(block, page) \
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245 | 7e7c5e4c | balrog | sec = (s->addr[page] & 3) + \
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246 | 7e7c5e4c | balrog | ((((s->addr[page] >> 2) & 0x3f) + \ |
247 | 7e7c5e4c | balrog | (((s->addr[block] & 0xfff) | \
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248 | 7e7c5e4c | balrog | (s->addr[block] >> 15 ? \
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249 | 7e7c5e4c | balrog | s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9)); |
250 | 7e7c5e4c | balrog | #define SETBUF_M() \
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251 | 7e7c5e4c | balrog | buf = (s->bufaddr & 8) ? \
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252 | 7e7c5e4c | balrog | s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ |
253 | 7e7c5e4c | balrog | buf += (s->bufaddr & 3) << 9; |
254 | 7e7c5e4c | balrog | #define SETBUF_S() \
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255 | 7e7c5e4c | balrog | buf = (s->bufaddr & 8) ? \
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256 | 7e7c5e4c | balrog | s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ |
257 | 7e7c5e4c | balrog | buf += (s->bufaddr & 3) << 4; |
258 | 7e7c5e4c | balrog | |
259 | 7e7c5e4c | balrog | switch (cmd) {
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260 | 7e7c5e4c | balrog | case 0x00: /* Load single/multiple sector data unit into buffer */ |
261 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
262 | 7e7c5e4c | balrog | |
263 | 7e7c5e4c | balrog | SETBUF_M() |
264 | 7e7c5e4c | balrog | if (onenand_load_main(s, sec, s->count, buf))
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265 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
266 | 7e7c5e4c | balrog | |
267 | 7e7c5e4c | balrog | #if 0
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268 | 7e7c5e4c | balrog | SETBUF_S()
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269 | 7e7c5e4c | balrog | if (onenand_load_spare(s, sec, s->count, buf))
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270 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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271 | 7e7c5e4c | balrog | #endif
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272 | 7e7c5e4c | balrog | |
273 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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274 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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275 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
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276 | 7e7c5e4c | balrog | */
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277 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
278 | 7e7c5e4c | balrog | break;
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279 | 7e7c5e4c | balrog | case 0x13: /* Load single/multiple spare sector into buffer */ |
280 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
281 | 7e7c5e4c | balrog | |
282 | 7e7c5e4c | balrog | SETBUF_S() |
283 | 7e7c5e4c | balrog | if (onenand_load_spare(s, sec, s->count, buf))
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284 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; |
285 | 7e7c5e4c | balrog | |
286 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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287 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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288 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
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289 | 7e7c5e4c | balrog | */
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290 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; |
291 | 7e7c5e4c | balrog | break;
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292 | 7e7c5e4c | balrog | case 0x80: /* Program single/multiple sector data unit from buffer */ |
293 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
294 | 7e7c5e4c | balrog | |
295 | 7e7c5e4c | balrog | SETBUF_M() |
296 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, s->count, buf))
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297 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
298 | 7e7c5e4c | balrog | |
299 | 7e7c5e4c | balrog | #if 0
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300 | 7e7c5e4c | balrog | SETBUF_S()
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301 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, s->count, buf))
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302 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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303 | 7e7c5e4c | balrog | #endif
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304 | 7e7c5e4c | balrog | |
305 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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306 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
307 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
|
308 | 7e7c5e4c | balrog | */
|
309 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
310 | 7e7c5e4c | balrog | break;
|
311 | 7e7c5e4c | balrog | case 0x1a: /* Program single/multiple spare area sector from buffer */ |
312 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
313 | 7e7c5e4c | balrog | |
314 | 7e7c5e4c | balrog | SETBUF_S() |
315 | 7e7c5e4c | balrog | if (onenand_prog_spare(s, sec, s->count, buf))
|
316 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
317 | 7e7c5e4c | balrog | |
318 | 7e7c5e4c | balrog | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
|
319 | 7e7c5e4c | balrog | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
|
320 | 7e7c5e4c | balrog | * then we need two split the read/write into two chunks.
|
321 | 7e7c5e4c | balrog | */
|
322 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
323 | 7e7c5e4c | balrog | break;
|
324 | 7e7c5e4c | balrog | case 0x1b: /* Copy-back program */ |
325 | 7e7c5e4c | balrog | SETBUF_S() |
326 | 7e7c5e4c | balrog | |
327 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
328 | 7e7c5e4c | balrog | if (onenand_load_main(s, sec, s->count, buf))
|
329 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
330 | 7e7c5e4c | balrog | |
331 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) |
332 | 7e7c5e4c | balrog | if (onenand_prog_main(s, sec, s->count, buf))
|
333 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; |
334 | 7e7c5e4c | balrog | |
335 | 7e7c5e4c | balrog | /* TODO: spare areas */
|
336 | 7e7c5e4c | balrog | |
337 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_PROG; |
338 | 7e7c5e4c | balrog | break;
|
339 | 7e7c5e4c | balrog | |
340 | 7e7c5e4c | balrog | case 0x23: /* Unlock NAND array block(s) */ |
341 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
342 | 7e7c5e4c | balrog | |
343 | 7e7c5e4c | balrog | /* XXX the previous (?) area should be locked automatically */
|
344 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
345 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
346 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
347 | 7e7c5e4c | balrog | break;
|
348 | 7e7c5e4c | balrog | } |
349 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
350 | 7e7c5e4c | balrog | break;
|
351 | 7e7c5e4c | balrog | |
352 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
353 | 7e7c5e4c | balrog | } |
354 | 7e7c5e4c | balrog | break;
|
355 | 89588a4b | balrog | case 0x27: /* Unlock All NAND array blocks */ |
356 | 89588a4b | balrog | s->intstatus |= ONEN_INT; |
357 | 89588a4b | balrog | |
358 | 89588a4b | balrog | for (b = 0; b < s->blocks; b ++) { |
359 | 89588a4b | balrog | if (b >= s->blocks) {
|
360 | 89588a4b | balrog | s->status |= ONEN_ERR_CMD; |
361 | 89588a4b | balrog | break;
|
362 | 89588a4b | balrog | } |
363 | 89588a4b | balrog | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
364 | 89588a4b | balrog | break;
|
365 | 89588a4b | balrog | |
366 | 89588a4b | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; |
367 | 89588a4b | balrog | } |
368 | 89588a4b | balrog | break;
|
369 | 89588a4b | balrog | |
370 | 7e7c5e4c | balrog | case 0x2a: /* Lock NAND array block(s) */ |
371 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
372 | 7e7c5e4c | balrog | |
373 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
374 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
375 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
376 | 7e7c5e4c | balrog | break;
|
377 | 7e7c5e4c | balrog | } |
378 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
|
379 | 7e7c5e4c | balrog | break;
|
380 | 7e7c5e4c | balrog | |
381 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; |
382 | 7e7c5e4c | balrog | } |
383 | 7e7c5e4c | balrog | break;
|
384 | 7e7c5e4c | balrog | case 0x2c: /* Lock-tight NAND array block(s) */ |
385 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
386 | 7e7c5e4c | balrog | |
387 | 7e7c5e4c | balrog | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { |
388 | 7e7c5e4c | balrog | if (b >= s->blocks) {
|
389 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
390 | 7e7c5e4c | balrog | break;
|
391 | 7e7c5e4c | balrog | } |
392 | 7e7c5e4c | balrog | if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
|
393 | 7e7c5e4c | balrog | continue;
|
394 | 7e7c5e4c | balrog | |
395 | 7e7c5e4c | balrog | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; |
396 | 7e7c5e4c | balrog | } |
397 | 7e7c5e4c | balrog | break;
|
398 | 7e7c5e4c | balrog | |
399 | 7e7c5e4c | balrog | case 0x71: /* Erase-Verify-Read */ |
400 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
401 | 7e7c5e4c | balrog | break;
|
402 | 7e7c5e4c | balrog | case 0x95: /* Multi-block erase */ |
403 | 7e7c5e4c | balrog | qemu_irq_pulse(s->intr); |
404 | 7e7c5e4c | balrog | /* Fall through. */
|
405 | 7e7c5e4c | balrog | case 0x94: /* Block erase */ |
406 | 7e7c5e4c | balrog | sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
407 | 7e7c5e4c | balrog | (s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) |
408 | 7e7c5e4c | balrog | << (BLOCK_SHIFT - 9);
|
409 | 7e7c5e4c | balrog | if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) |
410 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; |
411 | 7e7c5e4c | balrog | |
412 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
413 | 7e7c5e4c | balrog | break;
|
414 | 7e7c5e4c | balrog | case 0xb0: /* Erase suspend */ |
415 | 7e7c5e4c | balrog | break;
|
416 | 7e7c5e4c | balrog | case 0x30: /* Erase resume */ |
417 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
418 | 7e7c5e4c | balrog | break;
|
419 | 7e7c5e4c | balrog | |
420 | 7e7c5e4c | balrog | case 0xf0: /* Reset NAND Flash core */ |
421 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
422 | 7e7c5e4c | balrog | break;
|
423 | 7e7c5e4c | balrog | case 0xf3: /* Reset OneNAND */ |
424 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
425 | 7e7c5e4c | balrog | break;
|
426 | 7e7c5e4c | balrog | |
427 | 7e7c5e4c | balrog | case 0x65: /* OTP Access */ |
428 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
429 | b9d38e95 | Blue Swirl | s->bdrv_cur = NULL;
|
430 | 7e7c5e4c | balrog | s->current = s->otp; |
431 | 7e7c5e4c | balrog | s->secs_cur = 1 << (BLOCK_SHIFT - 9); |
432 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_BLOCK] = 0;
|
433 | 7e7c5e4c | balrog | s->otpmode = 1;
|
434 | 7e7c5e4c | balrog | break;
|
435 | 7e7c5e4c | balrog | |
436 | 7e7c5e4c | balrog | default:
|
437 | 7e7c5e4c | balrog | s->status |= ONEN_ERR_CMD; |
438 | 7e7c5e4c | balrog | s->intstatus |= ONEN_INT; |
439 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
440 | 7e7c5e4c | balrog | __FUNCTION__, cmd); |
441 | 7e7c5e4c | balrog | } |
442 | 7e7c5e4c | balrog | |
443 | 7e7c5e4c | balrog | onenand_intr_update(s); |
444 | 7e7c5e4c | balrog | } |
445 | 7e7c5e4c | balrog | |
446 | c227f099 | Anthony Liguori | static uint32_t onenand_read(void *opaque, target_phys_addr_t addr) |
447 | 7e7c5e4c | balrog | { |
448 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) opaque; |
449 | 8da3ff18 | pbrook | int offset = addr >> s->shift;
|
450 | 7e7c5e4c | balrog | |
451 | 7e7c5e4c | balrog | switch (offset) {
|
452 | 7e7c5e4c | balrog | case 0x0000 ... 0xc000: |
453 | 8da3ff18 | pbrook | return lduw_le_p(s->boot[0] + addr); |
454 | 7e7c5e4c | balrog | |
455 | 7e7c5e4c | balrog | case 0xf000: /* Manufacturer ID */ |
456 | 7e7c5e4c | balrog | return (s->id >> 16) & 0xff; |
457 | 7e7c5e4c | balrog | case 0xf001: /* Device ID */ |
458 | 7e7c5e4c | balrog | return (s->id >> 8) & 0xff; |
459 | 7e7c5e4c | balrog | /* TODO: get the following values from a real chip! */
|
460 | 7e7c5e4c | balrog | case 0xf002: /* Version ID */ |
461 | 7e7c5e4c | balrog | return (s->id >> 0) & 0xff; |
462 | 7e7c5e4c | balrog | case 0xf003: /* Data Buffer size */ |
463 | 7e7c5e4c | balrog | return 1 << PAGE_SHIFT; |
464 | 7e7c5e4c | balrog | case 0xf004: /* Boot Buffer size */ |
465 | 7e7c5e4c | balrog | return 0x200; |
466 | 7e7c5e4c | balrog | case 0xf005: /* Amount of buffers */ |
467 | 7e7c5e4c | balrog | return 1 | (2 << 8); |
468 | 7e7c5e4c | balrog | case 0xf006: /* Technology */ |
469 | 7e7c5e4c | balrog | return 0; |
470 | 7e7c5e4c | balrog | |
471 | 7e7c5e4c | balrog | case 0xf100 ... 0xf107: /* Start addresses */ |
472 | 7e7c5e4c | balrog | return s->addr[offset - 0xf100]; |
473 | 7e7c5e4c | balrog | |
474 | 7e7c5e4c | balrog | case 0xf200: /* Start buffer */ |
475 | 7e7c5e4c | balrog | return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
476 | 7e7c5e4c | balrog | |
477 | 7e7c5e4c | balrog | case 0xf220: /* Command */ |
478 | 7e7c5e4c | balrog | return s->command;
|
479 | 7e7c5e4c | balrog | case 0xf221: /* System Configuration 1 */ |
480 | 7e7c5e4c | balrog | return s->config[0] & 0xffe0; |
481 | 7e7c5e4c | balrog | case 0xf222: /* System Configuration 2 */ |
482 | 7e7c5e4c | balrog | return s->config[1]; |
483 | 7e7c5e4c | balrog | |
484 | 7e7c5e4c | balrog | case 0xf240: /* Controller Status */ |
485 | 7e7c5e4c | balrog | return s->status;
|
486 | 7e7c5e4c | balrog | case 0xf241: /* Interrupt */ |
487 | 7e7c5e4c | balrog | return s->intstatus;
|
488 | 7e7c5e4c | balrog | case 0xf24c: /* Unlock Start Block Address */ |
489 | 7e7c5e4c | balrog | return s->unladdr[0]; |
490 | 7e7c5e4c | balrog | case 0xf24d: /* Unlock End Block Address */ |
491 | 7e7c5e4c | balrog | return s->unladdr[1]; |
492 | 7e7c5e4c | balrog | case 0xf24e: /* Write Protection Status */ |
493 | 7e7c5e4c | balrog | return s->wpstatus;
|
494 | 7e7c5e4c | balrog | |
495 | 7e7c5e4c | balrog | case 0xff00: /* ECC Status */ |
496 | 7e7c5e4c | balrog | return 0x00; |
497 | 7e7c5e4c | balrog | case 0xff01: /* ECC Result of main area data */ |
498 | 7e7c5e4c | balrog | case 0xff02: /* ECC Result of spare area data */ |
499 | 7e7c5e4c | balrog | case 0xff03: /* ECC Result of main area data */ |
500 | 7e7c5e4c | balrog | case 0xff04: /* ECC Result of spare area data */ |
501 | 2ac71179 | Paul Brook | hw_error("%s: imeplement ECC\n", __FUNCTION__);
|
502 | 7e7c5e4c | balrog | return 0x0000; |
503 | 7e7c5e4c | balrog | } |
504 | 7e7c5e4c | balrog | |
505 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
506 | 7e7c5e4c | balrog | __FUNCTION__, offset); |
507 | 7e7c5e4c | balrog | return 0; |
508 | 7e7c5e4c | balrog | } |
509 | 7e7c5e4c | balrog | |
510 | c227f099 | Anthony Liguori | static void onenand_write(void *opaque, target_phys_addr_t addr, |
511 | 7e7c5e4c | balrog | uint32_t value) |
512 | 7e7c5e4c | balrog | { |
513 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) opaque; |
514 | 8da3ff18 | pbrook | int offset = addr >> s->shift;
|
515 | 7e7c5e4c | balrog | int sec;
|
516 | 7e7c5e4c | balrog | |
517 | 7e7c5e4c | balrog | switch (offset) {
|
518 | 7e7c5e4c | balrog | case 0x0000 ... 0x01ff: |
519 | 7e7c5e4c | balrog | case 0x8000 ... 0x800f: |
520 | 7e7c5e4c | balrog | if (s->cycle) {
|
521 | 7e7c5e4c | balrog | s->cycle = 0;
|
522 | 7e7c5e4c | balrog | |
523 | 7e7c5e4c | balrog | if (value == 0x0000) { |
524 | 7e7c5e4c | balrog | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
525 | 7e7c5e4c | balrog | onenand_load_main(s, sec, |
526 | 7e7c5e4c | balrog | 1 << (PAGE_SHIFT - 9), s->data[0][0]); |
527 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_PAGE] += 4;
|
528 | 7e7c5e4c | balrog | s->addr[ONEN_BUF_PAGE] &= 0xff;
|
529 | 7e7c5e4c | balrog | } |
530 | 7e7c5e4c | balrog | break;
|
531 | 7e7c5e4c | balrog | } |
532 | 7e7c5e4c | balrog | |
533 | 7e7c5e4c | balrog | switch (value) {
|
534 | 7e7c5e4c | balrog | case 0x00f0: /* Reset OneNAND */ |
535 | 7e7c5e4c | balrog | onenand_reset(s, 0);
|
536 | 7e7c5e4c | balrog | break;
|
537 | 7e7c5e4c | balrog | |
538 | 7e7c5e4c | balrog | case 0x00e0: /* Load Data into Buffer */ |
539 | 7e7c5e4c | balrog | s->cycle = 1;
|
540 | 7e7c5e4c | balrog | break;
|
541 | 7e7c5e4c | balrog | |
542 | 7e7c5e4c | balrog | case 0x0090: /* Read Identification Data */ |
543 | 7e7c5e4c | balrog | memset(s->boot[0], 0, 3 << s->shift); |
544 | 7e7c5e4c | balrog | s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff; |
545 | 7e7c5e4c | balrog | s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff; |
546 | 7e7c5e4c | balrog | s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
547 | 7e7c5e4c | balrog | break;
|
548 | 7e7c5e4c | balrog | |
549 | 7e7c5e4c | balrog | default:
|
550 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
|
551 | 7e7c5e4c | balrog | __FUNCTION__, value); |
552 | 7e7c5e4c | balrog | } |
553 | 7e7c5e4c | balrog | break;
|
554 | 7e7c5e4c | balrog | |
555 | 7e7c5e4c | balrog | case 0xf100 ... 0xf107: /* Start addresses */ |
556 | 7e7c5e4c | balrog | s->addr[offset - 0xf100] = value;
|
557 | 7e7c5e4c | balrog | break;
|
558 | 7e7c5e4c | balrog | |
559 | 7e7c5e4c | balrog | case 0xf200: /* Start buffer */ |
560 | 7e7c5e4c | balrog | s->bufaddr = (value >> 8) & 0xf; |
561 | 7e7c5e4c | balrog | if (PAGE_SHIFT == 11) |
562 | 7e7c5e4c | balrog | s->count = (value & 3) ?: 4; |
563 | 7e7c5e4c | balrog | else if (PAGE_SHIFT == 10) |
564 | 7e7c5e4c | balrog | s->count = (value & 1) ?: 2; |
565 | 7e7c5e4c | balrog | break;
|
566 | 7e7c5e4c | balrog | |
567 | 7e7c5e4c | balrog | case 0xf220: /* Command */ |
568 | 7e7c5e4c | balrog | if (s->intstatus & (1 << 15)) |
569 | 7e7c5e4c | balrog | break;
|
570 | 7e7c5e4c | balrog | s->command = value; |
571 | 7e7c5e4c | balrog | onenand_command(s, s->command); |
572 | 7e7c5e4c | balrog | break;
|
573 | 7e7c5e4c | balrog | case 0xf221: /* System Configuration 1 */ |
574 | 7e7c5e4c | balrog | s->config[0] = value;
|
575 | 7e7c5e4c | balrog | onenand_intr_update(s); |
576 | 7e7c5e4c | balrog | qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); |
577 | 7e7c5e4c | balrog | break;
|
578 | 7e7c5e4c | balrog | case 0xf222: /* System Configuration 2 */ |
579 | 7e7c5e4c | balrog | s->config[1] = value;
|
580 | 7e7c5e4c | balrog | break;
|
581 | 7e7c5e4c | balrog | |
582 | 7e7c5e4c | balrog | case 0xf241: /* Interrupt */ |
583 | 7e7c5e4c | balrog | s->intstatus &= value; |
584 | 7e7c5e4c | balrog | if ((1 << 15) & ~s->intstatus) |
585 | 7e7c5e4c | balrog | s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | |
586 | 7e7c5e4c | balrog | ONEN_ERR_PROG | ONEN_ERR_LOAD); |
587 | 7e7c5e4c | balrog | onenand_intr_update(s); |
588 | 7e7c5e4c | balrog | break;
|
589 | 7e7c5e4c | balrog | case 0xf24c: /* Unlock Start Block Address */ |
590 | 7e7c5e4c | balrog | s->unladdr[0] = value & (s->blocks - 1); |
591 | 7e7c5e4c | balrog | /* For some reason we have to set the end address to by default
|
592 | 7e7c5e4c | balrog | * be same as start because the software forgets to write anything
|
593 | 7e7c5e4c | balrog | * in there. */
|
594 | 7e7c5e4c | balrog | s->unladdr[1] = value & (s->blocks - 1); |
595 | 7e7c5e4c | balrog | break;
|
596 | 7e7c5e4c | balrog | case 0xf24d: /* Unlock End Block Address */ |
597 | 7e7c5e4c | balrog | s->unladdr[1] = value & (s->blocks - 1); |
598 | 7e7c5e4c | balrog | break;
|
599 | 7e7c5e4c | balrog | |
600 | 7e7c5e4c | balrog | default:
|
601 | 7e7c5e4c | balrog | fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
602 | 7e7c5e4c | balrog | __FUNCTION__, offset); |
603 | 7e7c5e4c | balrog | } |
604 | 7e7c5e4c | balrog | } |
605 | 7e7c5e4c | balrog | |
606 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const onenand_readfn[] = { |
607 | 7e7c5e4c | balrog | onenand_read, /* TODO */
|
608 | 7e7c5e4c | balrog | onenand_read, |
609 | 7e7c5e4c | balrog | onenand_read, |
610 | 7e7c5e4c | balrog | }; |
611 | 7e7c5e4c | balrog | |
612 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const onenand_writefn[] = { |
613 | 7e7c5e4c | balrog | onenand_write, /* TODO */
|
614 | 7e7c5e4c | balrog | onenand_write, |
615 | 7e7c5e4c | balrog | onenand_write, |
616 | 7e7c5e4c | balrog | }; |
617 | 7e7c5e4c | balrog | |
618 | 7e7c5e4c | balrog | void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
619 | 7e7c5e4c | balrog | { |
620 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
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621 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); |
622 | 7e7c5e4c | balrog | uint32_t size = 1 << (24 + ((id >> 12) & 7)); |
623 | 7e7c5e4c | balrog | void *ram;
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624 | 7e7c5e4c | balrog | |
625 | 7e7c5e4c | balrog | s->shift = regshift; |
626 | 7e7c5e4c | balrog | s->intr = irq; |
627 | b9d38e95 | Blue Swirl | s->rdy = NULL;
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628 | 7e7c5e4c | balrog | s->id = id; |
629 | 7e7c5e4c | balrog | s->blocks = size >> BLOCK_SHIFT; |
630 | 7e7c5e4c | balrog | s->secs = size >> 9;
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631 | 7e7c5e4c | balrog | s->blockwp = qemu_malloc(s->blocks); |
632 | 7e7c5e4c | balrog | s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0; |
633 | 1eed09cb | Avi Kivity | s->iomemtype = cpu_register_io_memory(onenand_readfn, |
634 | 7e7c5e4c | balrog | onenand_writefn, s); |
635 | 751c6a17 | Gerd Hoffmann | if (!dinfo)
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636 | 7e7c5e4c | balrog | s->image = memset(qemu_malloc(size + (size >> 5)),
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637 | 7e7c5e4c | balrog | 0xff, size + (size >> 5)); |
638 | 7e7c5e4c | balrog | else
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639 | 751c6a17 | Gerd Hoffmann | s->bdrv = dinfo->bdrv; |
640 | 7e7c5e4c | balrog | s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
641 | 7e7c5e4c | balrog | 0xff, (64 + 2) << PAGE_SHIFT); |
642 | 7e7c5e4c | balrog | s->ram = qemu_ram_alloc(0xc000 << s->shift);
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643 | 5c130f65 | pbrook | ram = qemu_get_ram_ptr(s->ram); |
644 | 7e7c5e4c | balrog | s->boot[0] = ram + (0x0000 << s->shift); |
645 | 7e7c5e4c | balrog | s->boot[1] = ram + (0x8000 << s->shift); |
646 | 7e7c5e4c | balrog | s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); |
647 | 7e7c5e4c | balrog | s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); |
648 | 7e7c5e4c | balrog | s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); |
649 | 7e7c5e4c | balrog | s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); |
650 | 7e7c5e4c | balrog | |
651 | 7e7c5e4c | balrog | onenand_reset(s, 1);
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652 | 7e7c5e4c | balrog | |
653 | 7e7c5e4c | balrog | return s;
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654 | 7e7c5e4c | balrog | } |
655 | c580d92b | balrog | |
656 | c580d92b | balrog | void *onenand_raw_otp(void *opaque) |
657 | c580d92b | balrog | { |
658 | bc24a225 | Paul Brook | OneNANDState *s = (OneNANDState *) opaque; |
659 | c580d92b | balrog | |
660 | c580d92b | balrog | return s->otp;
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661 | c580d92b | balrog | } |