root / hw / ppc4xx.h @ ba5e5090
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1 | 008ff9d7 | j_mayer | /*
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2 | 008ff9d7 | j_mayer | * QEMU PowerPC 4xx emulation shared definitions
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3 | 008ff9d7 | j_mayer | *
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4 | 008ff9d7 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 008ff9d7 | j_mayer | *
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6 | 008ff9d7 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 008ff9d7 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 008ff9d7 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 008ff9d7 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 008ff9d7 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 008ff9d7 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 008ff9d7 | j_mayer | *
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13 | 008ff9d7 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 008ff9d7 | j_mayer | * all copies or substantial portions of the Software.
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15 | 008ff9d7 | j_mayer | *
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16 | 008ff9d7 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 008ff9d7 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 008ff9d7 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 008ff9d7 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 008ff9d7 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 008ff9d7 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 008ff9d7 | j_mayer | * THE SOFTWARE.
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23 | 008ff9d7 | j_mayer | */
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24 | 008ff9d7 | j_mayer | |
25 | 008ff9d7 | j_mayer | #if !defined(PPC_4XX_H)
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26 | 008ff9d7 | j_mayer | #define PPC_4XX_H
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27 | 008ff9d7 | j_mayer | |
28 | 825bb581 | aurel32 | #include "pci.h" |
29 | 825bb581 | aurel32 | |
30 | 008ff9d7 | j_mayer | /* PowerPC 4xx core initialization */
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31 | b55266b5 | blueswir1 | CPUState *ppc4xx_init (const char *cpu_model, |
32 | c227f099 | Anthony Liguori | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
33 | 008ff9d7 | j_mayer | uint32_t sysclk); |
34 | 008ff9d7 | j_mayer | |
35 | 008ff9d7 | j_mayer | /* PowerPC 4xx universal interrupt controller */
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36 | 008ff9d7 | j_mayer | enum {
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37 | 008ff9d7 | j_mayer | PPCUIC_OUTPUT_INT = 0,
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38 | 008ff9d7 | j_mayer | PPCUIC_OUTPUT_CINT = 1,
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39 | 008ff9d7 | j_mayer | PPCUIC_OUTPUT_NB, |
40 | 008ff9d7 | j_mayer | }; |
41 | 008ff9d7 | j_mayer | qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
42 | 008ff9d7 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr); |
43 | 008ff9d7 | j_mayer | |
44 | c227f099 | Anthony Liguori | ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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45 | c227f099 | Anthony Liguori | target_phys_addr_t ram_bases[], |
46 | c227f099 | Anthony Liguori | target_phys_addr_t ram_sizes[], |
47 | b7da58fd | aurel32 | const unsigned int sdram_bank_sizes[]); |
48 | b7da58fd | aurel32 | |
49 | 80e8bd2b | aurel32 | void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
50 | c227f099 | Anthony Liguori | target_phys_addr_t *ram_bases, |
51 | c227f099 | Anthony Liguori | target_phys_addr_t *ram_sizes, |
52 | 61b24405 | aurel32 | int do_init);
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53 | 61b24405 | aurel32 | |
54 | 825bb581 | aurel32 | PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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55 | c227f099 | Anthony Liguori | target_phys_addr_t config_space, |
56 | c227f099 | Anthony Liguori | target_phys_addr_t int_ack, |
57 | c227f099 | Anthony Liguori | target_phys_addr_t special_cycle, |
58 | c227f099 | Anthony Liguori | target_phys_addr_t registers); |
59 | 825bb581 | aurel32 | |
60 | 008ff9d7 | j_mayer | #endif /* !defined(PPC_4XX_H) */ |