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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 micro operations
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | f68dd770 | bellard | |
21 | f68dd770 | bellard | #define ASM_SOFTMMU
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22 | 2c0262af | bellard | #include "exec.h" |
23 | 2c0262af | bellard | |
24 | 2c0262af | bellard | /* n must be a constant to be efficient */
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25 | 14ce26e7 | bellard | static inline target_long lshift(target_long x, int n) |
26 | 2c0262af | bellard | { |
27 | 2c0262af | bellard | if (n >= 0) |
28 | 2c0262af | bellard | return x << n;
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29 | 2c0262af | bellard | else
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30 | 2c0262af | bellard | return x >> (-n);
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31 | 2c0262af | bellard | } |
32 | 2c0262af | bellard | |
33 | 2c0262af | bellard | /* we define the various pieces of code used by the JIT */
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34 | 2c0262af | bellard | |
35 | 2c0262af | bellard | #define REG EAX
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36 | 2c0262af | bellard | #define REGNAME _EAX
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37 | 2c0262af | bellard | #include "opreg_template.h" |
38 | 2c0262af | bellard | #undef REG
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39 | 2c0262af | bellard | #undef REGNAME
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40 | 2c0262af | bellard | |
41 | 2c0262af | bellard | #define REG ECX
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42 | 2c0262af | bellard | #define REGNAME _ECX
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43 | 2c0262af | bellard | #include "opreg_template.h" |
44 | 2c0262af | bellard | #undef REG
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45 | 2c0262af | bellard | #undef REGNAME
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46 | 2c0262af | bellard | |
47 | 2c0262af | bellard | #define REG EDX
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48 | 2c0262af | bellard | #define REGNAME _EDX
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49 | 2c0262af | bellard | #include "opreg_template.h" |
50 | 2c0262af | bellard | #undef REG
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51 | 2c0262af | bellard | #undef REGNAME
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52 | 2c0262af | bellard | |
53 | 2c0262af | bellard | #define REG EBX
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54 | 2c0262af | bellard | #define REGNAME _EBX
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55 | 2c0262af | bellard | #include "opreg_template.h" |
56 | 2c0262af | bellard | #undef REG
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57 | 2c0262af | bellard | #undef REGNAME
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58 | 2c0262af | bellard | |
59 | 2c0262af | bellard | #define REG ESP
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60 | 2c0262af | bellard | #define REGNAME _ESP
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61 | 2c0262af | bellard | #include "opreg_template.h" |
62 | 2c0262af | bellard | #undef REG
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63 | 2c0262af | bellard | #undef REGNAME
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64 | 2c0262af | bellard | |
65 | 2c0262af | bellard | #define REG EBP
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66 | 2c0262af | bellard | #define REGNAME _EBP
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67 | 2c0262af | bellard | #include "opreg_template.h" |
68 | 2c0262af | bellard | #undef REG
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69 | 2c0262af | bellard | #undef REGNAME
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70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | #define REG ESI
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72 | 2c0262af | bellard | #define REGNAME _ESI
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73 | 2c0262af | bellard | #include "opreg_template.h" |
74 | 2c0262af | bellard | #undef REG
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75 | 2c0262af | bellard | #undef REGNAME
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76 | 2c0262af | bellard | |
77 | 2c0262af | bellard | #define REG EDI
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78 | 2c0262af | bellard | #define REGNAME _EDI
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79 | 2c0262af | bellard | #include "opreg_template.h" |
80 | 2c0262af | bellard | #undef REG
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81 | 2c0262af | bellard | #undef REGNAME
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82 | 2c0262af | bellard | |
83 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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84 | 14ce26e7 | bellard | |
85 | 14ce26e7 | bellard | #define REG (env->regs[8]) |
86 | 14ce26e7 | bellard | #define REGNAME _R8
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87 | 14ce26e7 | bellard | #include "opreg_template.h" |
88 | 14ce26e7 | bellard | #undef REG
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89 | 14ce26e7 | bellard | #undef REGNAME
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90 | 14ce26e7 | bellard | |
91 | 14ce26e7 | bellard | #define REG (env->regs[9]) |
92 | 14ce26e7 | bellard | #define REGNAME _R9
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93 | 14ce26e7 | bellard | #include "opreg_template.h" |
94 | 14ce26e7 | bellard | #undef REG
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95 | 14ce26e7 | bellard | #undef REGNAME
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96 | 14ce26e7 | bellard | |
97 | 14ce26e7 | bellard | #define REG (env->regs[10]) |
98 | 14ce26e7 | bellard | #define REGNAME _R10
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99 | 14ce26e7 | bellard | #include "opreg_template.h" |
100 | 14ce26e7 | bellard | #undef REG
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101 | 14ce26e7 | bellard | #undef REGNAME
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102 | 14ce26e7 | bellard | |
103 | 14ce26e7 | bellard | #define REG (env->regs[11]) |
104 | 14ce26e7 | bellard | #define REGNAME _R11
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105 | 14ce26e7 | bellard | #include "opreg_template.h" |
106 | 14ce26e7 | bellard | #undef REG
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107 | 14ce26e7 | bellard | #undef REGNAME
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108 | 14ce26e7 | bellard | |
109 | 14ce26e7 | bellard | #define REG (env->regs[12]) |
110 | 14ce26e7 | bellard | #define REGNAME _R12
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111 | 14ce26e7 | bellard | #include "opreg_template.h" |
112 | 14ce26e7 | bellard | #undef REG
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113 | 14ce26e7 | bellard | #undef REGNAME
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114 | 14ce26e7 | bellard | |
115 | 14ce26e7 | bellard | #define REG (env->regs[13]) |
116 | 14ce26e7 | bellard | #define REGNAME _R13
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117 | 14ce26e7 | bellard | #include "opreg_template.h" |
118 | 14ce26e7 | bellard | #undef REG
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119 | 14ce26e7 | bellard | #undef REGNAME
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120 | 14ce26e7 | bellard | |
121 | 14ce26e7 | bellard | #define REG (env->regs[14]) |
122 | 14ce26e7 | bellard | #define REGNAME _R14
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123 | 14ce26e7 | bellard | #include "opreg_template.h" |
124 | 14ce26e7 | bellard | #undef REG
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125 | 14ce26e7 | bellard | #undef REGNAME
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126 | 14ce26e7 | bellard | |
127 | 14ce26e7 | bellard | #define REG (env->regs[15]) |
128 | 14ce26e7 | bellard | #define REGNAME _R15
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129 | 14ce26e7 | bellard | #include "opreg_template.h" |
130 | 14ce26e7 | bellard | #undef REG
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131 | 14ce26e7 | bellard | #undef REGNAME
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132 | 14ce26e7 | bellard | |
133 | 14ce26e7 | bellard | #endif
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134 | 14ce26e7 | bellard | |
135 | 2c0262af | bellard | /* operations with flags */
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136 | 2c0262af | bellard | |
137 | 2c0262af | bellard | /* update flags with T0 and T1 (add/sub case) */
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138 | 2c0262af | bellard | void OPPROTO op_update2_cc(void) |
139 | 2c0262af | bellard | { |
140 | 2c0262af | bellard | CC_SRC = T1; |
141 | 2c0262af | bellard | CC_DST = T0; |
142 | 2c0262af | bellard | } |
143 | 2c0262af | bellard | |
144 | 2c0262af | bellard | /* update flags with T0 (logic operation case) */
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145 | 2c0262af | bellard | void OPPROTO op_update1_cc(void) |
146 | 2c0262af | bellard | { |
147 | 2c0262af | bellard | CC_DST = T0; |
148 | 2c0262af | bellard | } |
149 | 2c0262af | bellard | |
150 | 2c0262af | bellard | void OPPROTO op_update_neg_cc(void) |
151 | 2c0262af | bellard | { |
152 | 2c0262af | bellard | CC_SRC = -T0; |
153 | 2c0262af | bellard | CC_DST = T0; |
154 | 2c0262af | bellard | } |
155 | 2c0262af | bellard | |
156 | 2c0262af | bellard | void OPPROTO op_cmpl_T0_T1_cc(void) |
157 | 2c0262af | bellard | { |
158 | 2c0262af | bellard | CC_SRC = T1; |
159 | 2c0262af | bellard | CC_DST = T0 - T1; |
160 | 2c0262af | bellard | } |
161 | 2c0262af | bellard | |
162 | 2c0262af | bellard | void OPPROTO op_update_inc_cc(void) |
163 | 2c0262af | bellard | { |
164 | 2c0262af | bellard | CC_SRC = cc_table[CC_OP].compute_c(); |
165 | 2c0262af | bellard | CC_DST = T0; |
166 | 2c0262af | bellard | } |
167 | 2c0262af | bellard | |
168 | 2c0262af | bellard | void OPPROTO op_testl_T0_T1_cc(void) |
169 | 2c0262af | bellard | { |
170 | 2c0262af | bellard | CC_DST = T0 & T1; |
171 | 2c0262af | bellard | } |
172 | 2c0262af | bellard | |
173 | 2c0262af | bellard | /* operations without flags */
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174 | 2c0262af | bellard | |
175 | 2c0262af | bellard | void OPPROTO op_negl_T0(void) |
176 | 2c0262af | bellard | { |
177 | 2c0262af | bellard | T0 = -T0; |
178 | 2c0262af | bellard | } |
179 | 2c0262af | bellard | |
180 | 2c0262af | bellard | void OPPROTO op_incl_T0(void) |
181 | 2c0262af | bellard | { |
182 | 2c0262af | bellard | T0++; |
183 | 2c0262af | bellard | } |
184 | 2c0262af | bellard | |
185 | 2c0262af | bellard | void OPPROTO op_decl_T0(void) |
186 | 2c0262af | bellard | { |
187 | 2c0262af | bellard | T0--; |
188 | 2c0262af | bellard | } |
189 | 2c0262af | bellard | |
190 | 2c0262af | bellard | void OPPROTO op_notl_T0(void) |
191 | 2c0262af | bellard | { |
192 | 2c0262af | bellard | T0 = ~T0; |
193 | 2c0262af | bellard | } |
194 | 2c0262af | bellard | |
195 | 2c0262af | bellard | /* multiply/divide */
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196 | d36cd60e | bellard | |
197 | d36cd60e | bellard | /* XXX: add eflags optimizations */
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198 | d36cd60e | bellard | /* XXX: add non P4 style flags */
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199 | d36cd60e | bellard | |
200 | 2c0262af | bellard | void OPPROTO op_mulb_AL_T0(void) |
201 | 2c0262af | bellard | { |
202 | 2c0262af | bellard | unsigned int res; |
203 | 2c0262af | bellard | res = (uint8_t)EAX * (uint8_t)T0; |
204 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | res;
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205 | d36cd60e | bellard | CC_DST = res; |
206 | 2c0262af | bellard | CC_SRC = (res & 0xff00);
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207 | 2c0262af | bellard | } |
208 | 2c0262af | bellard | |
209 | 2c0262af | bellard | void OPPROTO op_imulb_AL_T0(void) |
210 | 2c0262af | bellard | { |
211 | 2c0262af | bellard | int res;
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212 | 2c0262af | bellard | res = (int8_t)EAX * (int8_t)T0; |
213 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
214 | d36cd60e | bellard | CC_DST = res; |
215 | 2c0262af | bellard | CC_SRC = (res != (int8_t)res); |
216 | 2c0262af | bellard | } |
217 | 2c0262af | bellard | |
218 | 2c0262af | bellard | void OPPROTO op_mulw_AX_T0(void) |
219 | 2c0262af | bellard | { |
220 | 2c0262af | bellard | unsigned int res; |
221 | 2c0262af | bellard | res = (uint16_t)EAX * (uint16_t)T0; |
222 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
223 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
224 | d36cd60e | bellard | CC_DST = res; |
225 | 2c0262af | bellard | CC_SRC = res >> 16;
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226 | 2c0262af | bellard | } |
227 | 2c0262af | bellard | |
228 | 2c0262af | bellard | void OPPROTO op_imulw_AX_T0(void) |
229 | 2c0262af | bellard | { |
230 | 2c0262af | bellard | int res;
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231 | 2c0262af | bellard | res = (int16_t)EAX * (int16_t)T0; |
232 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (res & 0xffff); |
233 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | ((res >> 16) & 0xffff); |
234 | d36cd60e | bellard | CC_DST = res; |
235 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
236 | 2c0262af | bellard | } |
237 | 2c0262af | bellard | |
238 | 2c0262af | bellard | void OPPROTO op_mull_EAX_T0(void) |
239 | 2c0262af | bellard | { |
240 | 2c0262af | bellard | uint64_t res; |
241 | 2c0262af | bellard | res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0); |
242 | 14ce26e7 | bellard | EAX = (uint32_t)res; |
243 | 14ce26e7 | bellard | EDX = (uint32_t)(res >> 32);
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244 | 14ce26e7 | bellard | CC_DST = (uint32_t)res; |
245 | 14ce26e7 | bellard | CC_SRC = (uint32_t)(res >> 32);
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246 | 2c0262af | bellard | } |
247 | 2c0262af | bellard | |
248 | 2c0262af | bellard | void OPPROTO op_imull_EAX_T0(void) |
249 | 2c0262af | bellard | { |
250 | 2c0262af | bellard | int64_t res; |
251 | 2c0262af | bellard | res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0); |
252 | 31313213 | bellard | EAX = (uint32_t)(res); |
253 | 31313213 | bellard | EDX = (uint32_t)(res >> 32);
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254 | d36cd60e | bellard | CC_DST = res; |
255 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
256 | 2c0262af | bellard | } |
257 | 2c0262af | bellard | |
258 | 2c0262af | bellard | void OPPROTO op_imulw_T0_T1(void) |
259 | 2c0262af | bellard | { |
260 | 2c0262af | bellard | int res;
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261 | 2c0262af | bellard | res = (int16_t)T0 * (int16_t)T1; |
262 | 2c0262af | bellard | T0 = res; |
263 | d36cd60e | bellard | CC_DST = res; |
264 | 2c0262af | bellard | CC_SRC = (res != (int16_t)res); |
265 | 2c0262af | bellard | } |
266 | 2c0262af | bellard | |
267 | 2c0262af | bellard | void OPPROTO op_imull_T0_T1(void) |
268 | 2c0262af | bellard | { |
269 | 2c0262af | bellard | int64_t res; |
270 | 2c0262af | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
271 | 2c0262af | bellard | T0 = res; |
272 | d36cd60e | bellard | CC_DST = res; |
273 | 2c0262af | bellard | CC_SRC = (res != (int32_t)res); |
274 | 2c0262af | bellard | } |
275 | 2c0262af | bellard | |
276 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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277 | 14ce26e7 | bellard | void OPPROTO op_mulq_EAX_T0(void) |
278 | 14ce26e7 | bellard | { |
279 | 14ce26e7 | bellard | helper_mulq_EAX_T0(); |
280 | 14ce26e7 | bellard | } |
281 | 14ce26e7 | bellard | |
282 | 14ce26e7 | bellard | void OPPROTO op_imulq_EAX_T0(void) |
283 | 14ce26e7 | bellard | { |
284 | 14ce26e7 | bellard | helper_imulq_EAX_T0(); |
285 | 14ce26e7 | bellard | } |
286 | 14ce26e7 | bellard | |
287 | 14ce26e7 | bellard | void OPPROTO op_imulq_T0_T1(void) |
288 | 14ce26e7 | bellard | { |
289 | 14ce26e7 | bellard | helper_imulq_T0_T1(); |
290 | 14ce26e7 | bellard | } |
291 | 14ce26e7 | bellard | #endif
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292 | 14ce26e7 | bellard | |
293 | 2c0262af | bellard | /* division, flags are undefined */
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294 | 2c0262af | bellard | |
295 | 2c0262af | bellard | void OPPROTO op_divb_AL_T0(void) |
296 | 2c0262af | bellard | { |
297 | 2c0262af | bellard | unsigned int num, den, q, r; |
298 | 2c0262af | bellard | |
299 | 2c0262af | bellard | num = (EAX & 0xffff);
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300 | 2c0262af | bellard | den = (T0 & 0xff);
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301 | 2c0262af | bellard | if (den == 0) { |
302 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
303 | 2c0262af | bellard | } |
304 | 45bbbb46 | bellard | q = (num / den); |
305 | 45bbbb46 | bellard | if (q > 0xff) |
306 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
307 | 45bbbb46 | bellard | q &= 0xff;
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308 | 2c0262af | bellard | r = (num % den) & 0xff;
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309 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (r << 8) | q; |
310 | 2c0262af | bellard | } |
311 | 2c0262af | bellard | |
312 | 2c0262af | bellard | void OPPROTO op_idivb_AL_T0(void) |
313 | 2c0262af | bellard | { |
314 | 2c0262af | bellard | int num, den, q, r;
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315 | 2c0262af | bellard | |
316 | 2c0262af | bellard | num = (int16_t)EAX; |
317 | 2c0262af | bellard | den = (int8_t)T0; |
318 | 2c0262af | bellard | if (den == 0) { |
319 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
320 | 2c0262af | bellard | } |
321 | 45bbbb46 | bellard | q = (num / den); |
322 | 45bbbb46 | bellard | if (q != (int8_t)q)
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323 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
324 | 45bbbb46 | bellard | q &= 0xff;
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325 | 2c0262af | bellard | r = (num % den) & 0xff;
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326 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | (r << 8) | q; |
327 | 2c0262af | bellard | } |
328 | 2c0262af | bellard | |
329 | 2c0262af | bellard | void OPPROTO op_divw_AX_T0(void) |
330 | 2c0262af | bellard | { |
331 | 2c0262af | bellard | unsigned int num, den, q, r; |
332 | 2c0262af | bellard | |
333 | 2c0262af | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
334 | 2c0262af | bellard | den = (T0 & 0xffff);
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335 | 2c0262af | bellard | if (den == 0) { |
336 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
337 | 2c0262af | bellard | } |
338 | 45bbbb46 | bellard | q = (num / den); |
339 | 45bbbb46 | bellard | if (q > 0xffff) |
340 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
341 | 45bbbb46 | bellard | q &= 0xffff;
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342 | 2c0262af | bellard | r = (num % den) & 0xffff;
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343 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | q;
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344 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | r;
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345 | 2c0262af | bellard | } |
346 | 2c0262af | bellard | |
347 | 2c0262af | bellard | void OPPROTO op_idivw_AX_T0(void) |
348 | 2c0262af | bellard | { |
349 | 2c0262af | bellard | int num, den, q, r;
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350 | 2c0262af | bellard | |
351 | 2c0262af | bellard | num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); |
352 | 2c0262af | bellard | den = (int16_t)T0; |
353 | 2c0262af | bellard | if (den == 0) { |
354 | 2c0262af | bellard | raise_exception(EXCP00_DIVZ); |
355 | 2c0262af | bellard | } |
356 | 45bbbb46 | bellard | q = (num / den); |
357 | 45bbbb46 | bellard | if (q != (int16_t)q)
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358 | 45bbbb46 | bellard | raise_exception(EXCP00_DIVZ); |
359 | 45bbbb46 | bellard | q &= 0xffff;
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360 | 2c0262af | bellard | r = (num % den) & 0xffff;
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361 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | q;
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362 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | r;
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363 | 2c0262af | bellard | } |
364 | 2c0262af | bellard | |
365 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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366 | 14ce26e7 | bellard | void OPPROTO op_divq_EAX_T0(void) |
367 | 14ce26e7 | bellard | { |
368 | 14ce26e7 | bellard | helper_divq_EAX_T0(); |
369 | 14ce26e7 | bellard | } |
370 | 14ce26e7 | bellard | |
371 | 14ce26e7 | bellard | void OPPROTO op_idivq_EAX_T0(void) |
372 | 14ce26e7 | bellard | { |
373 | 14ce26e7 | bellard | helper_idivq_EAX_T0(); |
374 | 14ce26e7 | bellard | } |
375 | 14ce26e7 | bellard | #endif
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376 | 14ce26e7 | bellard | |
377 | 2c0262af | bellard | /* constant load & misc op */
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378 | 2c0262af | bellard | |
379 | 14ce26e7 | bellard | /* XXX: consistent names */
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380 | 2c0262af | bellard | void OPPROTO op_addl_T1_im(void) |
381 | 2c0262af | bellard | { |
382 | 2c0262af | bellard | T1 += PARAM1; |
383 | 2c0262af | bellard | } |
384 | 2c0262af | bellard | |
385 | 2c0262af | bellard | void OPPROTO op_movl_T1_A0(void) |
386 | 2c0262af | bellard | { |
387 | 2c0262af | bellard | T1 = A0; |
388 | 2c0262af | bellard | } |
389 | 2c0262af | bellard | |
390 | 2c0262af | bellard | void OPPROTO op_addl_A0_AL(void) |
391 | 2c0262af | bellard | { |
392 | 14ce26e7 | bellard | A0 = (uint32_t)(A0 + (EAX & 0xff));
|
393 | 14ce26e7 | bellard | } |
394 | 14ce26e7 | bellard | |
395 | 14ce26e7 | bellard | #ifdef WORDS_BIGENDIAN
|
396 | 14ce26e7 | bellard | typedef union UREG64 { |
397 | 14ce26e7 | bellard | struct { uint16_t v3, v2, v1, v0; } w;
|
398 | 14ce26e7 | bellard | struct { uint32_t v1, v0; } l;
|
399 | 14ce26e7 | bellard | uint64_t q; |
400 | 14ce26e7 | bellard | } UREG64; |
401 | 14ce26e7 | bellard | #else
|
402 | 14ce26e7 | bellard | typedef union UREG64 { |
403 | 14ce26e7 | bellard | struct { uint16_t v0, v1, v2, v3; } w;
|
404 | 14ce26e7 | bellard | struct { uint32_t v0, v1; } l;
|
405 | 14ce26e7 | bellard | uint64_t q; |
406 | 14ce26e7 | bellard | } UREG64; |
407 | 14ce26e7 | bellard | #endif
|
408 | 14ce26e7 | bellard | |
409 | 14ce26e7 | bellard | #define PARAMQ1 \
|
410 | 14ce26e7 | bellard | ({\ |
411 | 14ce26e7 | bellard | UREG64 __p;\ |
412 | 14ce26e7 | bellard | __p.l.v1 = PARAM1;\ |
413 | 14ce26e7 | bellard | __p.l.v0 = PARAM2;\ |
414 | 14ce26e7 | bellard | __p.q;\ |
415 | 5fafdf24 | ths | }) |
416 | 14ce26e7 | bellard | |
417 | 0573fbfc | ths | #ifdef TARGET_X86_64
|
418 | 0573fbfc | ths | |
419 | 14ce26e7 | bellard | void OPPROTO op_addq_A0_AL(void) |
420 | 14ce26e7 | bellard | { |
421 | 14ce26e7 | bellard | A0 = (A0 + (EAX & 0xff));
|
422 | 14ce26e7 | bellard | } |
423 | 14ce26e7 | bellard | |
424 | 14ce26e7 | bellard | #endif
|
425 | 14ce26e7 | bellard | |
426 | 2c0262af | bellard | void OPPROTO op_hlt(void) |
427 | 2c0262af | bellard | { |
428 | 3d7374c5 | bellard | helper_hlt(); |
429 | 3d7374c5 | bellard | } |
430 | 3d7374c5 | bellard | |
431 | 3d7374c5 | bellard | void OPPROTO op_monitor(void) |
432 | 3d7374c5 | bellard | { |
433 | 3d7374c5 | bellard | helper_monitor(); |
434 | 3d7374c5 | bellard | } |
435 | 3d7374c5 | bellard | |
436 | 3d7374c5 | bellard | void OPPROTO op_mwait(void) |
437 | 3d7374c5 | bellard | { |
438 | 3d7374c5 | bellard | helper_mwait(); |
439 | 2c0262af | bellard | } |
440 | 2c0262af | bellard | |
441 | 2c0262af | bellard | void OPPROTO op_debug(void) |
442 | 2c0262af | bellard | { |
443 | 2c0262af | bellard | env->exception_index = EXCP_DEBUG; |
444 | 2c0262af | bellard | cpu_loop_exit(); |
445 | 2c0262af | bellard | } |
446 | 2c0262af | bellard | |
447 | 2c0262af | bellard | void OPPROTO op_raise_interrupt(void) |
448 | 2c0262af | bellard | { |
449 | a8ede8ba | bellard | int intno, next_eip_addend;
|
450 | 2c0262af | bellard | intno = PARAM1; |
451 | a8ede8ba | bellard | next_eip_addend = PARAM2; |
452 | a8ede8ba | bellard | raise_interrupt(intno, 1, 0, next_eip_addend); |
453 | 2c0262af | bellard | } |
454 | 2c0262af | bellard | |
455 | 2c0262af | bellard | void OPPROTO op_raise_exception(void) |
456 | 2c0262af | bellard | { |
457 | 2c0262af | bellard | int exception_index;
|
458 | 2c0262af | bellard | exception_index = PARAM1; |
459 | 2c0262af | bellard | raise_exception(exception_index); |
460 | 2c0262af | bellard | } |
461 | 2c0262af | bellard | |
462 | 2c0262af | bellard | void OPPROTO op_into(void) |
463 | 2c0262af | bellard | { |
464 | 2c0262af | bellard | int eflags;
|
465 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
466 | 2c0262af | bellard | if (eflags & CC_O) {
|
467 | 2c0262af | bellard | raise_interrupt(EXCP04_INTO, 1, 0, PARAM1); |
468 | 2c0262af | bellard | } |
469 | 2c0262af | bellard | FORCE_RET(); |
470 | 2c0262af | bellard | } |
471 | 2c0262af | bellard | |
472 | 2c0262af | bellard | void OPPROTO op_cli(void) |
473 | 2c0262af | bellard | { |
474 | 2c0262af | bellard | env->eflags &= ~IF_MASK; |
475 | 2c0262af | bellard | } |
476 | 2c0262af | bellard | |
477 | 2c0262af | bellard | void OPPROTO op_sti(void) |
478 | 2c0262af | bellard | { |
479 | 2c0262af | bellard | env->eflags |= IF_MASK; |
480 | 2c0262af | bellard | } |
481 | 2c0262af | bellard | |
482 | 2c0262af | bellard | void OPPROTO op_set_inhibit_irq(void) |
483 | 2c0262af | bellard | { |
484 | 2c0262af | bellard | env->hflags |= HF_INHIBIT_IRQ_MASK; |
485 | 2c0262af | bellard | } |
486 | 2c0262af | bellard | |
487 | 2c0262af | bellard | void OPPROTO op_reset_inhibit_irq(void) |
488 | 2c0262af | bellard | { |
489 | 2c0262af | bellard | env->hflags &= ~HF_INHIBIT_IRQ_MASK; |
490 | 2c0262af | bellard | } |
491 | 2c0262af | bellard | |
492 | 3b21e03e | bellard | void OPPROTO op_rsm(void) |
493 | 3b21e03e | bellard | { |
494 | 3b21e03e | bellard | helper_rsm(); |
495 | 3b21e03e | bellard | } |
496 | 3b21e03e | bellard | |
497 | 2c0262af | bellard | #if 0
|
498 | 2c0262af | bellard | /* vm86plus instructions */
|
499 | 2c0262af | bellard | void OPPROTO op_cli_vm(void)
|
500 | 2c0262af | bellard | {
|
501 | 2c0262af | bellard | env->eflags &= ~VIF_MASK;
|
502 | 2c0262af | bellard | }
|
503 | 2c0262af | bellard | |
504 | 2c0262af | bellard | void OPPROTO op_sti_vm(void)
|
505 | 2c0262af | bellard | {
|
506 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
507 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
508 | 2c0262af | bellard | EIP = PARAM1;
|
509 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
510 | 2c0262af | bellard | }
|
511 | 2c0262af | bellard | FORCE_RET();
|
512 | 2c0262af | bellard | }
|
513 | 2c0262af | bellard | #endif
|
514 | 2c0262af | bellard | |
515 | 2c0262af | bellard | void OPPROTO op_boundw(void) |
516 | 2c0262af | bellard | { |
517 | 2c0262af | bellard | int low, high, v;
|
518 | 14ce26e7 | bellard | low = ldsw(A0); |
519 | 14ce26e7 | bellard | high = ldsw(A0 + 2);
|
520 | 2c0262af | bellard | v = (int16_t)T0; |
521 | 2c0262af | bellard | if (v < low || v > high) {
|
522 | 2c0262af | bellard | raise_exception(EXCP05_BOUND); |
523 | 2c0262af | bellard | } |
524 | 2c0262af | bellard | FORCE_RET(); |
525 | 2c0262af | bellard | } |
526 | 2c0262af | bellard | |
527 | 2c0262af | bellard | void OPPROTO op_boundl(void) |
528 | 2c0262af | bellard | { |
529 | 2c0262af | bellard | int low, high, v;
|
530 | 14ce26e7 | bellard | low = ldl(A0); |
531 | 14ce26e7 | bellard | high = ldl(A0 + 4);
|
532 | 2c0262af | bellard | v = T0; |
533 | 2c0262af | bellard | if (v < low || v > high) {
|
534 | 2c0262af | bellard | raise_exception(EXCP05_BOUND); |
535 | 2c0262af | bellard | } |
536 | 2c0262af | bellard | FORCE_RET(); |
537 | 2c0262af | bellard | } |
538 | 2c0262af | bellard | |
539 | 2c0262af | bellard | void OPPROTO op_cmpxchg8b(void) |
540 | 2c0262af | bellard | { |
541 | 2c0262af | bellard | helper_cmpxchg8b(); |
542 | 2c0262af | bellard | } |
543 | 2c0262af | bellard | |
544 | 88fe8a41 | ths | void OPPROTO op_single_step(void) |
545 | 88fe8a41 | ths | { |
546 | 88fe8a41 | ths | helper_single_step(); |
547 | 88fe8a41 | ths | } |
548 | 88fe8a41 | ths | |
549 | 2c0262af | bellard | /* multiple size ops */
|
550 | 2c0262af | bellard | |
551 | 2c0262af | bellard | #define ldul ldl
|
552 | 2c0262af | bellard | |
553 | 2c0262af | bellard | #define SHIFT 0 |
554 | 2c0262af | bellard | #include "ops_template.h" |
555 | 2c0262af | bellard | #undef SHIFT
|
556 | 2c0262af | bellard | |
557 | 2c0262af | bellard | #define SHIFT 1 |
558 | 2c0262af | bellard | #include "ops_template.h" |
559 | 2c0262af | bellard | #undef SHIFT
|
560 | 2c0262af | bellard | |
561 | 2c0262af | bellard | #define SHIFT 2 |
562 | 2c0262af | bellard | #include "ops_template.h" |
563 | 2c0262af | bellard | #undef SHIFT
|
564 | 2c0262af | bellard | |
565 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
566 | 14ce26e7 | bellard | |
567 | 14ce26e7 | bellard | #define SHIFT 3 |
568 | 14ce26e7 | bellard | #include "ops_template.h" |
569 | 14ce26e7 | bellard | #undef SHIFT
|
570 | 14ce26e7 | bellard | |
571 | 14ce26e7 | bellard | #endif
|
572 | 14ce26e7 | bellard | |
573 | 2c0262af | bellard | /* sign extend */
|
574 | 2c0262af | bellard | |
575 | 2c0262af | bellard | void OPPROTO op_movsbl_T0_T0(void) |
576 | 2c0262af | bellard | { |
577 | 2c0262af | bellard | T0 = (int8_t)T0; |
578 | 2c0262af | bellard | } |
579 | 2c0262af | bellard | |
580 | 2c0262af | bellard | void OPPROTO op_movzbl_T0_T0(void) |
581 | 2c0262af | bellard | { |
582 | 2c0262af | bellard | T0 = (uint8_t)T0; |
583 | 2c0262af | bellard | } |
584 | 2c0262af | bellard | |
585 | 2c0262af | bellard | void OPPROTO op_movswl_T0_T0(void) |
586 | 2c0262af | bellard | { |
587 | 2c0262af | bellard | T0 = (int16_t)T0; |
588 | 2c0262af | bellard | } |
589 | 2c0262af | bellard | |
590 | 2c0262af | bellard | void OPPROTO op_movzwl_T0_T0(void) |
591 | 2c0262af | bellard | { |
592 | 2c0262af | bellard | T0 = (uint16_t)T0; |
593 | 2c0262af | bellard | } |
594 | 2c0262af | bellard | |
595 | 2c0262af | bellard | void OPPROTO op_movswl_EAX_AX(void) |
596 | 2c0262af | bellard | { |
597 | 0499e4a0 | bellard | EAX = (uint32_t)((int16_t)EAX); |
598 | 2c0262af | bellard | } |
599 | 2c0262af | bellard | |
600 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
601 | 664e0f19 | bellard | void OPPROTO op_movslq_T0_T0(void) |
602 | 664e0f19 | bellard | { |
603 | 664e0f19 | bellard | T0 = (int32_t)T0; |
604 | 664e0f19 | bellard | } |
605 | 664e0f19 | bellard | |
606 | 14ce26e7 | bellard | void OPPROTO op_movslq_RAX_EAX(void) |
607 | 14ce26e7 | bellard | { |
608 | 14ce26e7 | bellard | EAX = (int32_t)EAX; |
609 | 14ce26e7 | bellard | } |
610 | 14ce26e7 | bellard | #endif
|
611 | 14ce26e7 | bellard | |
612 | 2c0262af | bellard | void OPPROTO op_movsbw_AX_AL(void) |
613 | 2c0262af | bellard | { |
614 | 14ce26e7 | bellard | EAX = (EAX & ~0xffff) | ((int8_t)EAX & 0xffff); |
615 | 2c0262af | bellard | } |
616 | 2c0262af | bellard | |
617 | 2c0262af | bellard | void OPPROTO op_movslq_EDX_EAX(void) |
618 | 2c0262af | bellard | { |
619 | 0499e4a0 | bellard | EDX = (uint32_t)((int32_t)EAX >> 31);
|
620 | 2c0262af | bellard | } |
621 | 2c0262af | bellard | |
622 | 2c0262af | bellard | void OPPROTO op_movswl_DX_AX(void) |
623 | 2c0262af | bellard | { |
624 | 14ce26e7 | bellard | EDX = (EDX & ~0xffff) | (((int16_t)EAX >> 15) & 0xffff); |
625 | 14ce26e7 | bellard | } |
626 | 14ce26e7 | bellard | |
627 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
628 | 14ce26e7 | bellard | void OPPROTO op_movsqo_RDX_RAX(void) |
629 | 14ce26e7 | bellard | { |
630 | 14ce26e7 | bellard | EDX = (int64_t)EAX >> 63;
|
631 | 2c0262af | bellard | } |
632 | 14ce26e7 | bellard | #endif
|
633 | 2c0262af | bellard | |
634 | 2c0262af | bellard | /* string ops helpers */
|
635 | 2c0262af | bellard | |
636 | 2c0262af | bellard | void OPPROTO op_addl_ESI_T0(void) |
637 | 2c0262af | bellard | { |
638 | 14ce26e7 | bellard | ESI = (uint32_t)(ESI + T0); |
639 | 2c0262af | bellard | } |
640 | 2c0262af | bellard | |
641 | 2c0262af | bellard | void OPPROTO op_addw_ESI_T0(void) |
642 | 2c0262af | bellard | { |
643 | 2c0262af | bellard | ESI = (ESI & ~0xffff) | ((ESI + T0) & 0xffff); |
644 | 2c0262af | bellard | } |
645 | 2c0262af | bellard | |
646 | 2c0262af | bellard | void OPPROTO op_addl_EDI_T0(void) |
647 | 2c0262af | bellard | { |
648 | 14ce26e7 | bellard | EDI = (uint32_t)(EDI + T0); |
649 | 2c0262af | bellard | } |
650 | 2c0262af | bellard | |
651 | 2c0262af | bellard | void OPPROTO op_addw_EDI_T0(void) |
652 | 2c0262af | bellard | { |
653 | 2c0262af | bellard | EDI = (EDI & ~0xffff) | ((EDI + T0) & 0xffff); |
654 | 2c0262af | bellard | } |
655 | 2c0262af | bellard | |
656 | 2c0262af | bellard | void OPPROTO op_decl_ECX(void) |
657 | 2c0262af | bellard | { |
658 | 14ce26e7 | bellard | ECX = (uint32_t)(ECX - 1);
|
659 | 2c0262af | bellard | } |
660 | 2c0262af | bellard | |
661 | 2c0262af | bellard | void OPPROTO op_decw_ECX(void) |
662 | 2c0262af | bellard | { |
663 | 2c0262af | bellard | ECX = (ECX & ~0xffff) | ((ECX - 1) & 0xffff); |
664 | 2c0262af | bellard | } |
665 | 2c0262af | bellard | |
666 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
667 | 14ce26e7 | bellard | void OPPROTO op_addq_ESI_T0(void) |
668 | 14ce26e7 | bellard | { |
669 | 14ce26e7 | bellard | ESI = (ESI + T0); |
670 | 14ce26e7 | bellard | } |
671 | 14ce26e7 | bellard | |
672 | 14ce26e7 | bellard | void OPPROTO op_addq_EDI_T0(void) |
673 | 14ce26e7 | bellard | { |
674 | 14ce26e7 | bellard | EDI = (EDI + T0); |
675 | 14ce26e7 | bellard | } |
676 | 14ce26e7 | bellard | |
677 | 14ce26e7 | bellard | void OPPROTO op_decq_ECX(void) |
678 | 14ce26e7 | bellard | { |
679 | 14ce26e7 | bellard | ECX--; |
680 | 14ce26e7 | bellard | } |
681 | 14ce26e7 | bellard | #endif
|
682 | 14ce26e7 | bellard | |
683 | 2c0262af | bellard | void OPPROTO op_rdtsc(void) |
684 | 2c0262af | bellard | { |
685 | 2c0262af | bellard | helper_rdtsc(); |
686 | 2c0262af | bellard | } |
687 | 2c0262af | bellard | |
688 | df01e0fc | balrog | void OPPROTO op_rdpmc(void) |
689 | df01e0fc | balrog | { |
690 | df01e0fc | balrog | helper_rdpmc(); |
691 | df01e0fc | balrog | } |
692 | df01e0fc | balrog | |
693 | 2c0262af | bellard | void OPPROTO op_cpuid(void) |
694 | 2c0262af | bellard | { |
695 | 2c0262af | bellard | helper_cpuid(); |
696 | 2c0262af | bellard | } |
697 | 2c0262af | bellard | |
698 | 61a8c4ec | bellard | void OPPROTO op_enter_level(void) |
699 | 61a8c4ec | bellard | { |
700 | 61a8c4ec | bellard | helper_enter_level(PARAM1, PARAM2); |
701 | 61a8c4ec | bellard | } |
702 | 61a8c4ec | bellard | |
703 | 8f091a59 | bellard | #ifdef TARGET_X86_64
|
704 | 8f091a59 | bellard | void OPPROTO op_enter64_level(void) |
705 | 8f091a59 | bellard | { |
706 | 8f091a59 | bellard | helper_enter64_level(PARAM1, PARAM2); |
707 | 8f091a59 | bellard | } |
708 | 8f091a59 | bellard | #endif
|
709 | 8f091a59 | bellard | |
710 | 023fe10d | bellard | void OPPROTO op_sysenter(void) |
711 | 023fe10d | bellard | { |
712 | 023fe10d | bellard | helper_sysenter(); |
713 | 023fe10d | bellard | } |
714 | 023fe10d | bellard | |
715 | 023fe10d | bellard | void OPPROTO op_sysexit(void) |
716 | 023fe10d | bellard | { |
717 | 023fe10d | bellard | helper_sysexit(); |
718 | 023fe10d | bellard | } |
719 | 023fe10d | bellard | |
720 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
721 | 14ce26e7 | bellard | void OPPROTO op_syscall(void) |
722 | 14ce26e7 | bellard | { |
723 | 06c2f506 | bellard | helper_syscall(PARAM1); |
724 | 14ce26e7 | bellard | } |
725 | 14ce26e7 | bellard | |
726 | 14ce26e7 | bellard | void OPPROTO op_sysret(void) |
727 | 14ce26e7 | bellard | { |
728 | 14ce26e7 | bellard | helper_sysret(PARAM1); |
729 | 14ce26e7 | bellard | } |
730 | 14ce26e7 | bellard | #endif
|
731 | 14ce26e7 | bellard | |
732 | 2c0262af | bellard | void OPPROTO op_rdmsr(void) |
733 | 2c0262af | bellard | { |
734 | 2c0262af | bellard | helper_rdmsr(); |
735 | 2c0262af | bellard | } |
736 | 2c0262af | bellard | |
737 | 2c0262af | bellard | void OPPROTO op_wrmsr(void) |
738 | 2c0262af | bellard | { |
739 | 2c0262af | bellard | helper_wrmsr(); |
740 | 2c0262af | bellard | } |
741 | 2c0262af | bellard | |
742 | 2c0262af | bellard | /* bcd */
|
743 | 2c0262af | bellard | |
744 | 2c0262af | bellard | /* XXX: exception */
|
745 | 2c0262af | bellard | void OPPROTO op_aam(void) |
746 | 2c0262af | bellard | { |
747 | 2c0262af | bellard | int base = PARAM1;
|
748 | 2c0262af | bellard | int al, ah;
|
749 | 2c0262af | bellard | al = EAX & 0xff;
|
750 | 2c0262af | bellard | ah = al / base; |
751 | 2c0262af | bellard | al = al % base; |
752 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
753 | 2c0262af | bellard | CC_DST = al; |
754 | 2c0262af | bellard | } |
755 | 2c0262af | bellard | |
756 | 2c0262af | bellard | void OPPROTO op_aad(void) |
757 | 2c0262af | bellard | { |
758 | 2c0262af | bellard | int base = PARAM1;
|
759 | 2c0262af | bellard | int al, ah;
|
760 | 2c0262af | bellard | al = EAX & 0xff;
|
761 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
762 | 2c0262af | bellard | al = ((ah * base) + al) & 0xff;
|
763 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al;
|
764 | 2c0262af | bellard | CC_DST = al; |
765 | 2c0262af | bellard | } |
766 | 2c0262af | bellard | |
767 | 2c0262af | bellard | void OPPROTO op_aaa(void) |
768 | 2c0262af | bellard | { |
769 | 2c0262af | bellard | int icarry;
|
770 | 2c0262af | bellard | int al, ah, af;
|
771 | 2c0262af | bellard | int eflags;
|
772 | 2c0262af | bellard | |
773 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
774 | 2c0262af | bellard | af = eflags & CC_A; |
775 | 2c0262af | bellard | al = EAX & 0xff;
|
776 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
777 | 2c0262af | bellard | |
778 | 2c0262af | bellard | icarry = (al > 0xf9);
|
779 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
780 | 2c0262af | bellard | al = (al + 6) & 0x0f; |
781 | 2c0262af | bellard | ah = (ah + 1 + icarry) & 0xff; |
782 | 2c0262af | bellard | eflags |= CC_C | CC_A; |
783 | 2c0262af | bellard | } else {
|
784 | 2c0262af | bellard | eflags &= ~(CC_C | CC_A); |
785 | 2c0262af | bellard | al &= 0x0f;
|
786 | 2c0262af | bellard | } |
787 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
788 | 2c0262af | bellard | CC_SRC = eflags; |
789 | 647c5930 | pbrook | FORCE_RET(); |
790 | 2c0262af | bellard | } |
791 | 2c0262af | bellard | |
792 | 2c0262af | bellard | void OPPROTO op_aas(void) |
793 | 2c0262af | bellard | { |
794 | 2c0262af | bellard | int icarry;
|
795 | 2c0262af | bellard | int al, ah, af;
|
796 | 2c0262af | bellard | int eflags;
|
797 | 2c0262af | bellard | |
798 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
799 | 2c0262af | bellard | af = eflags & CC_A; |
800 | 2c0262af | bellard | al = EAX & 0xff;
|
801 | 2c0262af | bellard | ah = (EAX >> 8) & 0xff; |
802 | 2c0262af | bellard | |
803 | 2c0262af | bellard | icarry = (al < 6);
|
804 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
805 | 2c0262af | bellard | al = (al - 6) & 0x0f; |
806 | 2c0262af | bellard | ah = (ah - 1 - icarry) & 0xff; |
807 | 2c0262af | bellard | eflags |= CC_C | CC_A; |
808 | 2c0262af | bellard | } else {
|
809 | 2c0262af | bellard | eflags &= ~(CC_C | CC_A); |
810 | 2c0262af | bellard | al &= 0x0f;
|
811 | 2c0262af | bellard | } |
812 | 2c0262af | bellard | EAX = (EAX & ~0xffff) | al | (ah << 8); |
813 | 2c0262af | bellard | CC_SRC = eflags; |
814 | 647c5930 | pbrook | FORCE_RET(); |
815 | 2c0262af | bellard | } |
816 | 2c0262af | bellard | |
817 | 2c0262af | bellard | void OPPROTO op_daa(void) |
818 | 2c0262af | bellard | { |
819 | 2c0262af | bellard | int al, af, cf;
|
820 | 2c0262af | bellard | int eflags;
|
821 | 2c0262af | bellard | |
822 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
823 | 2c0262af | bellard | cf = eflags & CC_C; |
824 | 2c0262af | bellard | af = eflags & CC_A; |
825 | 2c0262af | bellard | al = EAX & 0xff;
|
826 | 2c0262af | bellard | |
827 | 2c0262af | bellard | eflags = 0;
|
828 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
829 | 2c0262af | bellard | al = (al + 6) & 0xff; |
830 | 2c0262af | bellard | eflags |= CC_A; |
831 | 2c0262af | bellard | } |
832 | 2c0262af | bellard | if ((al > 0x9f) || cf) { |
833 | 2c0262af | bellard | al = (al + 0x60) & 0xff; |
834 | 2c0262af | bellard | eflags |= CC_C; |
835 | 2c0262af | bellard | } |
836 | 2c0262af | bellard | EAX = (EAX & ~0xff) | al;
|
837 | 2c0262af | bellard | /* well, speed is not an issue here, so we compute the flags by hand */
|
838 | 2c0262af | bellard | eflags |= (al == 0) << 6; /* zf */ |
839 | 2c0262af | bellard | eflags |= parity_table[al]; /* pf */
|
840 | 2c0262af | bellard | eflags |= (al & 0x80); /* sf */ |
841 | 2c0262af | bellard | CC_SRC = eflags; |
842 | 647c5930 | pbrook | FORCE_RET(); |
843 | 2c0262af | bellard | } |
844 | 2c0262af | bellard | |
845 | 2c0262af | bellard | void OPPROTO op_das(void) |
846 | 2c0262af | bellard | { |
847 | 2c0262af | bellard | int al, al1, af, cf;
|
848 | 2c0262af | bellard | int eflags;
|
849 | 2c0262af | bellard | |
850 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
851 | 2c0262af | bellard | cf = eflags & CC_C; |
852 | 2c0262af | bellard | af = eflags & CC_A; |
853 | 2c0262af | bellard | al = EAX & 0xff;
|
854 | 2c0262af | bellard | |
855 | 2c0262af | bellard | eflags = 0;
|
856 | 2c0262af | bellard | al1 = al; |
857 | 2c0262af | bellard | if (((al & 0x0f) > 9 ) || af) { |
858 | 2c0262af | bellard | eflags |= CC_A; |
859 | 2c0262af | bellard | if (al < 6 || cf) |
860 | 2c0262af | bellard | eflags |= CC_C; |
861 | 2c0262af | bellard | al = (al - 6) & 0xff; |
862 | 2c0262af | bellard | } |
863 | 2c0262af | bellard | if ((al1 > 0x99) || cf) { |
864 | 2c0262af | bellard | al = (al - 0x60) & 0xff; |
865 | 2c0262af | bellard | eflags |= CC_C; |
866 | 2c0262af | bellard | } |
867 | 2c0262af | bellard | EAX = (EAX & ~0xff) | al;
|
868 | 2c0262af | bellard | /* well, speed is not an issue here, so we compute the flags by hand */
|
869 | 2c0262af | bellard | eflags |= (al == 0) << 6; /* zf */ |
870 | 2c0262af | bellard | eflags |= parity_table[al]; /* pf */
|
871 | 2c0262af | bellard | eflags |= (al & 0x80); /* sf */ |
872 | 2c0262af | bellard | CC_SRC = eflags; |
873 | 647c5930 | pbrook | FORCE_RET(); |
874 | 2c0262af | bellard | } |
875 | 2c0262af | bellard | |
876 | 2c0262af | bellard | /* segment handling */
|
877 | 2c0262af | bellard | |
878 | 2c0262af | bellard | /* never use it with R_CS */
|
879 | 2c0262af | bellard | void OPPROTO op_movl_seg_T0(void) |
880 | 2c0262af | bellard | { |
881 | 3415a4dd | bellard | load_seg(PARAM1, T0); |
882 | 2c0262af | bellard | } |
883 | 2c0262af | bellard | |
884 | 2c0262af | bellard | /* faster VM86 version */
|
885 | 2c0262af | bellard | void OPPROTO op_movl_seg_T0_vm(void) |
886 | 2c0262af | bellard | { |
887 | 2c0262af | bellard | int selector;
|
888 | 2c0262af | bellard | SegmentCache *sc; |
889 | 3b46e624 | ths | |
890 | 2c0262af | bellard | selector = T0 & 0xffff;
|
891 | 2c0262af | bellard | /* env->segs[] access */
|
892 | 2c0262af | bellard | sc = (SegmentCache *)((char *)env + PARAM1);
|
893 | 2c0262af | bellard | sc->selector = selector; |
894 | 14ce26e7 | bellard | sc->base = (selector << 4);
|
895 | 2c0262af | bellard | } |
896 | 2c0262af | bellard | |
897 | 2c0262af | bellard | void OPPROTO op_movl_T0_seg(void) |
898 | 2c0262af | bellard | { |
899 | 2c0262af | bellard | T0 = env->segs[PARAM1].selector; |
900 | 2c0262af | bellard | } |
901 | 2c0262af | bellard | |
902 | 2c0262af | bellard | void OPPROTO op_lsl(void) |
903 | 2c0262af | bellard | { |
904 | 2c0262af | bellard | helper_lsl(); |
905 | 2c0262af | bellard | } |
906 | 2c0262af | bellard | |
907 | 2c0262af | bellard | void OPPROTO op_lar(void) |
908 | 2c0262af | bellard | { |
909 | 2c0262af | bellard | helper_lar(); |
910 | 2c0262af | bellard | } |
911 | 2c0262af | bellard | |
912 | 3ab493de | bellard | void OPPROTO op_verr(void) |
913 | 3ab493de | bellard | { |
914 | 3ab493de | bellard | helper_verr(); |
915 | 3ab493de | bellard | } |
916 | 3ab493de | bellard | |
917 | 3ab493de | bellard | void OPPROTO op_verw(void) |
918 | 3ab493de | bellard | { |
919 | 3ab493de | bellard | helper_verw(); |
920 | 3ab493de | bellard | } |
921 | 3ab493de | bellard | |
922 | 3ab493de | bellard | void OPPROTO op_arpl(void) |
923 | 3ab493de | bellard | { |
924 | 3ab493de | bellard | if ((T0 & 3) < (T1 & 3)) { |
925 | 3ab493de | bellard | /* XXX: emulate bug or 0xff3f0000 oring as in bochs ? */
|
926 | 3ab493de | bellard | T0 = (T0 & ~3) | (T1 & 3); |
927 | 3ab493de | bellard | T1 = CC_Z; |
928 | 3ab493de | bellard | } else {
|
929 | 3ab493de | bellard | T1 = 0;
|
930 | 3ab493de | bellard | } |
931 | 3ab493de | bellard | FORCE_RET(); |
932 | 3ab493de | bellard | } |
933 | 3b46e624 | ths | |
934 | 3ab493de | bellard | void OPPROTO op_arpl_update(void) |
935 | 3ab493de | bellard | { |
936 | 3ab493de | bellard | int eflags;
|
937 | 3ab493de | bellard | eflags = cc_table[CC_OP].compute_all(); |
938 | 3ab493de | bellard | CC_SRC = (eflags & ~CC_Z) | T1; |
939 | 3ab493de | bellard | } |
940 | 3b46e624 | ths | |
941 | 2c0262af | bellard | /* T0: segment, T1:eip */
|
942 | 2c0262af | bellard | void OPPROTO op_ljmp_protected_T0_T1(void) |
943 | 2c0262af | bellard | { |
944 | 08cea4ee | bellard | helper_ljmp_protected_T0_T1(PARAM1); |
945 | 2c0262af | bellard | } |
946 | 2c0262af | bellard | |
947 | 2c0262af | bellard | void OPPROTO op_lcall_real_T0_T1(void) |
948 | 2c0262af | bellard | { |
949 | 2c0262af | bellard | helper_lcall_real_T0_T1(PARAM1, PARAM2); |
950 | 2c0262af | bellard | } |
951 | 2c0262af | bellard | |
952 | 2c0262af | bellard | void OPPROTO op_lcall_protected_T0_T1(void) |
953 | 2c0262af | bellard | { |
954 | 2c0262af | bellard | helper_lcall_protected_T0_T1(PARAM1, PARAM2); |
955 | 2c0262af | bellard | } |
956 | 2c0262af | bellard | |
957 | 2c0262af | bellard | void OPPROTO op_iret_real(void) |
958 | 2c0262af | bellard | { |
959 | 2c0262af | bellard | helper_iret_real(PARAM1); |
960 | 2c0262af | bellard | } |
961 | 2c0262af | bellard | |
962 | 2c0262af | bellard | void OPPROTO op_iret_protected(void) |
963 | 2c0262af | bellard | { |
964 | 08cea4ee | bellard | helper_iret_protected(PARAM1, PARAM2); |
965 | 2c0262af | bellard | } |
966 | 2c0262af | bellard | |
967 | 2c0262af | bellard | void OPPROTO op_lret_protected(void) |
968 | 2c0262af | bellard | { |
969 | 2c0262af | bellard | helper_lret_protected(PARAM1, PARAM2); |
970 | 2c0262af | bellard | } |
971 | 2c0262af | bellard | |
972 | 2c0262af | bellard | void OPPROTO op_lldt_T0(void) |
973 | 2c0262af | bellard | { |
974 | 2c0262af | bellard | helper_lldt_T0(); |
975 | 2c0262af | bellard | } |
976 | 2c0262af | bellard | |
977 | 2c0262af | bellard | void OPPROTO op_ltr_T0(void) |
978 | 2c0262af | bellard | { |
979 | 2c0262af | bellard | helper_ltr_T0(); |
980 | 2c0262af | bellard | } |
981 | 2c0262af | bellard | |
982 | 0573fbfc | ths | /* CR registers access. */
|
983 | 2c0262af | bellard | void OPPROTO op_movl_crN_T0(void) |
984 | 2c0262af | bellard | { |
985 | 2c0262af | bellard | helper_movl_crN_T0(PARAM1); |
986 | 2c0262af | bellard | } |
987 | 2c0262af | bellard | |
988 | 0573fbfc | ths | /* These pseudo-opcodes check for SVM intercepts. */
|
989 | 0573fbfc | ths | void OPPROTO op_svm_check_intercept(void) |
990 | 0573fbfc | ths | { |
991 | 0573fbfc | ths | A0 = PARAM1 & PARAM2; |
992 | 0573fbfc | ths | svm_check_intercept(PARAMQ1); |
993 | 0573fbfc | ths | } |
994 | 0573fbfc | ths | |
995 | 0573fbfc | ths | void OPPROTO op_svm_check_intercept_param(void) |
996 | 0573fbfc | ths | { |
997 | 0573fbfc | ths | A0 = PARAM1 & PARAM2; |
998 | 0573fbfc | ths | svm_check_intercept_param(PARAMQ1, T1); |
999 | 0573fbfc | ths | } |
1000 | 0573fbfc | ths | |
1001 | 0573fbfc | ths | void OPPROTO op_svm_vmexit(void) |
1002 | 0573fbfc | ths | { |
1003 | 0573fbfc | ths | A0 = PARAM1 & PARAM2; |
1004 | 0573fbfc | ths | vmexit(PARAMQ1, T1); |
1005 | 0573fbfc | ths | } |
1006 | 0573fbfc | ths | |
1007 | 0573fbfc | ths | void OPPROTO op_geneflags(void) |
1008 | 0573fbfc | ths | { |
1009 | 0573fbfc | ths | CC_SRC = cc_table[CC_OP].compute_all(); |
1010 | 0573fbfc | ths | } |
1011 | 0573fbfc | ths | |
1012 | 0573fbfc | ths | /* This pseudo-opcode checks for IO intercepts. */
|
1013 | 0573fbfc | ths | #if !defined(CONFIG_USER_ONLY)
|
1014 | 0573fbfc | ths | void OPPROTO op_svm_check_intercept_io(void) |
1015 | 0573fbfc | ths | { |
1016 | 0573fbfc | ths | A0 = PARAM1 & PARAM2; |
1017 | 0573fbfc | ths | /* PARAMQ1 = TYPE (0 = OUT, 1 = IN; 4 = STRING; 8 = REP)
|
1018 | 0573fbfc | ths | T0 = PORT
|
1019 | 0573fbfc | ths | T1 = next eip */
|
1020 | 0573fbfc | ths | stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), T1);
|
1021 | 0573fbfc | ths | /* ASIZE does not appear on real hw */
|
1022 | 0573fbfc | ths | svm_check_intercept_param(SVM_EXIT_IOIO, |
1023 | 0573fbfc | ths | (PARAMQ1 & ~SVM_IOIO_ASIZE_MASK) | |
1024 | 0573fbfc | ths | ((T0 & 0xffff) << 16)); |
1025 | 0573fbfc | ths | } |
1026 | 0573fbfc | ths | #endif
|
1027 | 0573fbfc | ths | |
1028 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
1029 | 39c61f49 | bellard | void OPPROTO op_movtl_T0_cr8(void) |
1030 | 39c61f49 | bellard | { |
1031 | 39c61f49 | bellard | T0 = cpu_get_apic_tpr(env); |
1032 | 39c61f49 | bellard | } |
1033 | 82e41634 | bellard | #endif
|
1034 | 39c61f49 | bellard | |
1035 | 2c0262af | bellard | /* DR registers access */
|
1036 | 2c0262af | bellard | void OPPROTO op_movl_drN_T0(void) |
1037 | 2c0262af | bellard | { |
1038 | 2c0262af | bellard | helper_movl_drN_T0(PARAM1); |
1039 | 2c0262af | bellard | } |
1040 | 2c0262af | bellard | |
1041 | 2c0262af | bellard | void OPPROTO op_lmsw_T0(void) |
1042 | 2c0262af | bellard | { |
1043 | 710c15a2 | bellard | /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
|
1044 | 710c15a2 | bellard | if already set to one. */
|
1045 | 710c15a2 | bellard | T0 = (env->cr[0] & ~0xe) | (T0 & 0xf); |
1046 | 2c0262af | bellard | helper_movl_crN_T0(0);
|
1047 | 2c0262af | bellard | } |
1048 | 2c0262af | bellard | |
1049 | 2c0262af | bellard | void OPPROTO op_invlpg_A0(void) |
1050 | 2c0262af | bellard | { |
1051 | 2c0262af | bellard | helper_invlpg(A0); |
1052 | 2c0262af | bellard | } |
1053 | 2c0262af | bellard | |
1054 | 2c0262af | bellard | void OPPROTO op_movl_T0_env(void) |
1055 | 2c0262af | bellard | { |
1056 | 2c0262af | bellard | T0 = *(uint32_t *)((char *)env + PARAM1);
|
1057 | 2c0262af | bellard | } |
1058 | 2c0262af | bellard | |
1059 | 2c0262af | bellard | void OPPROTO op_movl_env_T0(void) |
1060 | 2c0262af | bellard | { |
1061 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T0;
|
1062 | 2c0262af | bellard | } |
1063 | 2c0262af | bellard | |
1064 | 2c0262af | bellard | void OPPROTO op_movl_env_T1(void) |
1065 | 2c0262af | bellard | { |
1066 | 2c0262af | bellard | *(uint32_t *)((char *)env + PARAM1) = T1;
|
1067 | 2c0262af | bellard | } |
1068 | 2c0262af | bellard | |
1069 | 14ce26e7 | bellard | void OPPROTO op_movtl_T0_env(void) |
1070 | 14ce26e7 | bellard | { |
1071 | 14ce26e7 | bellard | T0 = *(target_ulong *)((char *)env + PARAM1);
|
1072 | 14ce26e7 | bellard | } |
1073 | 14ce26e7 | bellard | |
1074 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T0(void) |
1075 | 14ce26e7 | bellard | { |
1076 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T0;
|
1077 | 14ce26e7 | bellard | } |
1078 | 14ce26e7 | bellard | |
1079 | 14ce26e7 | bellard | void OPPROTO op_movtl_T1_env(void) |
1080 | 14ce26e7 | bellard | { |
1081 | 14ce26e7 | bellard | T1 = *(target_ulong *)((char *)env + PARAM1);
|
1082 | 14ce26e7 | bellard | } |
1083 | 14ce26e7 | bellard | |
1084 | 14ce26e7 | bellard | void OPPROTO op_movtl_env_T1(void) |
1085 | 14ce26e7 | bellard | { |
1086 | 14ce26e7 | bellard | *(target_ulong *)((char *)env + PARAM1) = T1;
|
1087 | 14ce26e7 | bellard | } |
1088 | 14ce26e7 | bellard | |
1089 | 2c0262af | bellard | void OPPROTO op_clts(void) |
1090 | 2c0262af | bellard | { |
1091 | 2c0262af | bellard | env->cr[0] &= ~CR0_TS_MASK;
|
1092 | 7eee2a50 | bellard | env->hflags &= ~HF_TS_MASK; |
1093 | 2c0262af | bellard | } |
1094 | 2c0262af | bellard | |
1095 | 2c0262af | bellard | /* flags handling */
|
1096 | 2c0262af | bellard | |
1097 | 14ce26e7 | bellard | void OPPROTO op_jmp_label(void) |
1098 | 14ce26e7 | bellard | { |
1099 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1100 | 2c0262af | bellard | } |
1101 | 2c0262af | bellard | |
1102 | 14ce26e7 | bellard | void OPPROTO op_jnz_T0_label(void) |
1103 | 2c0262af | bellard | { |
1104 | 2c0262af | bellard | if (T0)
|
1105 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1106 | 39c61f49 | bellard | FORCE_RET(); |
1107 | 14ce26e7 | bellard | } |
1108 | 14ce26e7 | bellard | |
1109 | 14ce26e7 | bellard | void OPPROTO op_jz_T0_label(void) |
1110 | 14ce26e7 | bellard | { |
1111 | 14ce26e7 | bellard | if (!T0)
|
1112 | 14ce26e7 | bellard | GOTO_LABEL_PARAM(1);
|
1113 | 39c61f49 | bellard | FORCE_RET(); |
1114 | 2c0262af | bellard | } |
1115 | 2c0262af | bellard | |
1116 | 2c0262af | bellard | /* slow set cases (compute x86 flags) */
|
1117 | 2c0262af | bellard | void OPPROTO op_seto_T0_cc(void) |
1118 | 2c0262af | bellard | { |
1119 | 2c0262af | bellard | int eflags;
|
1120 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1121 | 2c0262af | bellard | T0 = (eflags >> 11) & 1; |
1122 | 2c0262af | bellard | } |
1123 | 2c0262af | bellard | |
1124 | 2c0262af | bellard | void OPPROTO op_setb_T0_cc(void) |
1125 | 2c0262af | bellard | { |
1126 | 2c0262af | bellard | T0 = cc_table[CC_OP].compute_c(); |
1127 | 2c0262af | bellard | } |
1128 | 2c0262af | bellard | |
1129 | 2c0262af | bellard | void OPPROTO op_setz_T0_cc(void) |
1130 | 2c0262af | bellard | { |
1131 | 2c0262af | bellard | int eflags;
|
1132 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1133 | 2c0262af | bellard | T0 = (eflags >> 6) & 1; |
1134 | 2c0262af | bellard | } |
1135 | 2c0262af | bellard | |
1136 | 2c0262af | bellard | void OPPROTO op_setbe_T0_cc(void) |
1137 | 2c0262af | bellard | { |
1138 | 2c0262af | bellard | int eflags;
|
1139 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1140 | 2c0262af | bellard | T0 = (eflags & (CC_Z | CC_C)) != 0;
|
1141 | 2c0262af | bellard | } |
1142 | 2c0262af | bellard | |
1143 | 2c0262af | bellard | void OPPROTO op_sets_T0_cc(void) |
1144 | 2c0262af | bellard | { |
1145 | 2c0262af | bellard | int eflags;
|
1146 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1147 | 2c0262af | bellard | T0 = (eflags >> 7) & 1; |
1148 | 2c0262af | bellard | } |
1149 | 2c0262af | bellard | |
1150 | 2c0262af | bellard | void OPPROTO op_setp_T0_cc(void) |
1151 | 2c0262af | bellard | { |
1152 | 2c0262af | bellard | int eflags;
|
1153 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1154 | 2c0262af | bellard | T0 = (eflags >> 2) & 1; |
1155 | 2c0262af | bellard | } |
1156 | 2c0262af | bellard | |
1157 | 2c0262af | bellard | void OPPROTO op_setl_T0_cc(void) |
1158 | 2c0262af | bellard | { |
1159 | 2c0262af | bellard | int eflags;
|
1160 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1161 | 2c0262af | bellard | T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1; |
1162 | 2c0262af | bellard | } |
1163 | 2c0262af | bellard | |
1164 | 2c0262af | bellard | void OPPROTO op_setle_T0_cc(void) |
1165 | 2c0262af | bellard | { |
1166 | 2c0262af | bellard | int eflags;
|
1167 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1168 | 2c0262af | bellard | T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0; |
1169 | 2c0262af | bellard | } |
1170 | 2c0262af | bellard | |
1171 | 2c0262af | bellard | void OPPROTO op_xor_T0_1(void) |
1172 | 2c0262af | bellard | { |
1173 | 2c0262af | bellard | T0 ^= 1;
|
1174 | 2c0262af | bellard | } |
1175 | 2c0262af | bellard | |
1176 | 0b9dc5e4 | bellard | void OPPROTO op_mov_T0_cc(void) |
1177 | 0b9dc5e4 | bellard | { |
1178 | 0b9dc5e4 | bellard | T0 = cc_table[CC_OP].compute_all(); |
1179 | 0b9dc5e4 | bellard | } |
1180 | 0b9dc5e4 | bellard | |
1181 | 4136f33c | bellard | /* XXX: clear VIF/VIP in all ops ? */
|
1182 | 2c0262af | bellard | |
1183 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0(void) |
1184 | 2c0262af | bellard | { |
1185 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK)); |
1186 | 2c0262af | bellard | } |
1187 | 2c0262af | bellard | |
1188 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0(void) |
1189 | 2c0262af | bellard | { |
1190 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff);
|
1191 | 4136f33c | bellard | } |
1192 | 4136f33c | bellard | |
1193 | 4136f33c | bellard | void OPPROTO op_movl_eflags_T0_io(void) |
1194 | 4136f33c | bellard | { |
1195 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)); |
1196 | 4136f33c | bellard | } |
1197 | 4136f33c | bellard | |
1198 | 4136f33c | bellard | void OPPROTO op_movw_eflags_T0_io(void) |
1199 | 4136f33c | bellard | { |
1200 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff);
|
1201 | 2c0262af | bellard | } |
1202 | 2c0262af | bellard | |
1203 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_cpl0(void) |
1204 | 2c0262af | bellard | { |
1205 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)); |
1206 | 2c0262af | bellard | } |
1207 | 2c0262af | bellard | |
1208 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_cpl0(void) |
1209 | 2c0262af | bellard | { |
1210 | 4b7aba51 | bellard | load_eflags(T0, (TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff);
|
1211 | 2c0262af | bellard | } |
1212 | 2c0262af | bellard | |
1213 | 2c0262af | bellard | #if 0
|
1214 | 2c0262af | bellard | /* vm86plus version */
|
1215 | 2c0262af | bellard | void OPPROTO op_movw_eflags_T0_vm(void)
|
1216 | 2c0262af | bellard | {
|
1217 | 2c0262af | bellard | int eflags;
|
1218 | 2c0262af | bellard | eflags = T0;
|
1219 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
1220 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
|
1221 | 2c0262af | bellard | /* we also update some system flags as in user mode */
|
1222 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
|
1223 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK16);
|
1224 | 2c0262af | bellard | if (eflags & IF_MASK) {
|
1225 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
1226 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
1227 | 2c0262af | bellard | EIP = PARAM1;
|
1228 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
1229 | 2c0262af | bellard | }
|
1230 | 2c0262af | bellard | }
|
1231 | 2c0262af | bellard | FORCE_RET();
|
1232 | 2c0262af | bellard | }
|
1233 | 2c0262af | bellard | |
1234 | 2c0262af | bellard | void OPPROTO op_movl_eflags_T0_vm(void)
|
1235 | 2c0262af | bellard | {
|
1236 | 2c0262af | bellard | int eflags;
|
1237 | 2c0262af | bellard | eflags = T0;
|
1238 | 2c0262af | bellard | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
1239 | 2c0262af | bellard | DF = 1 - (2 * ((eflags >> 10) & 1));
|
1240 | 2c0262af | bellard | /* we also update some system flags as in user mode */
|
1241 | 2c0262af | bellard | env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
|
1242 | 2c0262af | bellard | (eflags & FL_UPDATE_MASK32);
|
1243 | 2c0262af | bellard | if (eflags & IF_MASK) {
|
1244 | 2c0262af | bellard | env->eflags |= VIF_MASK;
|
1245 | 2c0262af | bellard | if (env->eflags & VIP_MASK) {
|
1246 | 2c0262af | bellard | EIP = PARAM1;
|
1247 | 2c0262af | bellard | raise_exception(EXCP0D_GPF);
|
1248 | 2c0262af | bellard | }
|
1249 | 2c0262af | bellard | }
|
1250 | 2c0262af | bellard | FORCE_RET();
|
1251 | 2c0262af | bellard | }
|
1252 | 2c0262af | bellard | #endif
|
1253 | 2c0262af | bellard | |
1254 | 2c0262af | bellard | /* XXX: compute only O flag */
|
1255 | 2c0262af | bellard | void OPPROTO op_movb_eflags_T0(void) |
1256 | 2c0262af | bellard | { |
1257 | 2c0262af | bellard | int of;
|
1258 | 2c0262af | bellard | of = cc_table[CC_OP].compute_all() & CC_O; |
1259 | 2c0262af | bellard | CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of; |
1260 | 2c0262af | bellard | } |
1261 | 2c0262af | bellard | |
1262 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags(void) |
1263 | 2c0262af | bellard | { |
1264 | 2c0262af | bellard | int eflags;
|
1265 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1266 | 2c0262af | bellard | eflags |= (DF & DF_MASK); |
1267 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK); |
1268 | 2c0262af | bellard | T0 = eflags; |
1269 | 2c0262af | bellard | } |
1270 | 2c0262af | bellard | |
1271 | 2c0262af | bellard | /* vm86plus version */
|
1272 | 2c0262af | bellard | #if 0
|
1273 | 2c0262af | bellard | void OPPROTO op_movl_T0_eflags_vm(void)
|
1274 | 2c0262af | bellard | {
|
1275 | 2c0262af | bellard | int eflags;
|
1276 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all();
|
1277 | 2c0262af | bellard | eflags |= (DF & DF_MASK);
|
1278 | 2c0262af | bellard | eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
|
1279 | 2c0262af | bellard | if (env->eflags & VIF_MASK)
|
1280 | 2c0262af | bellard | eflags |= IF_MASK;
|
1281 | 2c0262af | bellard | T0 = eflags;
|
1282 | 2c0262af | bellard | }
|
1283 | 2c0262af | bellard | #endif
|
1284 | 2c0262af | bellard | |
1285 | 2c0262af | bellard | void OPPROTO op_cld(void) |
1286 | 2c0262af | bellard | { |
1287 | 2c0262af | bellard | DF = 1;
|
1288 | 2c0262af | bellard | } |
1289 | 2c0262af | bellard | |
1290 | 2c0262af | bellard | void OPPROTO op_std(void) |
1291 | 2c0262af | bellard | { |
1292 | 2c0262af | bellard | DF = -1;
|
1293 | 2c0262af | bellard | } |
1294 | 2c0262af | bellard | |
1295 | 2c0262af | bellard | void OPPROTO op_clc(void) |
1296 | 2c0262af | bellard | { |
1297 | 2c0262af | bellard | int eflags;
|
1298 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1299 | 2c0262af | bellard | eflags &= ~CC_C; |
1300 | 2c0262af | bellard | CC_SRC = eflags; |
1301 | 2c0262af | bellard | } |
1302 | 2c0262af | bellard | |
1303 | 2c0262af | bellard | void OPPROTO op_stc(void) |
1304 | 2c0262af | bellard | { |
1305 | 2c0262af | bellard | int eflags;
|
1306 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1307 | 2c0262af | bellard | eflags |= CC_C; |
1308 | 2c0262af | bellard | CC_SRC = eflags; |
1309 | 2c0262af | bellard | } |
1310 | 2c0262af | bellard | |
1311 | 2c0262af | bellard | void OPPROTO op_cmc(void) |
1312 | 2c0262af | bellard | { |
1313 | 2c0262af | bellard | int eflags;
|
1314 | 2c0262af | bellard | eflags = cc_table[CC_OP].compute_all(); |
1315 | 2c0262af | bellard | eflags ^= CC_C; |
1316 | 2c0262af | bellard | CC_SRC = eflags; |
1317 | 2c0262af | bellard | } |
1318 | 2c0262af | bellard | |
1319 | 2c0262af | bellard | void OPPROTO op_salc(void) |
1320 | 2c0262af | bellard | { |
1321 | 2c0262af | bellard | int cf;
|
1322 | 2c0262af | bellard | cf = cc_table[CC_OP].compute_c(); |
1323 | 2c0262af | bellard | EAX = (EAX & ~0xff) | ((-cf) & 0xff); |
1324 | 2c0262af | bellard | } |
1325 | 2c0262af | bellard | |
1326 | 2c0262af | bellard | static int compute_all_eflags(void) |
1327 | 2c0262af | bellard | { |
1328 | 2c0262af | bellard | return CC_SRC;
|
1329 | 2c0262af | bellard | } |
1330 | 2c0262af | bellard | |
1331 | 2c0262af | bellard | static int compute_c_eflags(void) |
1332 | 2c0262af | bellard | { |
1333 | 2c0262af | bellard | return CC_SRC & CC_C;
|
1334 | 2c0262af | bellard | } |
1335 | 2c0262af | bellard | |
1336 | 2c0262af | bellard | CCTable cc_table[CC_OP_NB] = { |
1337 | 2c0262af | bellard | [CC_OP_DYNAMIC] = { /* should never happen */ },
|
1338 | 2c0262af | bellard | |
1339 | 2c0262af | bellard | [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags }, |
1340 | 2c0262af | bellard | |
1341 | d36cd60e | bellard | [CC_OP_MULB] = { compute_all_mulb, compute_c_mull }, |
1342 | d36cd60e | bellard | [CC_OP_MULW] = { compute_all_mulw, compute_c_mull }, |
1343 | d36cd60e | bellard | [CC_OP_MULL] = { compute_all_mull, compute_c_mull }, |
1344 | 2c0262af | bellard | |
1345 | 2c0262af | bellard | [CC_OP_ADDB] = { compute_all_addb, compute_c_addb }, |
1346 | 2c0262af | bellard | [CC_OP_ADDW] = { compute_all_addw, compute_c_addw }, |
1347 | 2c0262af | bellard | [CC_OP_ADDL] = { compute_all_addl, compute_c_addl }, |
1348 | 2c0262af | bellard | |
1349 | 2c0262af | bellard | [CC_OP_ADCB] = { compute_all_adcb, compute_c_adcb }, |
1350 | 2c0262af | bellard | [CC_OP_ADCW] = { compute_all_adcw, compute_c_adcw }, |
1351 | 2c0262af | bellard | [CC_OP_ADCL] = { compute_all_adcl, compute_c_adcl }, |
1352 | 2c0262af | bellard | |
1353 | 2c0262af | bellard | [CC_OP_SUBB] = { compute_all_subb, compute_c_subb }, |
1354 | 2c0262af | bellard | [CC_OP_SUBW] = { compute_all_subw, compute_c_subw }, |
1355 | 2c0262af | bellard | [CC_OP_SUBL] = { compute_all_subl, compute_c_subl }, |
1356 | 3b46e624 | ths | |
1357 | 2c0262af | bellard | [CC_OP_SBBB] = { compute_all_sbbb, compute_c_sbbb }, |
1358 | 2c0262af | bellard | [CC_OP_SBBW] = { compute_all_sbbw, compute_c_sbbw }, |
1359 | 2c0262af | bellard | [CC_OP_SBBL] = { compute_all_sbbl, compute_c_sbbl }, |
1360 | 3b46e624 | ths | |
1361 | 2c0262af | bellard | [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb }, |
1362 | 2c0262af | bellard | [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw }, |
1363 | 2c0262af | bellard | [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl }, |
1364 | 3b46e624 | ths | |
1365 | 2c0262af | bellard | [CC_OP_INCB] = { compute_all_incb, compute_c_incl }, |
1366 | 2c0262af | bellard | [CC_OP_INCW] = { compute_all_incw, compute_c_incl }, |
1367 | 2c0262af | bellard | [CC_OP_INCL] = { compute_all_incl, compute_c_incl }, |
1368 | 3b46e624 | ths | |
1369 | 2c0262af | bellard | [CC_OP_DECB] = { compute_all_decb, compute_c_incl }, |
1370 | 2c0262af | bellard | [CC_OP_DECW] = { compute_all_decw, compute_c_incl }, |
1371 | 2c0262af | bellard | [CC_OP_DECL] = { compute_all_decl, compute_c_incl }, |
1372 | 3b46e624 | ths | |
1373 | 2c0262af | bellard | [CC_OP_SHLB] = { compute_all_shlb, compute_c_shlb }, |
1374 | 2c0262af | bellard | [CC_OP_SHLW] = { compute_all_shlw, compute_c_shlw }, |
1375 | 2c0262af | bellard | [CC_OP_SHLL] = { compute_all_shll, compute_c_shll }, |
1376 | 2c0262af | bellard | |
1377 | 2c0262af | bellard | [CC_OP_SARB] = { compute_all_sarb, compute_c_sarl }, |
1378 | 2c0262af | bellard | [CC_OP_SARW] = { compute_all_sarw, compute_c_sarl }, |
1379 | 2c0262af | bellard | [CC_OP_SARL] = { compute_all_sarl, compute_c_sarl }, |
1380 | 14ce26e7 | bellard | |
1381 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
1382 | 14ce26e7 | bellard | [CC_OP_MULQ] = { compute_all_mulq, compute_c_mull }, |
1383 | 14ce26e7 | bellard | |
1384 | 14ce26e7 | bellard | [CC_OP_ADDQ] = { compute_all_addq, compute_c_addq }, |
1385 | 14ce26e7 | bellard | |
1386 | 14ce26e7 | bellard | [CC_OP_ADCQ] = { compute_all_adcq, compute_c_adcq }, |
1387 | 14ce26e7 | bellard | |
1388 | 14ce26e7 | bellard | [CC_OP_SUBQ] = { compute_all_subq, compute_c_subq }, |
1389 | 3b46e624 | ths | |
1390 | 14ce26e7 | bellard | [CC_OP_SBBQ] = { compute_all_sbbq, compute_c_sbbq }, |
1391 | 3b46e624 | ths | |
1392 | 14ce26e7 | bellard | [CC_OP_LOGICQ] = { compute_all_logicq, compute_c_logicq }, |
1393 | 3b46e624 | ths | |
1394 | 14ce26e7 | bellard | [CC_OP_INCQ] = { compute_all_incq, compute_c_incl }, |
1395 | 14ce26e7 | bellard | |
1396 | 14ce26e7 | bellard | [CC_OP_DECQ] = { compute_all_decq, compute_c_incl }, |
1397 | 14ce26e7 | bellard | |
1398 | 14ce26e7 | bellard | [CC_OP_SHLQ] = { compute_all_shlq, compute_c_shlq }, |
1399 | 14ce26e7 | bellard | |
1400 | 14ce26e7 | bellard | [CC_OP_SARQ] = { compute_all_sarq, compute_c_sarl }, |
1401 | 14ce26e7 | bellard | #endif
|
1402 | 2c0262af | bellard | }; |
1403 | 2c0262af | bellard | |
1404 | 19e6c4b8 | bellard | void OPPROTO op_fcomi_dummy(void) |
1405 | 2c0262af | bellard | { |
1406 | 19e6c4b8 | bellard | T0 = 0;
|
1407 | 2c0262af | bellard | } |
1408 | 2c0262af | bellard | |
1409 | 2c0262af | bellard | /* threading support */
|
1410 | 2c0262af | bellard | void OPPROTO op_lock(void) |
1411 | 2c0262af | bellard | { |
1412 | 2c0262af | bellard | cpu_lock(); |
1413 | 2c0262af | bellard | } |
1414 | 2c0262af | bellard | |
1415 | 2c0262af | bellard | void OPPROTO op_unlock(void) |
1416 | 2c0262af | bellard | { |
1417 | 2c0262af | bellard | cpu_unlock(); |
1418 | 2c0262af | bellard | } |
1419 | 2c0262af | bellard | |
1420 | 14ce26e7 | bellard | /* SSE support */
|
1421 | 5af45186 | bellard | void OPPROTO op_com_dummy(void) |
1422 | 14ce26e7 | bellard | { |
1423 | 5af45186 | bellard | T0 = 0;
|
1424 | 664e0f19 | bellard | } |
1425 | 664e0f19 | bellard | |
1426 | 0573fbfc | ths | /* Secure Virtual Machine ops */
|
1427 | 0573fbfc | ths | |
1428 | 0573fbfc | ths | void OPPROTO op_vmrun(void) |
1429 | 0573fbfc | ths | { |
1430 | 0573fbfc | ths | helper_vmrun(EAX); |
1431 | 0573fbfc | ths | } |
1432 | 0573fbfc | ths | |
1433 | 0573fbfc | ths | void OPPROTO op_vmmcall(void) |
1434 | 0573fbfc | ths | { |
1435 | 0573fbfc | ths | helper_vmmcall(); |
1436 | 0573fbfc | ths | } |
1437 | 0573fbfc | ths | |
1438 | 0573fbfc | ths | void OPPROTO op_vmload(void) |
1439 | 0573fbfc | ths | { |
1440 | 0573fbfc | ths | helper_vmload(EAX); |
1441 | 0573fbfc | ths | } |
1442 | 0573fbfc | ths | |
1443 | 0573fbfc | ths | void OPPROTO op_vmsave(void) |
1444 | 0573fbfc | ths | { |
1445 | 0573fbfc | ths | helper_vmsave(EAX); |
1446 | 0573fbfc | ths | } |
1447 | 0573fbfc | ths | |
1448 | 0573fbfc | ths | void OPPROTO op_stgi(void) |
1449 | 0573fbfc | ths | { |
1450 | 0573fbfc | ths | helper_stgi(); |
1451 | 0573fbfc | ths | } |
1452 | 0573fbfc | ths | |
1453 | 0573fbfc | ths | void OPPROTO op_clgi(void) |
1454 | 0573fbfc | ths | { |
1455 | 0573fbfc | ths | helper_clgi(); |
1456 | 0573fbfc | ths | } |
1457 | 0573fbfc | ths | |
1458 | 0573fbfc | ths | void OPPROTO op_skinit(void) |
1459 | 0573fbfc | ths | { |
1460 | 0573fbfc | ths | helper_skinit(); |
1461 | 0573fbfc | ths | } |
1462 | 0573fbfc | ths | |
1463 | 0573fbfc | ths | void OPPROTO op_invlpga(void) |
1464 | 0573fbfc | ths | { |
1465 | 0573fbfc | ths | helper_invlpga(); |
1466 | 0573fbfc | ths | } |