root / hw / mips_jazz.c @ bc24a225
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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU MIPS Jazz support
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3 | 4ce7ff6e | aurel32 | *
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4 | 4ce7ff6e | aurel32 | * Copyright (c) 2007-2008 Hervé Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | 4ce7ff6e | aurel32 | #include "mips.h" |
27 | 4ce7ff6e | aurel32 | #include "pc.h" |
28 | 4ce7ff6e | aurel32 | #include "isa.h" |
29 | 4ce7ff6e | aurel32 | #include "fdc.h" |
30 | 4ce7ff6e | aurel32 | #include "sysemu.h" |
31 | 4ce7ff6e | aurel32 | #include "audio/audio.h" |
32 | 4ce7ff6e | aurel32 | #include "boards.h" |
33 | 4ce7ff6e | aurel32 | #include "net.h" |
34 | 4ce7ff6e | aurel32 | #include "scsi.h" |
35 | 4ce7ff6e | aurel32 | |
36 | 4ce7ff6e | aurel32 | #ifdef TARGET_WORDS_BIGENDIAN
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37 | 4ce7ff6e | aurel32 | #define BIOS_FILENAME "mips_bios.bin" |
38 | 4ce7ff6e | aurel32 | #else
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39 | 4ce7ff6e | aurel32 | #define BIOS_FILENAME "mipsel_bios.bin" |
40 | 4ce7ff6e | aurel32 | #endif
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41 | 4ce7ff6e | aurel32 | |
42 | 4ce7ff6e | aurel32 | enum jazz_model_e
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43 | 4ce7ff6e | aurel32 | { |
44 | 4ce7ff6e | aurel32 | JAZZ_MAGNUM, |
45 | c171148c | aurel32 | JAZZ_PICA61, |
46 | 4ce7ff6e | aurel32 | }; |
47 | 4ce7ff6e | aurel32 | |
48 | 4ce7ff6e | aurel32 | static void main_cpu_reset(void *opaque) |
49 | 4ce7ff6e | aurel32 | { |
50 | 4ce7ff6e | aurel32 | CPUState *env = opaque; |
51 | 4ce7ff6e | aurel32 | cpu_reset(env); |
52 | 4ce7ff6e | aurel32 | } |
53 | 4ce7ff6e | aurel32 | |
54 | 4ce7ff6e | aurel32 | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
55 | 4ce7ff6e | aurel32 | { |
56 | 4ce7ff6e | aurel32 | CPUState *env = opaque; |
57 | 4ce7ff6e | aurel32 | return cpu_inw(env, 0x71); |
58 | 4ce7ff6e | aurel32 | } |
59 | 4ce7ff6e | aurel32 | |
60 | 4ce7ff6e | aurel32 | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
61 | 4ce7ff6e | aurel32 | { |
62 | 4ce7ff6e | aurel32 | CPUState *env = opaque; |
63 | 4ce7ff6e | aurel32 | cpu_outw(env, 0x71, val & 0xff); |
64 | 4ce7ff6e | aurel32 | } |
65 | 4ce7ff6e | aurel32 | |
66 | 4ce7ff6e | aurel32 | static CPUReadMemoryFunc *rtc_read[3] = { |
67 | 4ce7ff6e | aurel32 | rtc_readb, |
68 | 4ce7ff6e | aurel32 | rtc_readb, |
69 | 4ce7ff6e | aurel32 | rtc_readb, |
70 | 4ce7ff6e | aurel32 | }; |
71 | 4ce7ff6e | aurel32 | |
72 | 4ce7ff6e | aurel32 | static CPUWriteMemoryFunc *rtc_write[3] = { |
73 | 4ce7ff6e | aurel32 | rtc_writeb, |
74 | 4ce7ff6e | aurel32 | rtc_writeb, |
75 | 4ce7ff6e | aurel32 | rtc_writeb, |
76 | 4ce7ff6e | aurel32 | }; |
77 | 4ce7ff6e | aurel32 | |
78 | c6945b15 | aurel32 | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
79 | c6945b15 | aurel32 | { |
80 | c6945b15 | aurel32 | /* Nothing to do. That is only to ensure that
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81 | c6945b15 | aurel32 | * the current DMA acknowledge cycle is completed. */
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82 | c6945b15 | aurel32 | } |
83 | c6945b15 | aurel32 | |
84 | c6945b15 | aurel32 | static CPUReadMemoryFunc *dma_dummy_read[3] = { |
85 | c6945b15 | aurel32 | NULL,
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86 | c6945b15 | aurel32 | NULL,
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87 | c6945b15 | aurel32 | NULL,
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88 | c6945b15 | aurel32 | }; |
89 | c6945b15 | aurel32 | |
90 | c6945b15 | aurel32 | static CPUWriteMemoryFunc *dma_dummy_write[3] = { |
91 | c6945b15 | aurel32 | dma_dummy_writeb, |
92 | c6945b15 | aurel32 | dma_dummy_writeb, |
93 | c6945b15 | aurel32 | dma_dummy_writeb, |
94 | c6945b15 | aurel32 | }; |
95 | c6945b15 | aurel32 | |
96 | 4ce7ff6e | aurel32 | #ifdef HAS_AUDIO
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97 | 4ce7ff6e | aurel32 | static void audio_init(qemu_irq *pic) |
98 | 4ce7ff6e | aurel32 | { |
99 | 4ce7ff6e | aurel32 | struct soundhw *c;
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100 | 4ce7ff6e | aurel32 | int audio_enabled = 0; |
101 | 4ce7ff6e | aurel32 | |
102 | 4ce7ff6e | aurel32 | for (c = soundhw; !audio_enabled && c->name; ++c) {
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103 | 4ce7ff6e | aurel32 | audio_enabled = c->enabled; |
104 | 4ce7ff6e | aurel32 | } |
105 | 4ce7ff6e | aurel32 | |
106 | 4ce7ff6e | aurel32 | if (audio_enabled) {
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107 | 4ce7ff6e | aurel32 | AudioState *s; |
108 | 4ce7ff6e | aurel32 | |
109 | 4ce7ff6e | aurel32 | s = AUD_init(); |
110 | 4ce7ff6e | aurel32 | if (s) {
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111 | 4ce7ff6e | aurel32 | for (c = soundhw; c->name; ++c) {
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112 | 4ce7ff6e | aurel32 | if (c->enabled) {
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113 | 4ce7ff6e | aurel32 | if (c->isa) {
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114 | 4ce7ff6e | aurel32 | c->init.init_isa(s, pic); |
115 | 4ce7ff6e | aurel32 | } |
116 | 4ce7ff6e | aurel32 | } |
117 | 4ce7ff6e | aurel32 | } |
118 | 4ce7ff6e | aurel32 | } |
119 | 4ce7ff6e | aurel32 | } |
120 | 4ce7ff6e | aurel32 | } |
121 | 4ce7ff6e | aurel32 | #endif
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122 | 4ce7ff6e | aurel32 | |
123 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
124 | 4ce7ff6e | aurel32 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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125 | 4ce7ff6e | aurel32 | |
126 | 4ce7ff6e | aurel32 | static
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127 | 00f82b8a | aurel32 | void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, |
128 | 3023f332 | aliguori | const char *cpu_model, |
129 | 4ce7ff6e | aurel32 | enum jazz_model_e jazz_model)
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130 | 4ce7ff6e | aurel32 | { |
131 | 4ce7ff6e | aurel32 | char buf[1024]; |
132 | 4ce7ff6e | aurel32 | int bios_size, n;
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133 | 4ce7ff6e | aurel32 | CPUState *env; |
134 | 4ce7ff6e | aurel32 | qemu_irq *rc4030, *i8259; |
135 | c6945b15 | aurel32 | rc4030_dma *dmas; |
136 | 68238a9e | aurel32 | void* rc4030_opaque;
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137 | 4ce7ff6e | aurel32 | void *scsi_hba;
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138 | 4ce7ff6e | aurel32 | int hd;
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139 | c6945b15 | aurel32 | int s_rtc, s_dma_dummy;
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140 | a65f56ee | aurel32 | NICInfo *nd; |
141 | 4ce7ff6e | aurel32 | PITState *pit; |
142 | 4ce7ff6e | aurel32 | BlockDriverState *fds[MAX_FD]; |
143 | 4ce7ff6e | aurel32 | qemu_irq esp_reset; |
144 | dcac9679 | pbrook | ram_addr_t ram_offset; |
145 | dcac9679 | pbrook | ram_addr_t bios_offset; |
146 | 4ce7ff6e | aurel32 | |
147 | 4ce7ff6e | aurel32 | /* init CPUs */
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148 | 4ce7ff6e | aurel32 | if (cpu_model == NULL) { |
149 | 4ce7ff6e | aurel32 | #ifdef TARGET_MIPS64
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150 | 4ce7ff6e | aurel32 | cpu_model = "R4000";
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151 | 4ce7ff6e | aurel32 | #else
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152 | 4ce7ff6e | aurel32 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
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153 | 4ce7ff6e | aurel32 | cpu_model = "24Kf";
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154 | 4ce7ff6e | aurel32 | #endif
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155 | 4ce7ff6e | aurel32 | } |
156 | 4ce7ff6e | aurel32 | env = cpu_init(cpu_model); |
157 | 4ce7ff6e | aurel32 | if (!env) {
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158 | 4ce7ff6e | aurel32 | fprintf(stderr, "Unable to find CPU definition\n");
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159 | 4ce7ff6e | aurel32 | exit(1);
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160 | 4ce7ff6e | aurel32 | } |
161 | 4ce7ff6e | aurel32 | qemu_register_reset(main_cpu_reset, env); |
162 | 4ce7ff6e | aurel32 | |
163 | 4ce7ff6e | aurel32 | /* allocate RAM */
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164 | dcac9679 | pbrook | ram_offset = qemu_ram_alloc(ram_size); |
165 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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166 | dcac9679 | pbrook | |
167 | dcac9679 | pbrook | bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE); |
168 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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169 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
170 | dcac9679 | pbrook | cpu_register_physical_memory(0xfff00000LL,
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171 | dcac9679 | pbrook | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
172 | 4ce7ff6e | aurel32 | |
173 | 4ce7ff6e | aurel32 | /* load the BIOS image. */
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174 | c6945b15 | aurel32 | if (bios_name == NULL) |
175 | c6945b15 | aurel32 | bios_name = BIOS_FILENAME; |
176 | c6945b15 | aurel32 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
177 | dcac9679 | pbrook | bios_size = load_image_targphys(buf, 0xfff00000LL, MAGNUM_BIOS_SIZE);
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178 | 4ce7ff6e | aurel32 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
179 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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180 | 4ce7ff6e | aurel32 | buf); |
181 | 4ce7ff6e | aurel32 | exit(1);
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182 | 4ce7ff6e | aurel32 | } |
183 | 4ce7ff6e | aurel32 | |
184 | 4ce7ff6e | aurel32 | /* Init CPU internal devices */
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185 | 4ce7ff6e | aurel32 | cpu_mips_irq_init_cpu(env); |
186 | 4ce7ff6e | aurel32 | cpu_mips_clock_init(env); |
187 | 4ce7ff6e | aurel32 | |
188 | 4ce7ff6e | aurel32 | /* Chipset */
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189 | 68238a9e | aurel32 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
190 | c6945b15 | aurel32 | s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL); |
191 | c6945b15 | aurel32 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
192 | 4ce7ff6e | aurel32 | |
193 | 4ce7ff6e | aurel32 | /* ISA devices */
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194 | 4ce7ff6e | aurel32 | i8259 = i8259_init(env->irq[4]);
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195 | c6945b15 | aurel32 | DMA_init(0);
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196 | 4ce7ff6e | aurel32 | pit = pit_init(0x40, i8259[0]); |
197 | 4ce7ff6e | aurel32 | pcspk_init(pit); |
198 | 4ce7ff6e | aurel32 | |
199 | 4ce7ff6e | aurel32 | /* ISA IO space at 0x90000000 */
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200 | 4ce7ff6e | aurel32 | isa_mmio_init(0x90000000, 0x01000000); |
201 | 4ce7ff6e | aurel32 | isa_mem_base = 0x11000000;
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202 | 4ce7ff6e | aurel32 | |
203 | 4ce7ff6e | aurel32 | /* Video card */
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204 | 4ce7ff6e | aurel32 | switch (jazz_model) {
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205 | 4ce7ff6e | aurel32 | case JAZZ_MAGNUM:
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206 | b584726d | pbrook | g364fb_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0, rc4030[3]); |
207 | 4ce7ff6e | aurel32 | break;
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208 | c171148c | aurel32 | case JAZZ_PICA61:
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209 | b584726d | pbrook | isa_vga_mm_init(vga_ram_size, 0x40000000, 0x60000000, 0); |
210 | c171148c | aurel32 | break;
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211 | 4ce7ff6e | aurel32 | default:
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212 | 4ce7ff6e | aurel32 | break;
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213 | 4ce7ff6e | aurel32 | } |
214 | 4ce7ff6e | aurel32 | |
215 | 4ce7ff6e | aurel32 | /* Network controller */
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216 | a65f56ee | aurel32 | for (n = 0; n < nb_nics; n++) { |
217 | a65f56ee | aurel32 | nd = &nd_table[n]; |
218 | a65f56ee | aurel32 | if (!nd->model)
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219 | a65f56ee | aurel32 | nd->model = "dp83932";
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220 | a65f56ee | aurel32 | if (strcmp(nd->model, "dp83932") == 0) { |
221 | a65f56ee | aurel32 | dp83932_init(nd, 0x80001000, 2, rc4030[4], |
222 | a65f56ee | aurel32 | rc4030_opaque, rc4030_dma_memory_rw); |
223 | a65f56ee | aurel32 | break;
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224 | a65f56ee | aurel32 | } else if (strcmp(nd->model, "?") == 0) { |
225 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Supported NICs: dp83932\n");
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226 | a65f56ee | aurel32 | exit(1);
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227 | a65f56ee | aurel32 | } else {
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228 | a65f56ee | aurel32 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
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229 | a65f56ee | aurel32 | exit(1);
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230 | a65f56ee | aurel32 | } |
231 | a65f56ee | aurel32 | } |
232 | 4ce7ff6e | aurel32 | |
233 | 4ce7ff6e | aurel32 | /* SCSI adapter */
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234 | 5d20fa6b | blueswir1 | scsi_hba = esp_init(0x80002000, 0, |
235 | 68238a9e | aurel32 | rc4030_dma_read, rc4030_dma_write, dmas[0],
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236 | 4ce7ff6e | aurel32 | rc4030[5], &esp_reset);
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237 | 4ce7ff6e | aurel32 | for (n = 0; n < ESP_MAX_DEVS; n++) { |
238 | 4ce7ff6e | aurel32 | hd = drive_get_index(IF_SCSI, 0, n);
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239 | 4ce7ff6e | aurel32 | if (hd != -1) { |
240 | 4ce7ff6e | aurel32 | esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n); |
241 | 4ce7ff6e | aurel32 | } |
242 | 4ce7ff6e | aurel32 | } |
243 | 4ce7ff6e | aurel32 | |
244 | 4ce7ff6e | aurel32 | /* Floppy */
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245 | 4ce7ff6e | aurel32 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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246 | 4ce7ff6e | aurel32 | fprintf(stderr, "qemu: too many floppy drives\n");
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247 | 4ce7ff6e | aurel32 | exit(1);
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248 | 4ce7ff6e | aurel32 | } |
249 | 4ce7ff6e | aurel32 | for (n = 0; n < MAX_FD; n++) { |
250 | 4ce7ff6e | aurel32 | int fd = drive_get_index(IF_FLOPPY, 0, n); |
251 | 4ce7ff6e | aurel32 | if (fd != -1) |
252 | 4ce7ff6e | aurel32 | fds[n] = drives_table[fd].bdrv; |
253 | 4ce7ff6e | aurel32 | else
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254 | 4ce7ff6e | aurel32 | fds[n] = NULL;
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255 | 4ce7ff6e | aurel32 | } |
256 | 4ce7ff6e | aurel32 | fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds); |
257 | 4ce7ff6e | aurel32 | |
258 | 4ce7ff6e | aurel32 | /* Real time clock */
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259 | 42fc73a1 | aurel32 | rtc_init(0x70, i8259[8], 1980); |
260 | 4ce7ff6e | aurel32 | s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
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261 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
262 | 4ce7ff6e | aurel32 | |
263 | 4ce7ff6e | aurel32 | /* Keyboard (i8042) */
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264 | 4efbe58f | aurel32 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
265 | 4ce7ff6e | aurel32 | |
266 | 4ce7ff6e | aurel32 | /* Serial ports */
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267 | 4ce7ff6e | aurel32 | if (serial_hds[0]) |
268 | b6cd0ea1 | aurel32 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1); |
269 | 4ce7ff6e | aurel32 | if (serial_hds[1]) |
270 | b6cd0ea1 | aurel32 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1); |
271 | 4ce7ff6e | aurel32 | |
272 | 4ce7ff6e | aurel32 | /* Parallel port */
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273 | 4ce7ff6e | aurel32 | if (parallel_hds[0]) |
274 | 4ce7ff6e | aurel32 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); |
275 | 4ce7ff6e | aurel32 | |
276 | 4ce7ff6e | aurel32 | /* Sound card */
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277 | 4ce7ff6e | aurel32 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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278 | 4ce7ff6e | aurel32 | #ifdef HAS_AUDIO
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279 | 4ce7ff6e | aurel32 | audio_init(i8259); |
280 | 4ce7ff6e | aurel32 | #endif
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281 | 4ce7ff6e | aurel32 | |
282 | 4ce7ff6e | aurel32 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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283 | 4ce7ff6e | aurel32 | ds1225y_init(0x80009000, "nvram"); |
284 | 4ce7ff6e | aurel32 | |
285 | 4ce7ff6e | aurel32 | /* LED indicator */
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286 | 3023f332 | aliguori | jazz_led_init(0x8000f000);
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287 | 4ce7ff6e | aurel32 | } |
288 | 4ce7ff6e | aurel32 | |
289 | 4ce7ff6e | aurel32 | static
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290 | 00f82b8a | aurel32 | void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size, |
291 | 3023f332 | aliguori | const char *boot_device, |
292 | 4ce7ff6e | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
293 | 4ce7ff6e | aurel32 | const char *initrd_filename, const char *cpu_model) |
294 | 4ce7ff6e | aurel32 | { |
295 | 3023f332 | aliguori | mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_MAGNUM); |
296 | 4ce7ff6e | aurel32 | } |
297 | 4ce7ff6e | aurel32 | |
298 | c171148c | aurel32 | static
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299 | 00f82b8a | aurel32 | void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size, |
300 | 3023f332 | aliguori | const char *boot_device, |
301 | c171148c | aurel32 | const char *kernel_filename, const char *kernel_cmdline, |
302 | c171148c | aurel32 | const char *initrd_filename, const char *cpu_model) |
303 | c171148c | aurel32 | { |
304 | 3023f332 | aliguori | mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_PICA61); |
305 | c171148c | aurel32 | } |
306 | c171148c | aurel32 | |
307 | 4ce7ff6e | aurel32 | QEMUMachine mips_magnum_machine = { |
308 | eec2743e | ths | .name = "magnum",
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309 | eec2743e | ths | .desc = "MIPS Magnum",
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310 | eec2743e | ths | .init = mips_magnum_init, |
311 | c6945b15 | aurel32 | .use_scsi = 1,
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312 | 4ce7ff6e | aurel32 | }; |
313 | c171148c | aurel32 | |
314 | c171148c | aurel32 | QEMUMachine mips_pica61_machine = { |
315 | eec2743e | ths | .name = "pica61",
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316 | eec2743e | ths | .desc = "Acer Pica 61",
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317 | eec2743e | ths | .init = mips_pica61_init, |
318 | c6945b15 | aurel32 | .use_scsi = 1,
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319 | c171148c | aurel32 | }; |