Revision bc24a225 hw/pxa2xx_dma.c
| b/hw/pxa2xx_dma.c | ||
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#include "hw.h" |
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#include "pxa.h" |
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struct pxa2xx_dma_channel_s {
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typedef struct {
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target_phys_addr_t descr; |
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target_phys_addr_t src; |
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target_phys_addr_t dest; |
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uint32_t cmd; |
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uint32_t state; |
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int request; |
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}; |
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} PXA2xxDMAChannel;
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/* Allow the DMA to be used as a PIC. */ |
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typedef void (*pxa2xx_dma_handler_t)(void *opaque, int irq, int level); |
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struct pxa2xx_dma_state_s {
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struct PXA2xxDMAState {
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pxa2xx_dma_handler_t handler; |
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qemu_irq irq; |
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| ... | ... | |
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uint32_t pio; |
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int channels; |
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struct pxa2xx_dma_channel_s *chan;
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PXA2xxDMAChannel *chan;
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uint8_t *req; |
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|
| ... | ... | |
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#define DCSR_NODESCFETCH (1 << 30) |
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#define DCSR_RUN (1 << 31) |
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static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch)
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static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
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{
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if (ch >= 0) {
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if ((s->chan[ch].state & DCSR_STOPIRQEN) && |
| ... | ... | |
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} |
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static inline void pxa2xx_dma_descriptor_fetch( |
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struct pxa2xx_dma_state_s *s, int ch)
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PXA2xxDMAState *s, int ch)
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{
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uint32_t desc[4]; |
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target_phys_addr_t daddr = s->chan[ch].descr & ~0xf; |
| ... | ... | |
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s->chan[ch].state |= DCSR_STARTINTR; |
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} |
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static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s)
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static void pxa2xx_dma_run(PXA2xxDMAState *s)
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{
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int c, srcinc, destinc; |
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uint32_t n, size; |
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uint32_t width; |
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uint32_t length; |
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uint8_t buffer[32]; |
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struct pxa2xx_dma_channel_s *ch;
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PXA2xxDMAChannel *ch;
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if (s->running ++) |
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return; |
| ... | ... | |
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static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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unsigned int channel; |
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switch (offset) {
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| ... | ... | |
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static void pxa2xx_dma_write(void *opaque, |
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target_phys_addr_t offset, uint32_t value) |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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unsigned int channel; |
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switch (offset) {
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| ... | ... | |
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static void pxa2xx_dma_save(QEMUFile *f, void *opaque) |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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int i; |
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qemu_put_be32(f, s->channels); |
| ... | ... | |
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static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) |
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{
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struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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int i; |
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if (qemu_get_be32(f) != s->channels) |
| ... | ... | |
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return 0; |
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} |
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static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base,
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static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
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qemu_irq irq, int channels) |
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{
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int i, iomemtype; |
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struct pxa2xx_dma_state_s *s;
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s = (struct pxa2xx_dma_state_s *)
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qemu_mallocz(sizeof(struct pxa2xx_dma_state_s));
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PXA2xxDMAState *s;
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s = (PXA2xxDMAState *)
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qemu_mallocz(sizeof(PXA2xxDMAState));
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s->channels = channels; |
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s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels);
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s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels);
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s->irq = irq; |
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s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request; |
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s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
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memset(s->chan, 0, sizeof(struct pxa2xx_dma_channel_s) * s->channels);
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memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
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for (i = 0; i < s->channels; i ++) |
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s->chan[i].state = DCSR_STOPINTR; |
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|
| ... | ... | |
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return s; |
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} |
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struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
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PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
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qemu_irq irq) |
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{
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return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); |
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} |
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struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
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PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
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qemu_irq irq) |
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{
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return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); |
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} |
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void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on)
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void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on)
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{
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int ch; |
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if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) |
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