Revision bc265319 target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 321 | 321 |
} |
| 322 | 322 |
} |
| 323 | 323 |
|
| 324 |
static void raise_exception(int tt) |
|
| 325 |
{
|
|
| 326 |
env->exception_index = tt; |
|
| 327 |
cpu_loop_exit(env); |
|
| 328 |
} |
|
| 329 |
|
|
| 330 |
void HELPER(raise_exception)(int tt) |
|
| 331 |
{
|
|
| 332 |
raise_exception(tt); |
|
| 333 |
} |
|
| 334 |
|
|
| 335 | 324 |
void helper_check_align(target_ulong addr, uint32_t align) |
| 336 | 325 |
{
|
| 337 | 326 |
if (addr & align) {
|
| ... | ... | |
| 339 | 328 |
printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
|
| 340 | 329 |
"\n", addr, env->pc); |
| 341 | 330 |
#endif |
| 342 |
raise_exception(TT_UNALIGNED);
|
|
| 331 |
helper_raise_exception(env, TT_UNALIGNED);
|
|
| 343 | 332 |
} |
| 344 | 333 |
} |
| 345 | 334 |
|
| ... | ... | |
| 853 | 842 |
if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
|
| 854 | 843 |
/* Unmasked exception, generate a trap */ |
| 855 | 844 |
env->fsr |= FSR_FTT_IEEE_EXCP; |
| 856 |
raise_exception(TT_FP_EXCP);
|
|
| 845 |
helper_raise_exception(env, TT_FP_EXCP);
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|
| 857 | 846 |
} else {
|
| 858 | 847 |
/* Accumulate exceptions */ |
| 859 | 848 |
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5; |
| ... | ... | |
| 907 | 896 |
(env->fsr & FSR_NVM)) { \
|
| 908 | 897 |
env->fsr |= FSR_NVC; \ |
| 909 | 898 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
| 910 |
raise_exception(TT_FP_EXCP); \
|
|
| 899 |
helper_raise_exception(env, TT_FP_EXCP); \
|
|
| 911 | 900 |
} \ |
| 912 | 901 |
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
| 913 | 902 |
case float_relation_unordered: \ |
| 914 | 903 |
if ((env->fsr & FSR_NVM)) { \
|
| 915 | 904 |
env->fsr |= FSR_NVC; \ |
| 916 | 905 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
| 917 |
raise_exception(TT_FP_EXCP); \
|
|
| 906 |
helper_raise_exception(env, TT_FP_EXCP); \
|
|
| 918 | 907 |
} else { \
|
| 919 | 908 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
| 920 | 909 |
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
| ... | ... | |
| 943 | 932 |
(env->fsr & FSR_NVM)) { \
|
| 944 | 933 |
env->fsr |= FSR_NVC; \ |
| 945 | 934 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
| 946 |
raise_exception(TT_FP_EXCP); \
|
|
| 935 |
helper_raise_exception(env, TT_FP_EXCP); \
|
|
| 947 | 936 |
} \ |
| 948 | 937 |
switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
|
| 949 | 938 |
case float_relation_unordered: \ |
| 950 | 939 |
if ((env->fsr & FSR_NVM)) { \
|
| 951 | 940 |
env->fsr |= FSR_NVC; \ |
| 952 | 941 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
| 953 |
raise_exception(TT_FP_EXCP); \
|
|
| 942 |
helper_raise_exception(env, TT_FP_EXCP); \
|
|
| 954 | 943 |
} else { \
|
| 955 | 944 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
| 956 | 945 |
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
| ... | ... | |
| 2377 | 2366 |
#endif |
| 2378 | 2367 |
|
| 2379 | 2368 |
if (asi < 0x80) |
| 2380 |
raise_exception(TT_PRIV_ACT);
|
|
| 2369 |
helper_raise_exception(env, TT_PRIV_ACT);
|
|
| 2381 | 2370 |
|
| 2382 | 2371 |
helper_check_align(addr, size - 1); |
| 2383 | 2372 |
addr = asi_address_mask(env, asi, addr); |
| ... | ... | |
| 2480 | 2469 |
dump_asi("write", addr, asi, size, val);
|
| 2481 | 2470 |
#endif |
| 2482 | 2471 |
if (asi < 0x80) |
| 2483 |
raise_exception(TT_PRIV_ACT);
|
|
| 2472 |
helper_raise_exception(env, TT_PRIV_ACT);
|
|
| 2484 | 2473 |
|
| 2485 | 2474 |
helper_check_align(addr, size - 1); |
| 2486 | 2475 |
addr = asi_address_mask(env, asi, addr); |
| ... | ... | |
| 2557 | 2546 |
|| (cpu_has_hypervisor(env) |
| 2558 | 2547 |
&& asi >= 0x30 && asi < 0x80 |
| 2559 | 2548 |
&& !(env->hpstate & HS_PRIV))) |
| 2560 |
raise_exception(TT_PRIV_ACT);
|
|
| 2549 |
helper_raise_exception(env, TT_PRIV_ACT);
|
|
| 2561 | 2550 |
|
| 2562 | 2551 |
helper_check_align(addr, size - 1); |
| 2563 | 2552 |
addr = asi_address_mask(env, asi, addr); |
| ... | ... | |
| 2578 | 2567 |
dump_asi("read ", last_addr, asi, size, ret);
|
| 2579 | 2568 |
#endif |
| 2580 | 2569 |
/* env->exception_index is set in get_physical_address_data(). */ |
| 2581 |
raise_exception(env->exception_index);
|
|
| 2570 |
helper_raise_exception(env, env->exception_index);
|
|
| 2582 | 2571 |
} |
| 2583 | 2572 |
|
| 2584 | 2573 |
/* convert nonfaulting load ASIs to normal load ASIs */ |
| ... | ... | |
| 2711 | 2700 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
| 2712 | 2701 |
case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
| 2713 | 2702 |
// Only ldda allowed |
| 2714 |
raise_exception(TT_ILL_INSN);
|
|
| 2703 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 2715 | 2704 |
return 0; |
| 2716 | 2705 |
case 0x04: // Nucleus |
| 2717 | 2706 |
case 0x0c: // Nucleus Little Endian (LE) |
| ... | ... | |
| 2914 | 2903 |
|| (cpu_has_hypervisor(env) |
| 2915 | 2904 |
&& asi >= 0x30 && asi < 0x80 |
| 2916 | 2905 |
&& !(env->hpstate & HS_PRIV))) |
| 2917 |
raise_exception(TT_PRIV_ACT);
|
|
| 2906 |
helper_raise_exception(env, TT_PRIV_ACT);
|
|
| 2918 | 2907 |
|
| 2919 | 2908 |
helper_check_align(addr, size - 1); |
| 2920 | 2909 |
addr = asi_address_mask(env, asi, addr); |
| ... | ... | |
| 3071 | 3060 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
| 3072 | 3061 |
case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
| 3073 | 3062 |
// Only ldda allowed |
| 3074 |
raise_exception(TT_ILL_INSN);
|
|
| 3063 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3075 | 3064 |
return; |
| 3076 | 3065 |
case 0x04: // Nucleus |
| 3077 | 3066 |
case 0x0c: // Nucleus Little Endian (LE) |
| ... | ... | |
| 3291 | 3280 |
|| (cpu_has_hypervisor(env) |
| 3292 | 3281 |
&& asi >= 0x30 && asi < 0x80 |
| 3293 | 3282 |
&& !(env->hpstate & HS_PRIV))) |
| 3294 |
raise_exception(TT_PRIV_ACT);
|
|
| 3283 |
helper_raise_exception(env, TT_PRIV_ACT);
|
|
| 3295 | 3284 |
|
| 3296 | 3285 |
addr = asi_address_mask(env, asi, addr); |
| 3297 | 3286 |
|
| ... | ... | |
| 3350 | 3339 |
case 0xf8: /* UA2007/JPS1 Block load primary LE */ |
| 3351 | 3340 |
case 0xf9: /* UA2007/JPS1 Block load secondary LE */ |
| 3352 | 3341 |
if (rd & 7) {
|
| 3353 |
raise_exception(TT_ILL_INSN);
|
|
| 3342 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3354 | 3343 |
return; |
| 3355 | 3344 |
} |
| 3356 | 3345 |
helper_check_align(addr, 0x3f); |
| ... | ... | |
| 3370 | 3359 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
| 3371 | 3360 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
| 3372 | 3361 |
if (rd & 7) {
|
| 3373 |
raise_exception(TT_ILL_INSN);
|
|
| 3362 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3374 | 3363 |
return; |
| 3375 | 3364 |
} |
| 3376 | 3365 |
helper_check_align(addr, 0x3f); |
| ... | ... | |
| 3423 | 3412 |
case 0xf8: /* UA2007/JPS1 Block store primary LE */ |
| 3424 | 3413 |
case 0xf9: /* UA2007/JPS1 Block store secondary LE */ |
| 3425 | 3414 |
if (rd & 7) {
|
| 3426 |
raise_exception(TT_ILL_INSN);
|
|
| 3415 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3427 | 3416 |
return; |
| 3428 | 3417 |
} |
| 3429 | 3418 |
helper_check_align(addr, 0x3f); |
| ... | ... | |
| 3443 | 3432 |
case 0x78: /* JPS1 Block load primary LE, user privilege */ |
| 3444 | 3433 |
case 0x79: /* JPS1 Block load secondary LE, user privilege */ |
| 3445 | 3434 |
if (rd & 7) {
|
| 3446 |
raise_exception(TT_ILL_INSN);
|
|
| 3435 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3447 | 3436 |
return; |
| 3448 | 3437 |
} |
| 3449 | 3438 |
helper_check_align(addr, 0x3f); |
| ... | ... | |
| 3510 | 3499 |
unsigned int cwp; |
| 3511 | 3500 |
|
| 3512 | 3501 |
if (env->psret == 1) |
| 3513 |
raise_exception(TT_ILL_INSN);
|
|
| 3502 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3514 | 3503 |
|
| 3515 | 3504 |
env->psret = 1; |
| 3516 | 3505 |
cwp = cwp_inc(env->cwp + 1) ; |
| 3517 | 3506 |
if (env->wim & (1 << cwp)) {
|
| 3518 |
raise_exception(TT_WIN_UNF);
|
|
| 3507 |
helper_raise_exception(env, TT_WIN_UNF);
|
|
| 3519 | 3508 |
} |
| 3520 | 3509 |
set_cwp(cwp); |
| 3521 | 3510 |
env->psrs = env->psrps; |
| ... | ... | |
| 3532 | 3521 |
x1 = (b & 0xffffffff); |
| 3533 | 3522 |
|
| 3534 | 3523 |
if (x1 == 0) {
|
| 3535 |
raise_exception(TT_DIV_ZERO);
|
|
| 3524 |
helper_raise_exception(env, TT_DIV_ZERO);
|
|
| 3536 | 3525 |
} |
| 3537 | 3526 |
|
| 3538 | 3527 |
x0 = x0 / x1; |
| ... | ... | |
| 3569 | 3558 |
x1 = (b & 0xffffffff); |
| 3570 | 3559 |
|
| 3571 | 3560 |
if (x1 == 0) {
|
| 3572 |
raise_exception(TT_DIV_ZERO);
|
|
| 3561 |
helper_raise_exception(env, TT_DIV_ZERO);
|
|
| 3573 | 3562 |
} |
| 3574 | 3563 |
|
| 3575 | 3564 |
x0 = x0 / x1; |
| ... | ... | |
| 3754 | 3743 |
} |
| 3755 | 3744 |
#endif |
| 3756 | 3745 |
|
| 3757 |
void helper_debug(void) |
|
| 3758 |
{
|
|
| 3759 |
env->exception_index = EXCP_DEBUG; |
|
| 3760 |
cpu_loop_exit(env); |
|
| 3761 |
} |
|
| 3762 |
|
|
| 3763 | 3746 |
#ifndef TARGET_SPARC64 |
| 3764 | 3747 |
/* XXX: use another pointer for %iN registers to avoid slow wrapping |
| 3765 | 3748 |
handling ? */ |
| ... | ... | |
| 3769 | 3752 |
|
| 3770 | 3753 |
cwp = cwp_dec(env->cwp - 1); |
| 3771 | 3754 |
if (env->wim & (1 << cwp)) {
|
| 3772 |
raise_exception(TT_WIN_OVF);
|
|
| 3755 |
helper_raise_exception(env, TT_WIN_OVF);
|
|
| 3773 | 3756 |
} |
| 3774 | 3757 |
set_cwp(cwp); |
| 3775 | 3758 |
} |
| ... | ... | |
| 3780 | 3763 |
|
| 3781 | 3764 |
cwp = cwp_inc(env->cwp + 1); |
| 3782 | 3765 |
if (env->wim & (1 << cwp)) {
|
| 3783 |
raise_exception(TT_WIN_UNF);
|
|
| 3766 |
helper_raise_exception(env, TT_WIN_UNF);
|
|
| 3784 | 3767 |
} |
| 3785 | 3768 |
set_cwp(cwp); |
| 3786 | 3769 |
} |
| ... | ... | |
| 3788 | 3771 |
void helper_wrpsr(target_ulong new_psr) |
| 3789 | 3772 |
{
|
| 3790 | 3773 |
if ((new_psr & PSR_CWP) >= env->nwindows) {
|
| 3791 |
raise_exception(TT_ILL_INSN);
|
|
| 3774 |
helper_raise_exception(env, TT_ILL_INSN);
|
|
| 3792 | 3775 |
} else {
|
| 3793 | 3776 |
cpu_put_psr(env, new_psr); |
| 3794 | 3777 |
} |
| ... | ... | |
| 3808 | 3791 |
|
| 3809 | 3792 |
cwp = cwp_dec(env->cwp - 1); |
| 3810 | 3793 |
if (env->cansave == 0) {
|
| 3811 |
raise_exception(TT_SPILL | (env->otherwin != 0 ? |
|
| 3812 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
|
| 3813 |
((env->wstate & 0x7) << 2))); |
|
| 3794 |
helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ? |
|
| 3795 |
(TT_WOTHER | |
|
| 3796 |
((env->wstate & 0x38) >> 1)) : |
|
| 3797 |
((env->wstate & 0x7) << 2))); |
|
| 3814 | 3798 |
} else {
|
| 3815 | 3799 |
if (env->cleanwin - env->canrestore == 0) {
|
| 3816 | 3800 |
// XXX Clean windows without trap |
| 3817 |
raise_exception(TT_CLRWIN);
|
|
| 3801 |
helper_raise_exception(env, TT_CLRWIN);
|
|
| 3818 | 3802 |
} else {
|
| 3819 | 3803 |
env->cansave--; |
| 3820 | 3804 |
env->canrestore++; |
| ... | ... | |
| 3829 | 3813 |
|
| 3830 | 3814 |
cwp = cwp_inc(env->cwp + 1); |
| 3831 | 3815 |
if (env->canrestore == 0) {
|
| 3832 |
raise_exception(TT_FILL | (env->otherwin != 0 ? |
|
| 3833 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
|
| 3834 |
((env->wstate & 0x7) << 2))); |
|
| 3816 |
helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ? |
|
| 3817 |
(TT_WOTHER | |
|
| 3818 |
((env->wstate & 0x38) >> 1)) : |
|
| 3819 |
((env->wstate & 0x7) << 2))); |
|
| 3835 | 3820 |
} else {
|
| 3836 | 3821 |
env->cansave++; |
| 3837 | 3822 |
env->canrestore--; |
| ... | ... | |
| 3842 | 3827 |
void helper_flushw(void) |
| 3843 | 3828 |
{
|
| 3844 | 3829 |
if (env->cansave != env->nwindows - 2) {
|
| 3845 |
raise_exception(TT_SPILL | (env->otherwin != 0 ? |
|
| 3846 |
(TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
|
| 3847 |
((env->wstate & 0x7) << 2))); |
|
| 3830 |
helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ? |
|
| 3831 |
(TT_WOTHER | |
|
| 3832 |
((env->wstate & 0x38) >> 1)) : |
|
| 3833 |
((env->wstate & 0x7) << 2))); |
|
| 3848 | 3834 |
} |
| 3849 | 3835 |
} |
| 3850 | 3836 |
|
| ... | ... | |
| 4196 | 4182 |
"\n", addr, env->pc); |
| 4197 | 4183 |
#endif |
| 4198 | 4184 |
cpu_restore_state2(retaddr); |
| 4199 |
raise_exception(TT_UNALIGNED);
|
|
| 4185 |
helper_raise_exception(env, TT_UNALIGNED);
|
|
| 4200 | 4186 |
} |
| 4201 | 4187 |
|
| 4202 | 4188 |
/* try to fill the TLB and return an exception if error. If retaddr is |
| ... | ... | |
| 4266 | 4252 |
|
| 4267 | 4253 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
|
| 4268 | 4254 |
if (is_exec) |
| 4269 |
raise_exception(TT_CODE_ACCESS);
|
|
| 4255 |
helper_raise_exception(env, TT_CODE_ACCESS);
|
|
| 4270 | 4256 |
else |
| 4271 |
raise_exception(TT_DATA_ACCESS);
|
|
| 4257 |
helper_raise_exception(env, TT_DATA_ACCESS);
|
|
| 4272 | 4258 |
} |
| 4273 | 4259 |
|
| 4274 | 4260 |
/* flush neverland mappings created during no-fault mode, |
| ... | ... | |
| 4293 | 4279 |
#endif |
| 4294 | 4280 |
|
| 4295 | 4281 |
if (is_exec) |
| 4296 |
raise_exception(TT_CODE_ACCESS);
|
|
| 4282 |
helper_raise_exception(env, TT_CODE_ACCESS);
|
|
| 4297 | 4283 |
else |
| 4298 |
raise_exception(TT_DATA_ACCESS);
|
|
| 4284 |
helper_raise_exception(env, TT_DATA_ACCESS);
|
|
| 4299 | 4285 |
} |
| 4300 | 4286 |
#endif |
| 4301 | 4287 |
|
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