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/*
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* OpenPIC emulation
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*
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* Copyright (c) 2004 Jocelyn Mayer
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* 2011 Alexander Graf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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*
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* Based on OpenPic implementations:
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* - Intel GW80314 I/O companion chip developer's manual
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* - Motorola MPC8245 & MPC8540 user manuals.
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* - Motorola MCP750 (aka Raven) programmer manual.
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* - Motorola Harrier programmer manuel
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*
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* Serial interrupts, as implemented in Raven chipset are not supported yet.
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*
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*/
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#include "hw.h" |
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#include "ppc_mac.h" |
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#include "pci.h" |
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#include "openpic.h" |
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//#define DEBUG_OPENPIC
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#ifdef DEBUG_OPENPIC
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#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do { } while (0) |
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#endif
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#define USE_MPCxxx /* Intel model is broken, for now */ |
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#if defined (USE_INTEL_GW80314)
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/* Intel GW80314 I/O Companion chip */
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#define MAX_CPU 4 |
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#define MAX_IRQ 32 |
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#define MAX_DBL 4 |
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#define MAX_MBX 4 |
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#define MAX_TMR 4 |
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#define VECTOR_BITS 8 |
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#define MAX_IPI 0 |
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#define VID (0x00000000) |
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#elif defined(USE_MPCxxx)
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#define MAX_CPU 2 |
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#define MAX_IRQ 128 |
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#define MAX_DBL 0 |
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#define MAX_MBX 0 |
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#define MAX_TMR 4 |
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#define VECTOR_BITS 8 |
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#define MAX_IPI 4 |
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#define VID 0x03 /* MPIC version ID */ |
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#define VENI 0x00000000 /* Vendor ID */ |
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enum {
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IRQ_IPVP = 0,
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IRQ_IDE, |
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}; |
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/* OpenPIC */
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#define OPENPIC_MAX_CPU 2 |
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#define OPENPIC_MAX_IRQ 64 |
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#define OPENPIC_EXT_IRQ 48 |
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#define OPENPIC_MAX_TMR MAX_TMR
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#define OPENPIC_MAX_IPI MAX_IPI
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/* Interrupt definitions */
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#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */ |
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#define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */ |
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#define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */ |
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#if OPENPIC_MAX_IPI > 0 |
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#define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */ |
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#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */ |
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#else
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#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */ |
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#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */ |
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#endif
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/* MPIC */
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#define MPIC_MAX_CPU 1 |
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#define MPIC_MAX_EXT 12 |
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#define MPIC_MAX_INT 64 |
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#define MPIC_MAX_MSG 4 |
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#define MPIC_MAX_MSI 8 |
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#define MPIC_MAX_TMR MAX_TMR
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#define MPIC_MAX_IPI MAX_IPI
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#define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
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/* Interrupt definitions */
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#define MPIC_EXT_IRQ 0 |
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#define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
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#define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
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#define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
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#define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
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#define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
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#define MPIC_GLB_REG_START 0x0 |
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#define MPIC_GLB_REG_SIZE 0x10F0 |
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#define MPIC_TMR_REG_START 0x10F0 |
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#define MPIC_TMR_REG_SIZE 0x220 |
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#define MPIC_EXT_REG_START 0x10000 |
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#define MPIC_EXT_REG_SIZE 0x180 |
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#define MPIC_INT_REG_START 0x10200 |
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#define MPIC_INT_REG_SIZE 0x800 |
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#define MPIC_MSG_REG_START 0x11600 |
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#define MPIC_MSG_REG_SIZE 0x100 |
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#define MPIC_MSI_REG_START 0x11C00 |
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#define MPIC_MSI_REG_SIZE 0x100 |
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#define MPIC_CPU_REG_START 0x20000 |
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#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) |
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enum mpic_ide_bits {
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IDR_EP = 0,
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IDR_CI0 = 1,
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IDR_CI1 = 2,
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IDR_P1 = 30,
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IDR_P0 = 31,
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}; |
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#else
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#error "Please select which OpenPic implementation is to be emulated" |
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#endif
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#define OPENPIC_PAGE_SIZE 4096 |
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#define BF_WIDTH(_bits_) \
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(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
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static inline void set_bit (uint32_t *field, int bit) |
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{ |
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field[bit >> 5] |= 1 << (bit & 0x1F); |
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} |
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static inline void reset_bit (uint32_t *field, int bit) |
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{ |
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field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
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} |
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static inline int test_bit (uint32_t *field, int bit) |
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{ |
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return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
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} |
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static int get_current_cpu(void) |
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{ |
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return cpu_single_env->cpu_index;
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} |
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static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr, |
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int idx);
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static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr, |
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uint32_t val, int idx);
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enum {
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IRQ_EXTERNAL = 0x01,
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IRQ_INTERNAL = 0x02,
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IRQ_TIMER = 0x04,
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IRQ_SPECIAL = 0x08,
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}; |
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typedef struct IRQ_queue_t { |
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uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
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int next;
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int priority;
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} IRQ_queue_t; |
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typedef struct IRQ_src_t { |
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uint32_t ipvp; /* IRQ vector/priority register */
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uint32_t ide; /* IRQ destination register */
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int type;
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int last_cpu;
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int pending; /* TRUE if IRQ is pending */ |
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} IRQ_src_t; |
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enum IPVP_bits {
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IPVP_MASK = 31,
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IPVP_ACTIVITY = 30,
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IPVP_MODE = 29,
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IPVP_POLARITY = 23,
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IPVP_SENSE = 22,
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}; |
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#define IPVP_PRIORITY_MASK (0x1F << 16) |
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#define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
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#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
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#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
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typedef struct IRQ_dst_t { |
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uint32_t tfrr; |
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uint32_t pctp; /* CPU current task priority */
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uint32_t pcsr; /* CPU sensitivity register */
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IRQ_queue_t raised; |
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IRQ_queue_t servicing; |
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qemu_irq *irqs; |
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} IRQ_dst_t; |
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typedef struct openpic_t { |
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PCIDevice pci_dev; |
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MemoryRegion mem; |
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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uint32_t glbc; /* Global configuration register */
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uint32_t micr; /* MPIC interrupt configuration register */
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uint32_t veni; /* Vendor identification register */
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uint32_t pint; /* Processor initialization register */
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uint32_t spve; /* Spurious vector register */
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uint32_t tifr; /* Timer frequency reporting register */
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/* Source registers */
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IRQ_src_t src[MAX_IRQ]; |
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/* Local registers per output pin */
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IRQ_dst_t dst[MAX_CPU]; |
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int nb_cpus;
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/* Timer registers */
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struct {
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uint32_t ticc; /* Global timer current count register */
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uint32_t tibc; /* Global timer base count register */
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} timers[MAX_TMR]; |
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#if MAX_DBL > 0 |
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/* Doorbell registers */
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uint32_t dar; /* Doorbell activate register */
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struct {
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uint32_t dmr; /* Doorbell messaging register */
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} doorbells[MAX_DBL]; |
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#endif
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#if MAX_MBX > 0 |
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/* Mailbox registers */
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struct {
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uint32_t mbr; /* Mailbox register */
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} mailboxes[MAX_MAILBOXES]; |
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#endif
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/* IRQ out is used when in bypass mode (not implemented) */
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qemu_irq irq_out; |
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int max_irq;
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int irq_ipi0;
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int irq_tim0;
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void (*reset) (void *); |
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void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); |
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} openpic_t; |
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static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
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{ |
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set_bit(q->queue, n_IRQ); |
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} |
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static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
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{ |
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reset_bit(q->queue, n_IRQ); |
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} |
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static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
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{ |
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return test_bit(q->queue, n_IRQ);
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} |
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static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
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{ |
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int next, i;
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int priority;
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next = -1;
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priority = -1;
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for (i = 0; i < opp->max_irq; i++) { |
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if (IRQ_testbit(q, i)) {
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DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
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i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
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if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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next = i; |
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priority = IPVP_PRIORITY(opp->src[i].ipvp); |
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} |
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} |
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} |
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q->next = next; |
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q->priority = priority; |
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} |
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static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
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{ |
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if (q->next == -1) { |
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/* XXX: optimize */
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IRQ_check(opp, q); |
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} |
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return q->next;
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} |
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static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
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{ |
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IRQ_dst_t *dst; |
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IRQ_src_t *src; |
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int priority;
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dst = &opp->dst[n_CPU]; |
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src = &opp->src[n_IRQ]; |
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priority = IPVP_PRIORITY(src->ipvp); |
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if (priority <= dst->pctp) {
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/* Too low priority */
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DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
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__func__, n_IRQ, n_CPU); |
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return;
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} |
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if (IRQ_testbit(&dst->raised, n_IRQ)) {
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/* Interrupt miss */
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DPRINTF("%s: IRQ %d was missed on CPU %d\n",
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__func__, n_IRQ, n_CPU); |
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return;
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} |
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set_bit(&src->ipvp, IPVP_ACTIVITY); |
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IRQ_setbit(&dst->raised, n_IRQ); |
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if (priority < dst->raised.priority) {
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/* An higher priority IRQ is already raised */
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DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
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__func__, n_IRQ, dst->raised.next, n_CPU); |
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return;
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} |
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IRQ_get_next(opp, &dst->raised); |
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if (IRQ_get_next(opp, &dst->servicing) != -1 && |
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priority <= dst->servicing.priority) { |
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DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
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__func__, n_IRQ, dst->servicing.next, n_CPU); |
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/* Already servicing a higher priority IRQ */
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return;
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} |
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DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
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opp->irq_raise(opp, n_CPU, src); |
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} |
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/* update pic state because registers for n_IRQ have changed value */
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static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
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{ |
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IRQ_src_t *src; |
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int i;
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src = &opp->src[n_IRQ]; |
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if (!src->pending) {
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/* no irq pending */
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DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
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return;
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} |
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if (test_bit(&src->ipvp, IPVP_MASK)) {
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/* Interrupt source is disabled */
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DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
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return;
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} |
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if (IPVP_PRIORITY(src->ipvp) == 0) { |
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/* Priority set to zero */
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DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
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return;
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} |
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if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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/* IRQ already active */
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DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
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return;
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} |
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if (src->ide == 0x00000000) { |
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/* No target */
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DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
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return;
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} |
380 |
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if (src->ide == (1 << src->last_cpu)) { |
382 |
/* Only one CPU is allowed to receive this IRQ */
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IRQ_local_pipe(opp, src->last_cpu, n_IRQ); |
384 |
} else if (!test_bit(&src->ipvp, IPVP_MODE)) { |
385 |
/* Directed delivery mode */
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for (i = 0; i < opp->nb_cpus; i++) { |
387 |
if (test_bit(&src->ide, i))
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IRQ_local_pipe(opp, i, n_IRQ); |
389 |
} |
390 |
} else {
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/* Distributed delivery mode */
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for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
393 |
if (i == opp->nb_cpus)
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i = 0;
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if (test_bit(&src->ide, i)) {
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IRQ_local_pipe(opp, i, n_IRQ); |
397 |
src->last_cpu = i; |
398 |
break;
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} |
400 |
} |
401 |
} |
402 |
} |
403 |
|
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static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
405 |
{ |
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openpic_t *opp = opaque; |
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IRQ_src_t *src; |
408 |
|
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src = &opp->src[n_IRQ]; |
410 |
DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
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n_IRQ, level, src->ipvp); |
412 |
if (test_bit(&src->ipvp, IPVP_SENSE)) {
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/* level-sensitive irq */
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src->pending = level; |
415 |
if (!level)
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reset_bit(&src->ipvp, IPVP_ACTIVITY); |
417 |
} else {
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/* edge-sensitive irq */
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if (level)
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src->pending = 1;
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} |
422 |
openpic_update_irq(opp, n_IRQ); |
423 |
} |
424 |
|
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static void openpic_reset (void *opaque) |
426 |
{ |
427 |
openpic_t *opp = (openpic_t *)opaque; |
428 |
int i;
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429 |
|
430 |
opp->glbc = 0x80000000;
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/* Initialise controller registers */
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opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
433 |
opp->veni = VENI; |
434 |
opp->pint = 0x00000000;
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opp->spve = 0x000000FF;
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436 |
opp->tifr = 0x003F7A00;
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/* ? */
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opp->micr = 0x00000000;
|
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/* Initialise IRQ sources */
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for (i = 0; i < opp->max_irq; i++) { |
441 |
opp->src[i].ipvp = 0xA0000000;
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opp->src[i].ide = 0x00000000;
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} |
444 |
/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) { |
446 |
opp->dst[i].pctp = 0x0000000F;
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opp->dst[i].pcsr = 0x00000000;
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memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
449 |
opp->dst[i].raised.next = -1;
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memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
451 |
opp->dst[i].servicing.next = -1;
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} |
453 |
/* Initialise timers */
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for (i = 0; i < MAX_TMR; i++) { |
455 |
opp->timers[i].ticc = 0x00000000;
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opp->timers[i].tibc = 0x80000000;
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} |
458 |
/* Initialise doorbells */
|
459 |
#if MAX_DBL > 0 |
460 |
opp->dar = 0x00000000;
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461 |
for (i = 0; i < MAX_DBL; i++) { |
462 |
opp->doorbells[i].dmr = 0x00000000;
|
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} |
464 |
#endif
|
465 |
/* Initialise mailboxes */
|
466 |
#if MAX_MBX > 0 |
467 |
for (i = 0; i < MAX_MBX; i++) { /* ? */ |
468 |
opp->mailboxes[i].mbr = 0x00000000;
|
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} |
470 |
#endif
|
471 |
/* Go out of RESET state */
|
472 |
opp->glbc = 0x00000000;
|
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} |
474 |
|
475 |
static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
476 |
{ |
477 |
uint32_t retval; |
478 |
|
479 |
switch (reg) {
|
480 |
case IRQ_IPVP:
|
481 |
retval = opp->src[n_IRQ].ipvp; |
482 |
break;
|
483 |
case IRQ_IDE:
|
484 |
retval = opp->src[n_IRQ].ide; |
485 |
break;
|
486 |
} |
487 |
|
488 |
return retval;
|
489 |
} |
490 |
|
491 |
static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
492 |
uint32_t reg, uint32_t val) |
493 |
{ |
494 |
uint32_t tmp; |
495 |
|
496 |
switch (reg) {
|
497 |
case IRQ_IPVP:
|
498 |
/* NOTE: not fully accurate for special IRQs, but simple and
|
499 |
sufficient */
|
500 |
/* ACTIVITY bit is read-only */
|
501 |
opp->src[n_IRQ].ipvp = |
502 |
(opp->src[n_IRQ].ipvp & 0x40000000) |
|
503 |
(val & 0x800F00FF);
|
504 |
openpic_update_irq(opp, n_IRQ); |
505 |
DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
|
506 |
n_IRQ, val, opp->src[n_IRQ].ipvp); |
507 |
break;
|
508 |
case IRQ_IDE:
|
509 |
tmp = val & 0xC0000000;
|
510 |
tmp |= val & ((1 << MAX_CPU) - 1); |
511 |
opp->src[n_IRQ].ide = tmp; |
512 |
DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
513 |
break;
|
514 |
} |
515 |
} |
516 |
|
517 |
#if 0 // Code provision for Intel model
|
518 |
#if MAX_DBL > 0
|
519 |
static uint32_t read_doorbell_register (openpic_t *opp,
|
520 |
int n_dbl, uint32_t offset)
|
521 |
{
|
522 |
uint32_t retval;
|
523 |
|
524 |
switch (offset) {
|
525 |
case DBL_IPVP_OFFSET:
|
526 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
|
527 |
break;
|
528 |
case DBL_IDE_OFFSET:
|
529 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
|
530 |
break;
|
531 |
case DBL_DMR_OFFSET:
|
532 |
retval = opp->doorbells[n_dbl].dmr;
|
533 |
break;
|
534 |
}
|
535 |
|
536 |
return retval;
|
537 |
}
|
538 |
|
539 |
static void write_doorbell_register (penpic_t *opp, int n_dbl,
|
540 |
uint32_t offset, uint32_t value)
|
541 |
{
|
542 |
switch (offset) {
|
543 |
case DBL_IVPR_OFFSET:
|
544 |
write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
|
545 |
break;
|
546 |
case DBL_IDE_OFFSET:
|
547 |
write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
|
548 |
break;
|
549 |
case DBL_DMR_OFFSET:
|
550 |
opp->doorbells[n_dbl].dmr = value;
|
551 |
break;
|
552 |
}
|
553 |
}
|
554 |
#endif
|
555 |
|
556 |
#if MAX_MBX > 0 |
557 |
static uint32_t read_mailbox_register (openpic_t *opp,
|
558 |
int n_mbx, uint32_t offset)
|
559 |
{ |
560 |
uint32_t retval; |
561 |
|
562 |
switch (offset) {
|
563 |
case MBX_MBR_OFFSET:
|
564 |
retval = opp->mailboxes[n_mbx].mbr; |
565 |
break;
|
566 |
case MBX_IVPR_OFFSET:
|
567 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
568 |
break;
|
569 |
case MBX_DMR_OFFSET:
|
570 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
571 |
break;
|
572 |
} |
573 |
|
574 |
return retval;
|
575 |
} |
576 |
|
577 |
static void write_mailbox_register (openpic_t *opp, int n_mbx, |
578 |
uint32_t address, uint32_t value) |
579 |
{ |
580 |
switch (offset) {
|
581 |
case MBX_MBR_OFFSET:
|
582 |
opp->mailboxes[n_mbx].mbr = value; |
583 |
break;
|
584 |
case MBX_IVPR_OFFSET:
|
585 |
write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
586 |
break;
|
587 |
case MBX_DMR_OFFSET:
|
588 |
write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
589 |
break;
|
590 |
} |
591 |
} |
592 |
#endif
|
593 |
#endif /* 0 : Code provision for Intel model */ |
594 |
|
595 |
static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
596 |
{ |
597 |
openpic_t *opp = opaque; |
598 |
IRQ_dst_t *dst; |
599 |
int idx;
|
600 |
|
601 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
602 |
if (addr & 0xF) |
603 |
return;
|
604 |
switch (addr) {
|
605 |
case 0x40: |
606 |
case 0x50: |
607 |
case 0x60: |
608 |
case 0x70: |
609 |
case 0x80: |
610 |
case 0x90: |
611 |
case 0xA0: |
612 |
case 0xB0: |
613 |
openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); |
614 |
break;
|
615 |
case 0x1000: /* FREP */ |
616 |
break;
|
617 |
case 0x1020: /* GLBC */ |
618 |
if (val & 0x80000000 && opp->reset) |
619 |
opp->reset(opp); |
620 |
opp->glbc = val & ~0x80000000;
|
621 |
break;
|
622 |
case 0x1080: /* VENI */ |
623 |
break;
|
624 |
case 0x1090: /* PINT */ |
625 |
for (idx = 0; idx < opp->nb_cpus; idx++) { |
626 |
if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { |
627 |
DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
|
628 |
dst = &opp->dst[idx]; |
629 |
qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
630 |
} else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { |
631 |
DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
|
632 |
dst = &opp->dst[idx]; |
633 |
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
634 |
} |
635 |
} |
636 |
opp->pint = val; |
637 |
break;
|
638 |
case 0x10A0: /* IPI_IPVP */ |
639 |
case 0x10B0: |
640 |
case 0x10C0: |
641 |
case 0x10D0: |
642 |
{ |
643 |
int idx;
|
644 |
idx = (addr - 0x10A0) >> 4; |
645 |
write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val); |
646 |
} |
647 |
break;
|
648 |
case 0x10E0: /* SPVE */ |
649 |
opp->spve = val & 0x000000FF;
|
650 |
break;
|
651 |
case 0x10F0: /* TIFR */ |
652 |
opp->tifr = val; |
653 |
break;
|
654 |
default:
|
655 |
break;
|
656 |
} |
657 |
} |
658 |
|
659 |
static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr) |
660 |
{ |
661 |
openpic_t *opp = opaque; |
662 |
uint32_t retval; |
663 |
|
664 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
665 |
retval = 0xFFFFFFFF;
|
666 |
if (addr & 0xF) |
667 |
return retval;
|
668 |
switch (addr) {
|
669 |
case 0x1000: /* FREP */ |
670 |
retval = opp->frep; |
671 |
break;
|
672 |
case 0x1020: /* GLBC */ |
673 |
retval = opp->glbc; |
674 |
break;
|
675 |
case 0x1080: /* VENI */ |
676 |
retval = opp->veni; |
677 |
break;
|
678 |
case 0x1090: /* PINT */ |
679 |
retval = 0x00000000;
|
680 |
break;
|
681 |
case 0x40: |
682 |
case 0x50: |
683 |
case 0x60: |
684 |
case 0x70: |
685 |
case 0x80: |
686 |
case 0x90: |
687 |
case 0xA0: |
688 |
case 0xB0: |
689 |
retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
690 |
break;
|
691 |
case 0x10A0: /* IPI_IPVP */ |
692 |
case 0x10B0: |
693 |
case 0x10C0: |
694 |
case 0x10D0: |
695 |
{ |
696 |
int idx;
|
697 |
idx = (addr - 0x10A0) >> 4; |
698 |
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP); |
699 |
} |
700 |
break;
|
701 |
case 0x10E0: /* SPVE */ |
702 |
retval = opp->spve; |
703 |
break;
|
704 |
case 0x10F0: /* TIFR */ |
705 |
retval = opp->tifr; |
706 |
break;
|
707 |
default:
|
708 |
break;
|
709 |
} |
710 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
711 |
|
712 |
return retval;
|
713 |
} |
714 |
|
715 |
static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
716 |
{ |
717 |
openpic_t *opp = opaque; |
718 |
int idx;
|
719 |
|
720 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
721 |
if (addr & 0xF) |
722 |
return;
|
723 |
addr -= 0x1100;
|
724 |
addr &= 0xFFFF;
|
725 |
idx = (addr & 0xFFF0) >> 6; |
726 |
addr = addr & 0x30;
|
727 |
switch (addr) {
|
728 |
case 0x00: /* TICC */ |
729 |
break;
|
730 |
case 0x10: /* TIBC */ |
731 |
if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
732 |
(val & 0x80000000) == 0 && |
733 |
(opp->timers[idx].tibc & 0x80000000) != 0) |
734 |
opp->timers[idx].ticc &= ~0x80000000;
|
735 |
opp->timers[idx].tibc = val; |
736 |
break;
|
737 |
case 0x20: /* TIVP */ |
738 |
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val); |
739 |
break;
|
740 |
case 0x30: /* TIDE */ |
741 |
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val); |
742 |
break;
|
743 |
} |
744 |
} |
745 |
|
746 |
static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
747 |
{ |
748 |
openpic_t *opp = opaque; |
749 |
uint32_t retval; |
750 |
int idx;
|
751 |
|
752 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
753 |
retval = 0xFFFFFFFF;
|
754 |
if (addr & 0xF) |
755 |
return retval;
|
756 |
addr -= 0x1100;
|
757 |
addr &= 0xFFFF;
|
758 |
idx = (addr & 0xFFF0) >> 6; |
759 |
addr = addr & 0x30;
|
760 |
switch (addr) {
|
761 |
case 0x00: /* TICC */ |
762 |
retval = opp->timers[idx].ticc; |
763 |
break;
|
764 |
case 0x10: /* TIBC */ |
765 |
retval = opp->timers[idx].tibc; |
766 |
break;
|
767 |
case 0x20: /* TIPV */ |
768 |
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP); |
769 |
break;
|
770 |
case 0x30: /* TIDE */ |
771 |
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE); |
772 |
break;
|
773 |
} |
774 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
775 |
|
776 |
return retval;
|
777 |
} |
778 |
|
779 |
static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
780 |
{ |
781 |
openpic_t *opp = opaque; |
782 |
int idx;
|
783 |
|
784 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
785 |
if (addr & 0xF) |
786 |
return;
|
787 |
addr = addr & 0xFFF0;
|
788 |
idx = addr >> 5;
|
789 |
if (addr & 0x10) { |
790 |
/* EXDE / IFEDE / IEEDE */
|
791 |
write_IRQreg(opp, idx, IRQ_IDE, val); |
792 |
} else {
|
793 |
/* EXVP / IFEVP / IEEVP */
|
794 |
write_IRQreg(opp, idx, IRQ_IPVP, val); |
795 |
} |
796 |
} |
797 |
|
798 |
static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
799 |
{ |
800 |
openpic_t *opp = opaque; |
801 |
uint32_t retval; |
802 |
int idx;
|
803 |
|
804 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
805 |
retval = 0xFFFFFFFF;
|
806 |
if (addr & 0xF) |
807 |
return retval;
|
808 |
addr = addr & 0xFFF0;
|
809 |
idx = addr >> 5;
|
810 |
if (addr & 0x10) { |
811 |
/* EXDE / IFEDE / IEEDE */
|
812 |
retval = read_IRQreg(opp, idx, IRQ_IDE); |
813 |
} else {
|
814 |
/* EXVP / IFEVP / IEEVP */
|
815 |
retval = read_IRQreg(opp, idx, IRQ_IPVP); |
816 |
} |
817 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
818 |
|
819 |
return retval;
|
820 |
} |
821 |
|
822 |
static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr, |
823 |
uint32_t val, int idx)
|
824 |
{ |
825 |
openpic_t *opp = opaque; |
826 |
IRQ_src_t *src; |
827 |
IRQ_dst_t *dst; |
828 |
int s_IRQ, n_IRQ;
|
829 |
|
830 |
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx, |
831 |
addr, val); |
832 |
if (addr & 0xF) |
833 |
return;
|
834 |
dst = &opp->dst[idx]; |
835 |
addr &= 0xFF0;
|
836 |
switch (addr) {
|
837 |
#if MAX_IPI > 0 |
838 |
case 0x40: /* IPIDR */ |
839 |
case 0x50: |
840 |
case 0x60: |
841 |
case 0x70: |
842 |
idx = (addr - 0x40) >> 4; |
843 |
write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val); |
844 |
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
|
845 |
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
|
846 |
break;
|
847 |
#endif
|
848 |
case 0x80: /* PCTP */ |
849 |
dst->pctp = val & 0x0000000F;
|
850 |
break;
|
851 |
case 0x90: /* WHOAMI */ |
852 |
/* Read-only register */
|
853 |
break;
|
854 |
case 0xA0: /* PIAC */ |
855 |
/* Read-only register */
|
856 |
break;
|
857 |
case 0xB0: /* PEOI */ |
858 |
DPRINTF("PEOI\n");
|
859 |
s_IRQ = IRQ_get_next(opp, &dst->servicing); |
860 |
IRQ_resetbit(&dst->servicing, s_IRQ); |
861 |
dst->servicing.next = -1;
|
862 |
/* Set up next servicing IRQ */
|
863 |
s_IRQ = IRQ_get_next(opp, &dst->servicing); |
864 |
/* Check queued interrupts. */
|
865 |
n_IRQ = IRQ_get_next(opp, &dst->raised); |
866 |
src = &opp->src[n_IRQ]; |
867 |
if (n_IRQ != -1 && |
868 |
(s_IRQ == -1 ||
|
869 |
IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { |
870 |
DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
871 |
idx, n_IRQ); |
872 |
opp->irq_raise(opp, idx, src); |
873 |
} |
874 |
break;
|
875 |
default:
|
876 |
break;
|
877 |
} |
878 |
} |
879 |
|
880 |
static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val) |
881 |
{ |
882 |
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); |
883 |
} |
884 |
|
885 |
static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr, |
886 |
int idx)
|
887 |
{ |
888 |
openpic_t *opp = opaque; |
889 |
IRQ_src_t *src; |
890 |
IRQ_dst_t *dst; |
891 |
uint32_t retval; |
892 |
int n_IRQ;
|
893 |
|
894 |
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr); |
895 |
retval = 0xFFFFFFFF;
|
896 |
if (addr & 0xF) |
897 |
return retval;
|
898 |
dst = &opp->dst[idx]; |
899 |
addr &= 0xFF0;
|
900 |
switch (addr) {
|
901 |
case 0x80: /* PCTP */ |
902 |
retval = dst->pctp; |
903 |
break;
|
904 |
case 0x90: /* WHOAMI */ |
905 |
retval = idx; |
906 |
break;
|
907 |
case 0xA0: /* PIAC */ |
908 |
DPRINTF("Lower OpenPIC INT output\n");
|
909 |
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
910 |
n_IRQ = IRQ_get_next(opp, &dst->raised); |
911 |
DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
912 |
if (n_IRQ == -1) { |
913 |
/* No more interrupt pending */
|
914 |
retval = IPVP_VECTOR(opp->spve); |
915 |
} else {
|
916 |
src = &opp->src[n_IRQ]; |
917 |
if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
|
918 |
!(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
919 |
/* - Spurious level-sensitive IRQ
|
920 |
* - Priorities has been changed
|
921 |
* and the pending IRQ isn't allowed anymore
|
922 |
*/
|
923 |
reset_bit(&src->ipvp, IPVP_ACTIVITY); |
924 |
retval = IPVP_VECTOR(opp->spve); |
925 |
} else {
|
926 |
/* IRQ enter servicing state */
|
927 |
IRQ_setbit(&dst->servicing, n_IRQ); |
928 |
retval = IPVP_VECTOR(src->ipvp); |
929 |
} |
930 |
IRQ_resetbit(&dst->raised, n_IRQ); |
931 |
dst->raised.next = -1;
|
932 |
if (!test_bit(&src->ipvp, IPVP_SENSE)) {
|
933 |
/* edge-sensitive IRQ */
|
934 |
reset_bit(&src->ipvp, IPVP_ACTIVITY); |
935 |
src->pending = 0;
|
936 |
} |
937 |
} |
938 |
break;
|
939 |
case 0xB0: /* PEOI */ |
940 |
retval = 0;
|
941 |
break;
|
942 |
#if MAX_IPI > 0 |
943 |
case 0x40: /* IDE */ |
944 |
case 0x50: |
945 |
idx = (addr - 0x40) >> 4; |
946 |
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE); |
947 |
break;
|
948 |
#endif
|
949 |
default:
|
950 |
break;
|
951 |
} |
952 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
953 |
|
954 |
return retval;
|
955 |
} |
956 |
|
957 |
static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr) |
958 |
{ |
959 |
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); |
960 |
} |
961 |
|
962 |
static void openpic_buggy_write (void *opaque, |
963 |
target_phys_addr_t addr, uint32_t val) |
964 |
{ |
965 |
printf("Invalid OPENPIC write access !\n");
|
966 |
} |
967 |
|
968 |
static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
969 |
{ |
970 |
printf("Invalid OPENPIC read access !\n");
|
971 |
|
972 |
return -1; |
973 |
} |
974 |
|
975 |
static void openpic_writel (void *opaque, |
976 |
target_phys_addr_t addr, uint32_t val) |
977 |
{ |
978 |
openpic_t *opp = opaque; |
979 |
|
980 |
addr &= 0x3FFFF;
|
981 |
DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
982 |
if (addr < 0x1100) { |
983 |
/* Global registers */
|
984 |
openpic_gbl_write(opp, addr, val); |
985 |
} else if (addr < 0x10000) { |
986 |
/* Timers registers */
|
987 |
openpic_timer_write(opp, addr, val); |
988 |
} else if (addr < 0x20000) { |
989 |
/* Source registers */
|
990 |
openpic_src_write(opp, addr, val); |
991 |
} else {
|
992 |
/* CPU registers */
|
993 |
openpic_cpu_write(opp, addr, val); |
994 |
} |
995 |
} |
996 |
|
997 |
static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
998 |
{ |
999 |
openpic_t *opp = opaque; |
1000 |
uint32_t retval; |
1001 |
|
1002 |
addr &= 0x3FFFF;
|
1003 |
DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
1004 |
if (addr < 0x1100) { |
1005 |
/* Global registers */
|
1006 |
retval = openpic_gbl_read(opp, addr); |
1007 |
} else if (addr < 0x10000) { |
1008 |
/* Timers registers */
|
1009 |
retval = openpic_timer_read(opp, addr); |
1010 |
} else if (addr < 0x20000) { |
1011 |
/* Source registers */
|
1012 |
retval = openpic_src_read(opp, addr); |
1013 |
} else {
|
1014 |
/* CPU registers */
|
1015 |
retval = openpic_cpu_read(opp, addr); |
1016 |
} |
1017 |
|
1018 |
return retval;
|
1019 |
} |
1020 |
|
1021 |
static uint64_t openpic_read(void *opaque, target_phys_addr_t addr, |
1022 |
unsigned size)
|
1023 |
{ |
1024 |
openpic_t *opp = opaque; |
1025 |
|
1026 |
switch (size) {
|
1027 |
case 4: return openpic_readl(opp, addr); |
1028 |
default: return openpic_buggy_read(opp, addr); |
1029 |
} |
1030 |
} |
1031 |
|
1032 |
static void openpic_write(void *opaque, target_phys_addr_t addr, |
1033 |
uint64_t data, unsigned size)
|
1034 |
{ |
1035 |
openpic_t *opp = opaque; |
1036 |
|
1037 |
switch (size) {
|
1038 |
case 4: return openpic_writel(opp, addr, data); |
1039 |
default: return openpic_buggy_write(opp, addr, data); |
1040 |
} |
1041 |
} |
1042 |
|
1043 |
static const MemoryRegionOps openpic_ops = { |
1044 |
.read = openpic_read, |
1045 |
.write = openpic_write, |
1046 |
.endianness = DEVICE_LITTLE_ENDIAN, |
1047 |
}; |
1048 |
|
1049 |
static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1050 |
{ |
1051 |
unsigned int i; |
1052 |
|
1053 |
for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1054 |
qemu_put_be32s(f, &q->queue[i]); |
1055 |
|
1056 |
qemu_put_sbe32s(f, &q->next); |
1057 |
qemu_put_sbe32s(f, &q->priority); |
1058 |
} |
1059 |
|
1060 |
static void openpic_save(QEMUFile* f, void *opaque) |
1061 |
{ |
1062 |
openpic_t *opp = (openpic_t *)opaque; |
1063 |
unsigned int i; |
1064 |
|
1065 |
qemu_put_be32s(f, &opp->frep); |
1066 |
qemu_put_be32s(f, &opp->glbc); |
1067 |
qemu_put_be32s(f, &opp->micr); |
1068 |
qemu_put_be32s(f, &opp->veni); |
1069 |
qemu_put_be32s(f, &opp->pint); |
1070 |
qemu_put_be32s(f, &opp->spve); |
1071 |
qemu_put_be32s(f, &opp->tifr); |
1072 |
|
1073 |
for (i = 0; i < opp->max_irq; i++) { |
1074 |
qemu_put_be32s(f, &opp->src[i].ipvp); |
1075 |
qemu_put_be32s(f, &opp->src[i].ide); |
1076 |
qemu_put_sbe32s(f, &opp->src[i].type); |
1077 |
qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1078 |
qemu_put_sbe32s(f, &opp->src[i].pending); |
1079 |
} |
1080 |
|
1081 |
qemu_put_sbe32s(f, &opp->nb_cpus); |
1082 |
|
1083 |
for (i = 0; i < opp->nb_cpus; i++) { |
1084 |
qemu_put_be32s(f, &opp->dst[i].tfrr); |
1085 |
qemu_put_be32s(f, &opp->dst[i].pctp); |
1086 |
qemu_put_be32s(f, &opp->dst[i].pcsr); |
1087 |
openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1088 |
openpic_save_IRQ_queue(f, &opp->dst[i].servicing); |
1089 |
} |
1090 |
|
1091 |
for (i = 0; i < MAX_TMR; i++) { |
1092 |
qemu_put_be32s(f, &opp->timers[i].ticc); |
1093 |
qemu_put_be32s(f, &opp->timers[i].tibc); |
1094 |
} |
1095 |
|
1096 |
#if MAX_DBL > 0 |
1097 |
qemu_put_be32s(f, &opp->dar); |
1098 |
|
1099 |
for (i = 0; i < MAX_DBL; i++) { |
1100 |
qemu_put_be32s(f, &opp->doorbells[i].dmr); |
1101 |
} |
1102 |
#endif
|
1103 |
|
1104 |
#if MAX_MBX > 0 |
1105 |
for (i = 0; i < MAX_MAILBOXES; i++) { |
1106 |
qemu_put_be32s(f, &opp->mailboxes[i].mbr); |
1107 |
} |
1108 |
#endif
|
1109 |
|
1110 |
pci_device_save(&opp->pci_dev, f); |
1111 |
} |
1112 |
|
1113 |
static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
1114 |
{ |
1115 |
unsigned int i; |
1116 |
|
1117 |
for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) |
1118 |
qemu_get_be32s(f, &q->queue[i]); |
1119 |
|
1120 |
qemu_get_sbe32s(f, &q->next); |
1121 |
qemu_get_sbe32s(f, &q->priority); |
1122 |
} |
1123 |
|
1124 |
static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
1125 |
{ |
1126 |
openpic_t *opp = (openpic_t *)opaque; |
1127 |
unsigned int i; |
1128 |
|
1129 |
if (version_id != 1) |
1130 |
return -EINVAL;
|
1131 |
|
1132 |
qemu_get_be32s(f, &opp->frep); |
1133 |
qemu_get_be32s(f, &opp->glbc); |
1134 |
qemu_get_be32s(f, &opp->micr); |
1135 |
qemu_get_be32s(f, &opp->veni); |
1136 |
qemu_get_be32s(f, &opp->pint); |
1137 |
qemu_get_be32s(f, &opp->spve); |
1138 |
qemu_get_be32s(f, &opp->tifr); |
1139 |
|
1140 |
for (i = 0; i < opp->max_irq; i++) { |
1141 |
qemu_get_be32s(f, &opp->src[i].ipvp); |
1142 |
qemu_get_be32s(f, &opp->src[i].ide); |
1143 |
qemu_get_sbe32s(f, &opp->src[i].type); |
1144 |
qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1145 |
qemu_get_sbe32s(f, &opp->src[i].pending); |
1146 |
} |
1147 |
|
1148 |
qemu_get_sbe32s(f, &opp->nb_cpus); |
1149 |
|
1150 |
for (i = 0; i < opp->nb_cpus; i++) { |
1151 |
qemu_get_be32s(f, &opp->dst[i].tfrr); |
1152 |
qemu_get_be32s(f, &opp->dst[i].pctp); |
1153 |
qemu_get_be32s(f, &opp->dst[i].pcsr); |
1154 |
openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1155 |
openpic_load_IRQ_queue(f, &opp->dst[i].servicing); |
1156 |
} |
1157 |
|
1158 |
for (i = 0; i < MAX_TMR; i++) { |
1159 |
qemu_get_be32s(f, &opp->timers[i].ticc); |
1160 |
qemu_get_be32s(f, &opp->timers[i].tibc); |
1161 |
} |
1162 |
|
1163 |
#if MAX_DBL > 0 |
1164 |
qemu_get_be32s(f, &opp->dar); |
1165 |
|
1166 |
for (i = 0; i < MAX_DBL; i++) { |
1167 |
qemu_get_be32s(f, &opp->doorbells[i].dmr); |
1168 |
} |
1169 |
#endif
|
1170 |
|
1171 |
#if MAX_MBX > 0 |
1172 |
for (i = 0; i < MAX_MAILBOXES; i++) { |
1173 |
qemu_get_be32s(f, &opp->mailboxes[i].mbr); |
1174 |
} |
1175 |
#endif
|
1176 |
|
1177 |
return pci_device_load(&opp->pci_dev, f);
|
1178 |
} |
1179 |
|
1180 |
static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) |
1181 |
{ |
1182 |
qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1183 |
} |
1184 |
|
1185 |
qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
|
1186 |
qemu_irq **irqs, qemu_irq irq_out) |
1187 |
{ |
1188 |
openpic_t *opp; |
1189 |
uint8_t *pci_conf; |
1190 |
int i, m;
|
1191 |
|
1192 |
/* XXX: for now, only one CPU is supported */
|
1193 |
if (nb_cpus != 1) |
1194 |
return NULL; |
1195 |
if (bus) {
|
1196 |
opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), |
1197 |
-1, NULL, NULL); |
1198 |
pci_conf = opp->pci_dev.config; |
1199 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
1200 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2); |
1201 |
pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
|
1202 |
pci_conf[0x3d] = 0x00; // no interrupt pin |
1203 |
|
1204 |
memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000); |
1205 |
#if 0 // Don't implement ISU for now
|
1206 |
opp_io_memory = cpu_register_io_memory(openpic_src_read,
|
1207 |
openpic_src_write, NULL
|
1208 |
DEVICE_NATIVE_ENDIAN);
|
1209 |
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
|
1210 |
opp_io_memory);
|
1211 |
#endif
|
1212 |
|
1213 |
/* Register I/O spaces */
|
1214 |
pci_register_bar(&opp->pci_dev, 0,
|
1215 |
PCI_BASE_ADDRESS_SPACE_MEMORY, &opp->mem); |
1216 |
} else {
|
1217 |
opp = g_malloc0(sizeof(openpic_t));
|
1218 |
memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000); |
1219 |
} |
1220 |
|
1221 |
// isu_base &= 0xFFFC0000;
|
1222 |
opp->nb_cpus = nb_cpus; |
1223 |
opp->max_irq = OPENPIC_MAX_IRQ; |
1224 |
opp->irq_ipi0 = OPENPIC_IRQ_IPI0; |
1225 |
opp->irq_tim0 = OPENPIC_IRQ_TIM0; |
1226 |
/* Set IRQ types */
|
1227 |
for (i = 0; i < OPENPIC_EXT_IRQ; i++) { |
1228 |
opp->src[i].type = IRQ_EXTERNAL; |
1229 |
} |
1230 |
for (; i < OPENPIC_IRQ_TIM0; i++) {
|
1231 |
opp->src[i].type = IRQ_SPECIAL; |
1232 |
} |
1233 |
#if MAX_IPI > 0 |
1234 |
m = OPENPIC_IRQ_IPI0; |
1235 |
#else
|
1236 |
m = OPENPIC_IRQ_DBL0; |
1237 |
#endif
|
1238 |
for (; i < m; i++) {
|
1239 |
opp->src[i].type = IRQ_TIMER; |
1240 |
} |
1241 |
for (; i < OPENPIC_MAX_IRQ; i++) {
|
1242 |
opp->src[i].type = IRQ_INTERNAL; |
1243 |
} |
1244 |
for (i = 0; i < nb_cpus; i++) |
1245 |
opp->dst[i].irqs = irqs[i]; |
1246 |
opp->irq_out = irq_out; |
1247 |
|
1248 |
register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2, |
1249 |
openpic_save, openpic_load, opp); |
1250 |
qemu_register_reset(openpic_reset, opp); |
1251 |
|
1252 |
opp->irq_raise = openpic_irq_raise; |
1253 |
opp->reset = openpic_reset; |
1254 |
|
1255 |
if (pmem)
|
1256 |
*pmem = &opp->mem; |
1257 |
|
1258 |
return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
|
1259 |
} |
1260 |
|
1261 |
static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) |
1262 |
{ |
1263 |
int n_ci = IDR_CI0 - n_CPU;
|
1264 |
|
1265 |
if(test_bit(&src->ide, n_ci)) {
|
1266 |
qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); |
1267 |
} |
1268 |
else {
|
1269 |
qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
1270 |
} |
1271 |
} |
1272 |
|
1273 |
static void mpic_reset (void *opaque) |
1274 |
{ |
1275 |
openpic_t *mpp = (openpic_t *)opaque; |
1276 |
int i;
|
1277 |
|
1278 |
mpp->glbc = 0x80000000;
|
1279 |
/* Initialise controller registers */
|
1280 |
mpp->frep = 0x004f0002;
|
1281 |
mpp->veni = VENI; |
1282 |
mpp->pint = 0x00000000;
|
1283 |
mpp->spve = 0x0000FFFF;
|
1284 |
/* Initialise IRQ sources */
|
1285 |
for (i = 0; i < mpp->max_irq; i++) { |
1286 |
mpp->src[i].ipvp = 0x80800000;
|
1287 |
mpp->src[i].ide = 0x00000001;
|
1288 |
} |
1289 |
/* Initialise IRQ destinations */
|
1290 |
for (i = 0; i < MAX_CPU; i++) { |
1291 |
mpp->dst[i].pctp = 0x0000000F;
|
1292 |
mpp->dst[i].tfrr = 0x00000000;
|
1293 |
memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
1294 |
mpp->dst[i].raised.next = -1;
|
1295 |
memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
1296 |
mpp->dst[i].servicing.next = -1;
|
1297 |
} |
1298 |
/* Initialise timers */
|
1299 |
for (i = 0; i < MAX_TMR; i++) { |
1300 |
mpp->timers[i].ticc = 0x00000000;
|
1301 |
mpp->timers[i].tibc = 0x80000000;
|
1302 |
} |
1303 |
/* Go out of RESET state */
|
1304 |
mpp->glbc = 0x00000000;
|
1305 |
} |
1306 |
|
1307 |
static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val) |
1308 |
{ |
1309 |
openpic_t *mpp = opaque; |
1310 |
int idx, cpu;
|
1311 |
|
1312 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1313 |
if (addr & 0xF) |
1314 |
return;
|
1315 |
addr &= 0xFFFF;
|
1316 |
cpu = addr >> 12;
|
1317 |
idx = (addr >> 6) & 0x3; |
1318 |
switch (addr & 0x30) { |
1319 |
case 0x00: /* gtccr */ |
1320 |
break;
|
1321 |
case 0x10: /* gtbcr */ |
1322 |
if ((mpp->timers[idx].ticc & 0x80000000) != 0 && |
1323 |
(val & 0x80000000) == 0 && |
1324 |
(mpp->timers[idx].tibc & 0x80000000) != 0) |
1325 |
mpp->timers[idx].ticc &= ~0x80000000;
|
1326 |
mpp->timers[idx].tibc = val; |
1327 |
break;
|
1328 |
case 0x20: /* GTIVPR */ |
1329 |
write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP, val); |
1330 |
break;
|
1331 |
case 0x30: /* GTIDR & TFRR */ |
1332 |
if ((addr & 0xF0) == 0xF0) |
1333 |
mpp->dst[cpu].tfrr = val; |
1334 |
else
|
1335 |
write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE, val); |
1336 |
break;
|
1337 |
} |
1338 |
} |
1339 |
|
1340 |
static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr) |
1341 |
{ |
1342 |
openpic_t *mpp = opaque; |
1343 |
uint32_t retval; |
1344 |
int idx, cpu;
|
1345 |
|
1346 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1347 |
retval = 0xFFFFFFFF;
|
1348 |
if (addr & 0xF) |
1349 |
return retval;
|
1350 |
addr &= 0xFFFF;
|
1351 |
cpu = addr >> 12;
|
1352 |
idx = (addr >> 6) & 0x3; |
1353 |
switch (addr & 0x30) { |
1354 |
case 0x00: /* gtccr */ |
1355 |
retval = mpp->timers[idx].ticc; |
1356 |
break;
|
1357 |
case 0x10: /* gtbcr */ |
1358 |
retval = mpp->timers[idx].tibc; |
1359 |
break;
|
1360 |
case 0x20: /* TIPV */ |
1361 |
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP); |
1362 |
break;
|
1363 |
case 0x30: /* TIDR */ |
1364 |
if ((addr &0xF0) == 0XF0) |
1365 |
retval = mpp->dst[cpu].tfrr; |
1366 |
else
|
1367 |
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE); |
1368 |
break;
|
1369 |
} |
1370 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
1371 |
|
1372 |
return retval;
|
1373 |
} |
1374 |
|
1375 |
static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr, |
1376 |
uint32_t val) |
1377 |
{ |
1378 |
openpic_t *mpp = opaque; |
1379 |
int idx = MPIC_EXT_IRQ;
|
1380 |
|
1381 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1382 |
if (addr & 0xF) |
1383 |
return;
|
1384 |
|
1385 |
addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1386 |
if (addr < MPIC_EXT_REG_SIZE) {
|
1387 |
idx += (addr & 0xFFF0) >> 5; |
1388 |
if (addr & 0x10) { |
1389 |
/* EXDE / IFEDE / IEEDE */
|
1390 |
write_IRQreg(mpp, idx, IRQ_IDE, val); |
1391 |
} else {
|
1392 |
/* EXVP / IFEVP / IEEVP */
|
1393 |
write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1394 |
} |
1395 |
} |
1396 |
} |
1397 |
|
1398 |
static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr) |
1399 |
{ |
1400 |
openpic_t *mpp = opaque; |
1401 |
uint32_t retval; |
1402 |
int idx = MPIC_EXT_IRQ;
|
1403 |
|
1404 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1405 |
retval = 0xFFFFFFFF;
|
1406 |
if (addr & 0xF) |
1407 |
return retval;
|
1408 |
|
1409 |
addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1410 |
if (addr < MPIC_EXT_REG_SIZE) {
|
1411 |
idx += (addr & 0xFFF0) >> 5; |
1412 |
if (addr & 0x10) { |
1413 |
/* EXDE / IFEDE / IEEDE */
|
1414 |
retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1415 |
} else {
|
1416 |
/* EXVP / IFEVP / IEEVP */
|
1417 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1418 |
} |
1419 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
1420 |
} |
1421 |
|
1422 |
return retval;
|
1423 |
} |
1424 |
|
1425 |
static void mpic_src_int_write (void *opaque, target_phys_addr_t addr, |
1426 |
uint32_t val) |
1427 |
{ |
1428 |
openpic_t *mpp = opaque; |
1429 |
int idx = MPIC_INT_IRQ;
|
1430 |
|
1431 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1432 |
if (addr & 0xF) |
1433 |
return;
|
1434 |
|
1435 |
addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1436 |
if (addr < MPIC_INT_REG_SIZE) {
|
1437 |
idx += (addr & 0xFFF0) >> 5; |
1438 |
if (addr & 0x10) { |
1439 |
/* EXDE / IFEDE / IEEDE */
|
1440 |
write_IRQreg(mpp, idx, IRQ_IDE, val); |
1441 |
} else {
|
1442 |
/* EXVP / IFEVP / IEEVP */
|
1443 |
write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1444 |
} |
1445 |
} |
1446 |
} |
1447 |
|
1448 |
static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr) |
1449 |
{ |
1450 |
openpic_t *mpp = opaque; |
1451 |
uint32_t retval; |
1452 |
int idx = MPIC_INT_IRQ;
|
1453 |
|
1454 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1455 |
retval = 0xFFFFFFFF;
|
1456 |
if (addr & 0xF) |
1457 |
return retval;
|
1458 |
|
1459 |
addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1460 |
if (addr < MPIC_INT_REG_SIZE) {
|
1461 |
idx += (addr & 0xFFF0) >> 5; |
1462 |
if (addr & 0x10) { |
1463 |
/* EXDE / IFEDE / IEEDE */
|
1464 |
retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1465 |
} else {
|
1466 |
/* EXVP / IFEVP / IEEVP */
|
1467 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1468 |
} |
1469 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
1470 |
} |
1471 |
|
1472 |
return retval;
|
1473 |
} |
1474 |
|
1475 |
static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr, |
1476 |
uint32_t val) |
1477 |
{ |
1478 |
openpic_t *mpp = opaque; |
1479 |
int idx = MPIC_MSG_IRQ;
|
1480 |
|
1481 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1482 |
if (addr & 0xF) |
1483 |
return;
|
1484 |
|
1485 |
addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1486 |
if (addr < MPIC_MSG_REG_SIZE) {
|
1487 |
idx += (addr & 0xFFF0) >> 5; |
1488 |
if (addr & 0x10) { |
1489 |
/* EXDE / IFEDE / IEEDE */
|
1490 |
write_IRQreg(mpp, idx, IRQ_IDE, val); |
1491 |
} else {
|
1492 |
/* EXVP / IFEVP / IEEVP */
|
1493 |
write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1494 |
} |
1495 |
} |
1496 |
} |
1497 |
|
1498 |
static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr) |
1499 |
{ |
1500 |
openpic_t *mpp = opaque; |
1501 |
uint32_t retval; |
1502 |
int idx = MPIC_MSG_IRQ;
|
1503 |
|
1504 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1505 |
retval = 0xFFFFFFFF;
|
1506 |
if (addr & 0xF) |
1507 |
return retval;
|
1508 |
|
1509 |
addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1510 |
if (addr < MPIC_MSG_REG_SIZE) {
|
1511 |
idx += (addr & 0xFFF0) >> 5; |
1512 |
if (addr & 0x10) { |
1513 |
/* EXDE / IFEDE / IEEDE */
|
1514 |
retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1515 |
} else {
|
1516 |
/* EXVP / IFEVP / IEEVP */
|
1517 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1518 |
} |
1519 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
1520 |
} |
1521 |
|
1522 |
return retval;
|
1523 |
} |
1524 |
|
1525 |
static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr, |
1526 |
uint32_t val) |
1527 |
{ |
1528 |
openpic_t *mpp = opaque; |
1529 |
int idx = MPIC_MSI_IRQ;
|
1530 |
|
1531 |
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
1532 |
if (addr & 0xF) |
1533 |
return;
|
1534 |
|
1535 |
addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1536 |
if (addr < MPIC_MSI_REG_SIZE) {
|
1537 |
idx += (addr & 0xFFF0) >> 5; |
1538 |
if (addr & 0x10) { |
1539 |
/* EXDE / IFEDE / IEEDE */
|
1540 |
write_IRQreg(mpp, idx, IRQ_IDE, val); |
1541 |
} else {
|
1542 |
/* EXVP / IFEVP / IEEVP */
|
1543 |
write_IRQreg(mpp, idx, IRQ_IPVP, val); |
1544 |
} |
1545 |
} |
1546 |
} |
1547 |
static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr) |
1548 |
{ |
1549 |
openpic_t *mpp = opaque; |
1550 |
uint32_t retval; |
1551 |
int idx = MPIC_MSI_IRQ;
|
1552 |
|
1553 |
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
1554 |
retval = 0xFFFFFFFF;
|
1555 |
if (addr & 0xF) |
1556 |
return retval;
|
1557 |
|
1558 |
addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
|
1559 |
if (addr < MPIC_MSI_REG_SIZE) {
|
1560 |
idx += (addr & 0xFFF0) >> 5; |
1561 |
if (addr & 0x10) { |
1562 |
/* EXDE / IFEDE / IEEDE */
|
1563 |
retval = read_IRQreg(mpp, idx, IRQ_IDE); |
1564 |
} else {
|
1565 |
/* EXVP / IFEVP / IEEVP */
|
1566 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP); |
1567 |
} |
1568 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
1569 |
} |
1570 |
|
1571 |
return retval;
|
1572 |
} |
1573 |
|
1574 |
static CPUWriteMemoryFunc * const mpic_glb_write[] = { |
1575 |
&openpic_buggy_write, |
1576 |
&openpic_buggy_write, |
1577 |
&openpic_gbl_write, |
1578 |
}; |
1579 |
|
1580 |
static CPUReadMemoryFunc * const mpic_glb_read[] = { |
1581 |
&openpic_buggy_read, |
1582 |
&openpic_buggy_read, |
1583 |
&openpic_gbl_read, |
1584 |
}; |
1585 |
|
1586 |
static CPUWriteMemoryFunc * const mpic_tmr_write[] = { |
1587 |
&openpic_buggy_write, |
1588 |
&openpic_buggy_write, |
1589 |
&mpic_timer_write, |
1590 |
}; |
1591 |
|
1592 |
static CPUReadMemoryFunc * const mpic_tmr_read[] = { |
1593 |
&openpic_buggy_read, |
1594 |
&openpic_buggy_read, |
1595 |
&mpic_timer_read, |
1596 |
}; |
1597 |
|
1598 |
static CPUWriteMemoryFunc * const mpic_cpu_write[] = { |
1599 |
&openpic_buggy_write, |
1600 |
&openpic_buggy_write, |
1601 |
&openpic_cpu_write, |
1602 |
}; |
1603 |
|
1604 |
static CPUReadMemoryFunc * const mpic_cpu_read[] = { |
1605 |
&openpic_buggy_read, |
1606 |
&openpic_buggy_read, |
1607 |
&openpic_cpu_read, |
1608 |
}; |
1609 |
|
1610 |
static CPUWriteMemoryFunc * const mpic_ext_write[] = { |
1611 |
&openpic_buggy_write, |
1612 |
&openpic_buggy_write, |
1613 |
&mpic_src_ext_write, |
1614 |
}; |
1615 |
|
1616 |
static CPUReadMemoryFunc * const mpic_ext_read[] = { |
1617 |
&openpic_buggy_read, |
1618 |
&openpic_buggy_read, |
1619 |
&mpic_src_ext_read, |
1620 |
}; |
1621 |
|
1622 |
static CPUWriteMemoryFunc * const mpic_int_write[] = { |
1623 |
&openpic_buggy_write, |
1624 |
&openpic_buggy_write, |
1625 |
&mpic_src_int_write, |
1626 |
}; |
1627 |
|
1628 |
static CPUReadMemoryFunc * const mpic_int_read[] = { |
1629 |
&openpic_buggy_read, |
1630 |
&openpic_buggy_read, |
1631 |
&mpic_src_int_read, |
1632 |
}; |
1633 |
|
1634 |
static CPUWriteMemoryFunc * const mpic_msg_write[] = { |
1635 |
&openpic_buggy_write, |
1636 |
&openpic_buggy_write, |
1637 |
&mpic_src_msg_write, |
1638 |
}; |
1639 |
|
1640 |
static CPUReadMemoryFunc * const mpic_msg_read[] = { |
1641 |
&openpic_buggy_read, |
1642 |
&openpic_buggy_read, |
1643 |
&mpic_src_msg_read, |
1644 |
}; |
1645 |
static CPUWriteMemoryFunc * const mpic_msi_write[] = { |
1646 |
&openpic_buggy_write, |
1647 |
&openpic_buggy_write, |
1648 |
&mpic_src_msi_write, |
1649 |
}; |
1650 |
|
1651 |
static CPUReadMemoryFunc * const mpic_msi_read[] = { |
1652 |
&openpic_buggy_read, |
1653 |
&openpic_buggy_read, |
1654 |
&mpic_src_msi_read, |
1655 |
}; |
1656 |
|
1657 |
qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
|
1658 |
qemu_irq **irqs, qemu_irq irq_out) |
1659 |
{ |
1660 |
openpic_t *mpp; |
1661 |
int i;
|
1662 |
struct {
|
1663 |
CPUReadMemoryFunc * const *read;
|
1664 |
CPUWriteMemoryFunc * const *write;
|
1665 |
target_phys_addr_t start_addr; |
1666 |
ram_addr_t size; |
1667 |
} const list[] = {
|
1668 |
{mpic_glb_read, mpic_glb_write, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE}, |
1669 |
{mpic_tmr_read, mpic_tmr_write, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE}, |
1670 |
{mpic_ext_read, mpic_ext_write, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE}, |
1671 |
{mpic_int_read, mpic_int_write, MPIC_INT_REG_START, MPIC_INT_REG_SIZE}, |
1672 |
{mpic_msg_read, mpic_msg_write, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE}, |
1673 |
{mpic_msi_read, mpic_msi_write, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE}, |
1674 |
{mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, |
1675 |
}; |
1676 |
|
1677 |
/* XXX: for now, only one CPU is supported */
|
1678 |
if (nb_cpus != 1) |
1679 |
return NULL; |
1680 |
|
1681 |
mpp = g_malloc0(sizeof(openpic_t));
|
1682 |
|
1683 |
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { |
1684 |
int mem_index;
|
1685 |
|
1686 |
mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp, |
1687 |
DEVICE_BIG_ENDIAN); |
1688 |
if (mem_index < 0) { |
1689 |
goto free;
|
1690 |
} |
1691 |
cpu_register_physical_memory(base + list[i].start_addr, |
1692 |
list[i].size, mem_index); |
1693 |
} |
1694 |
|
1695 |
mpp->nb_cpus = nb_cpus; |
1696 |
mpp->max_irq = MPIC_MAX_IRQ; |
1697 |
mpp->irq_ipi0 = MPIC_IPI_IRQ; |
1698 |
mpp->irq_tim0 = MPIC_TMR_IRQ; |
1699 |
|
1700 |
for (i = 0; i < nb_cpus; i++) |
1701 |
mpp->dst[i].irqs = irqs[i]; |
1702 |
mpp->irq_out = irq_out; |
1703 |
|
1704 |
mpp->irq_raise = mpic_irq_raise; |
1705 |
mpp->reset = mpic_reset; |
1706 |
|
1707 |
register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp); |
1708 |
qemu_register_reset(mpic_reset, mpp); |
1709 |
|
1710 |
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
|
1711 |
|
1712 |
free:
|
1713 |
g_free(mpp); |
1714 |
return NULL; |
1715 |
} |