root / hw / apic.c @ bc798c77
History | View | Annotate | Download (26 kB)
1 |
/*
|
---|---|
2 |
* APIC support
|
3 |
*
|
4 |
* Copyright (c) 2004-2005 Fabrice Bellard
|
5 |
*
|
6 |
* This library is free software; you can redistribute it and/or
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
8 |
* License as published by the Free Software Foundation; either
|
9 |
* version 2 of the License, or (at your option) any later version.
|
10 |
*
|
11 |
* This library is distributed in the hope that it will be useful,
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
* Lesser General Public License for more details.
|
15 |
*
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>
|
18 |
*/
|
19 |
#include "hw.h" |
20 |
#include "pc.h" |
21 |
#include "pci.h" |
22 |
#include "msix.h" |
23 |
#include "qemu-timer.h" |
24 |
#include "host-utils.h" |
25 |
#include "kvm.h" |
26 |
|
27 |
//#define DEBUG_APIC
|
28 |
|
29 |
/* APIC Local Vector Table */
|
30 |
#define APIC_LVT_TIMER 0 |
31 |
#define APIC_LVT_THERMAL 1 |
32 |
#define APIC_LVT_PERFORM 2 |
33 |
#define APIC_LVT_LINT0 3 |
34 |
#define APIC_LVT_LINT1 4 |
35 |
#define APIC_LVT_ERROR 5 |
36 |
#define APIC_LVT_NB 6 |
37 |
|
38 |
/* APIC delivery modes */
|
39 |
#define APIC_DM_FIXED 0 |
40 |
#define APIC_DM_LOWPRI 1 |
41 |
#define APIC_DM_SMI 2 |
42 |
#define APIC_DM_NMI 4 |
43 |
#define APIC_DM_INIT 5 |
44 |
#define APIC_DM_SIPI 6 |
45 |
#define APIC_DM_EXTINT 7 |
46 |
|
47 |
/* APIC destination mode */
|
48 |
#define APIC_DESTMODE_FLAT 0xf |
49 |
#define APIC_DESTMODE_CLUSTER 1 |
50 |
|
51 |
#define APIC_TRIGGER_EDGE 0 |
52 |
#define APIC_TRIGGER_LEVEL 1 |
53 |
|
54 |
#define APIC_LVT_TIMER_PERIODIC (1<<17) |
55 |
#define APIC_LVT_MASKED (1<<16) |
56 |
#define APIC_LVT_LEVEL_TRIGGER (1<<15) |
57 |
#define APIC_LVT_REMOTE_IRR (1<<14) |
58 |
#define APIC_INPUT_POLARITY (1<<13) |
59 |
#define APIC_SEND_PENDING (1<<12) |
60 |
|
61 |
#define ESR_ILLEGAL_ADDRESS (1 << 7) |
62 |
|
63 |
#define APIC_SV_ENABLE (1 << 8) |
64 |
|
65 |
#define MAX_APICS 255 |
66 |
#define MAX_APIC_WORDS 8 |
67 |
|
68 |
/* Intel APIC constants: from include/asm/msidef.h */
|
69 |
#define MSI_DATA_VECTOR_SHIFT 0 |
70 |
#define MSI_DATA_VECTOR_MASK 0x000000ff |
71 |
#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
72 |
#define MSI_DATA_TRIGGER_SHIFT 15 |
73 |
#define MSI_DATA_LEVEL_SHIFT 14 |
74 |
#define MSI_ADDR_DEST_MODE_SHIFT 2 |
75 |
#define MSI_ADDR_DEST_ID_SHIFT 12 |
76 |
#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
77 |
|
78 |
#define MSI_ADDR_BASE 0xfee00000 |
79 |
#define MSI_ADDR_SIZE 0x100000 |
80 |
|
81 |
typedef struct APICState { |
82 |
CPUState *cpu_env; |
83 |
uint32_t apicbase; |
84 |
uint8_t id; |
85 |
uint8_t arb_id; |
86 |
uint8_t tpr; |
87 |
uint32_t spurious_vec; |
88 |
uint8_t log_dest; |
89 |
uint8_t dest_mode; |
90 |
uint32_t isr[8]; /* in service register */ |
91 |
uint32_t tmr[8]; /* trigger mode register */ |
92 |
uint32_t irr[8]; /* interrupt request register */ |
93 |
uint32_t lvt[APIC_LVT_NB]; |
94 |
uint32_t esr; /* error register */
|
95 |
uint32_t icr[2];
|
96 |
|
97 |
uint32_t divide_conf; |
98 |
int count_shift;
|
99 |
uint32_t initial_count; |
100 |
int64_t initial_count_load_time, next_time; |
101 |
uint32_t idx; |
102 |
QEMUTimer *timer; |
103 |
int sipi_vector;
|
104 |
int wait_for_sipi;
|
105 |
} APICState; |
106 |
|
107 |
static int apic_io_memory; |
108 |
static APICState *local_apics[MAX_APICS + 1]; |
109 |
static int last_apic_idx = 0; |
110 |
static int apic_irq_delivered; |
111 |
|
112 |
|
113 |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
114 |
static void apic_update_irq(APICState *s); |
115 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
116 |
uint8_t dest, uint8_t dest_mode); |
117 |
|
118 |
/* Find first bit starting from msb */
|
119 |
static int fls_bit(uint32_t value) |
120 |
{ |
121 |
return 31 - clz32(value); |
122 |
} |
123 |
|
124 |
/* Find first bit starting from lsb */
|
125 |
static int ffs_bit(uint32_t value) |
126 |
{ |
127 |
return ctz32(value);
|
128 |
} |
129 |
|
130 |
static inline void set_bit(uint32_t *tab, int index) |
131 |
{ |
132 |
int i, mask;
|
133 |
i = index >> 5;
|
134 |
mask = 1 << (index & 0x1f); |
135 |
tab[i] |= mask; |
136 |
} |
137 |
|
138 |
static inline void reset_bit(uint32_t *tab, int index) |
139 |
{ |
140 |
int i, mask;
|
141 |
i = index >> 5;
|
142 |
mask = 1 << (index & 0x1f); |
143 |
tab[i] &= ~mask; |
144 |
} |
145 |
|
146 |
static inline int get_bit(uint32_t *tab, int index) |
147 |
{ |
148 |
int i, mask;
|
149 |
i = index >> 5;
|
150 |
mask = 1 << (index & 0x1f); |
151 |
return !!(tab[i] & mask);
|
152 |
} |
153 |
|
154 |
static void apic_local_deliver(CPUState *env, int vector) |
155 |
{ |
156 |
APICState *s = env->apic_state; |
157 |
uint32_t lvt = s->lvt[vector]; |
158 |
int trigger_mode;
|
159 |
|
160 |
if (lvt & APIC_LVT_MASKED)
|
161 |
return;
|
162 |
|
163 |
switch ((lvt >> 8) & 7) { |
164 |
case APIC_DM_SMI:
|
165 |
cpu_interrupt(env, CPU_INTERRUPT_SMI); |
166 |
break;
|
167 |
|
168 |
case APIC_DM_NMI:
|
169 |
cpu_interrupt(env, CPU_INTERRUPT_NMI); |
170 |
break;
|
171 |
|
172 |
case APIC_DM_EXTINT:
|
173 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
174 |
break;
|
175 |
|
176 |
case APIC_DM_FIXED:
|
177 |
trigger_mode = APIC_TRIGGER_EDGE; |
178 |
if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
|
179 |
(lvt & APIC_LVT_LEVEL_TRIGGER)) |
180 |
trigger_mode = APIC_TRIGGER_LEVEL; |
181 |
apic_set_irq(s, lvt & 0xff, trigger_mode);
|
182 |
} |
183 |
} |
184 |
|
185 |
void apic_deliver_pic_intr(CPUState *env, int level) |
186 |
{ |
187 |
if (level)
|
188 |
apic_local_deliver(env, APIC_LVT_LINT0); |
189 |
else {
|
190 |
APICState *s = env->apic_state; |
191 |
uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
192 |
|
193 |
switch ((lvt >> 8) & 7) { |
194 |
case APIC_DM_FIXED:
|
195 |
if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
|
196 |
break;
|
197 |
reset_bit(s->irr, lvt & 0xff);
|
198 |
/* fall through */
|
199 |
case APIC_DM_EXTINT:
|
200 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
201 |
break;
|
202 |
} |
203 |
} |
204 |
} |
205 |
|
206 |
#define foreach_apic(apic, deliver_bitmask, code) \
|
207 |
{\ |
208 |
int __i, __j, __mask;\
|
209 |
for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
210 |
__mask = deliver_bitmask[__i];\ |
211 |
if (__mask) {\
|
212 |
for(__j = 0; __j < 32; __j++) {\ |
213 |
if (__mask & (1 << __j)) {\ |
214 |
apic = local_apics[__i * 32 + __j];\
|
215 |
if (apic) {\
|
216 |
code;\ |
217 |
}\ |
218 |
}\ |
219 |
}\ |
220 |
}\ |
221 |
}\ |
222 |
} |
223 |
|
224 |
static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
225 |
uint8_t delivery_mode, |
226 |
uint8_t vector_num, uint8_t polarity, |
227 |
uint8_t trigger_mode) |
228 |
{ |
229 |
APICState *apic_iter; |
230 |
|
231 |
switch (delivery_mode) {
|
232 |
case APIC_DM_LOWPRI:
|
233 |
/* XXX: search for focus processor, arbitration */
|
234 |
{ |
235 |
int i, d;
|
236 |
d = -1;
|
237 |
for(i = 0; i < MAX_APIC_WORDS; i++) { |
238 |
if (deliver_bitmask[i]) {
|
239 |
d = i * 32 + ffs_bit(deliver_bitmask[i]);
|
240 |
break;
|
241 |
} |
242 |
} |
243 |
if (d >= 0) { |
244 |
apic_iter = local_apics[d]; |
245 |
if (apic_iter) {
|
246 |
apic_set_irq(apic_iter, vector_num, trigger_mode); |
247 |
} |
248 |
} |
249 |
} |
250 |
return;
|
251 |
|
252 |
case APIC_DM_FIXED:
|
253 |
break;
|
254 |
|
255 |
case APIC_DM_SMI:
|
256 |
foreach_apic(apic_iter, deliver_bitmask, |
257 |
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
258 |
return;
|
259 |
|
260 |
case APIC_DM_NMI:
|
261 |
foreach_apic(apic_iter, deliver_bitmask, |
262 |
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
263 |
return;
|
264 |
|
265 |
case APIC_DM_INIT:
|
266 |
/* normal INIT IPI sent to processors */
|
267 |
foreach_apic(apic_iter, deliver_bitmask, |
268 |
cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
269 |
return;
|
270 |
|
271 |
case APIC_DM_EXTINT:
|
272 |
/* handled in I/O APIC code */
|
273 |
break;
|
274 |
|
275 |
default:
|
276 |
return;
|
277 |
} |
278 |
|
279 |
foreach_apic(apic_iter, deliver_bitmask, |
280 |
apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
281 |
} |
282 |
|
283 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
|
284 |
uint8_t delivery_mode, uint8_t vector_num, |
285 |
uint8_t polarity, uint8_t trigger_mode) |
286 |
{ |
287 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
288 |
|
289 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
290 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
291 |
trigger_mode); |
292 |
} |
293 |
|
294 |
void cpu_set_apic_base(CPUState *env, uint64_t val)
|
295 |
{ |
296 |
APICState *s = env->apic_state; |
297 |
#ifdef DEBUG_APIC
|
298 |
printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
299 |
#endif
|
300 |
if (!s)
|
301 |
return;
|
302 |
s->apicbase = (val & 0xfffff000) |
|
303 |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
304 |
/* if disabled, cannot be enabled again */
|
305 |
if (!(val & MSR_IA32_APICBASE_ENABLE)) {
|
306 |
s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
307 |
env->cpuid_features &= ~CPUID_APIC; |
308 |
s->spurious_vec &= ~APIC_SV_ENABLE; |
309 |
} |
310 |
} |
311 |
|
312 |
uint64_t cpu_get_apic_base(CPUState *env) |
313 |
{ |
314 |
APICState *s = env->apic_state; |
315 |
#ifdef DEBUG_APIC
|
316 |
printf("cpu_get_apic_base: %016" PRIx64 "\n", |
317 |
s ? (uint64_t)s->apicbase: 0);
|
318 |
#endif
|
319 |
return s ? s->apicbase : 0; |
320 |
} |
321 |
|
322 |
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
|
323 |
{ |
324 |
APICState *s = env->apic_state; |
325 |
if (!s)
|
326 |
return;
|
327 |
s->tpr = (val & 0x0f) << 4; |
328 |
apic_update_irq(s); |
329 |
} |
330 |
|
331 |
uint8_t cpu_get_apic_tpr(CPUX86State *env) |
332 |
{ |
333 |
APICState *s = env->apic_state; |
334 |
return s ? s->tpr >> 4 : 0; |
335 |
} |
336 |
|
337 |
/* return -1 if no bit is set */
|
338 |
static int get_highest_priority_int(uint32_t *tab) |
339 |
{ |
340 |
int i;
|
341 |
for(i = 7; i >= 0; i--) { |
342 |
if (tab[i] != 0) { |
343 |
return i * 32 + fls_bit(tab[i]); |
344 |
} |
345 |
} |
346 |
return -1; |
347 |
} |
348 |
|
349 |
static int apic_get_ppr(APICState *s) |
350 |
{ |
351 |
int tpr, isrv, ppr;
|
352 |
|
353 |
tpr = (s->tpr >> 4);
|
354 |
isrv = get_highest_priority_int(s->isr); |
355 |
if (isrv < 0) |
356 |
isrv = 0;
|
357 |
isrv >>= 4;
|
358 |
if (tpr >= isrv)
|
359 |
ppr = s->tpr; |
360 |
else
|
361 |
ppr = isrv << 4;
|
362 |
return ppr;
|
363 |
} |
364 |
|
365 |
static int apic_get_arb_pri(APICState *s) |
366 |
{ |
367 |
/* XXX: arbitration */
|
368 |
return 0; |
369 |
} |
370 |
|
371 |
/* signal the CPU if an irq is pending */
|
372 |
static void apic_update_irq(APICState *s) |
373 |
{ |
374 |
int irrv, ppr;
|
375 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
376 |
return;
|
377 |
irrv = get_highest_priority_int(s->irr); |
378 |
if (irrv < 0) |
379 |
return;
|
380 |
ppr = apic_get_ppr(s); |
381 |
if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
382 |
return;
|
383 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
384 |
} |
385 |
|
386 |
void apic_reset_irq_delivered(void) |
387 |
{ |
388 |
apic_irq_delivered = 0;
|
389 |
} |
390 |
|
391 |
int apic_get_irq_delivered(void) |
392 |
{ |
393 |
return apic_irq_delivered;
|
394 |
} |
395 |
|
396 |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
397 |
{ |
398 |
apic_irq_delivered += !get_bit(s->irr, vector_num); |
399 |
|
400 |
set_bit(s->irr, vector_num); |
401 |
if (trigger_mode)
|
402 |
set_bit(s->tmr, vector_num); |
403 |
else
|
404 |
reset_bit(s->tmr, vector_num); |
405 |
apic_update_irq(s); |
406 |
} |
407 |
|
408 |
static void apic_eoi(APICState *s) |
409 |
{ |
410 |
int isrv;
|
411 |
isrv = get_highest_priority_int(s->isr); |
412 |
if (isrv < 0) |
413 |
return;
|
414 |
reset_bit(s->isr, isrv); |
415 |
/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
416 |
set the remote IRR bit for level triggered interrupts. */
|
417 |
apic_update_irq(s); |
418 |
} |
419 |
|
420 |
static int apic_find_dest(uint8_t dest) |
421 |
{ |
422 |
APICState *apic = local_apics[dest]; |
423 |
int i;
|
424 |
|
425 |
if (apic && apic->id == dest)
|
426 |
return dest; /* shortcut in case apic->id == apic->idx */ |
427 |
|
428 |
for (i = 0; i < MAX_APICS; i++) { |
429 |
apic = local_apics[i]; |
430 |
if (apic && apic->id == dest)
|
431 |
return i;
|
432 |
} |
433 |
|
434 |
return -1; |
435 |
} |
436 |
|
437 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
438 |
uint8_t dest, uint8_t dest_mode) |
439 |
{ |
440 |
APICState *apic_iter; |
441 |
int i;
|
442 |
|
443 |
if (dest_mode == 0) { |
444 |
if (dest == 0xff) { |
445 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
446 |
} else {
|
447 |
int idx = apic_find_dest(dest);
|
448 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
449 |
if (idx >= 0) |
450 |
set_bit(deliver_bitmask, idx); |
451 |
} |
452 |
} else {
|
453 |
/* XXX: cluster mode */
|
454 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
455 |
for(i = 0; i < MAX_APICS; i++) { |
456 |
apic_iter = local_apics[i]; |
457 |
if (apic_iter) {
|
458 |
if (apic_iter->dest_mode == 0xf) { |
459 |
if (dest & apic_iter->log_dest)
|
460 |
set_bit(deliver_bitmask, i); |
461 |
} else if (apic_iter->dest_mode == 0x0) { |
462 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
463 |
(dest & apic_iter->log_dest & 0x0f)) {
|
464 |
set_bit(deliver_bitmask, i); |
465 |
} |
466 |
} |
467 |
} |
468 |
} |
469 |
} |
470 |
} |
471 |
|
472 |
|
473 |
void apic_init_reset(CPUState *env)
|
474 |
{ |
475 |
APICState *s = env->apic_state; |
476 |
int i;
|
477 |
|
478 |
if (!s)
|
479 |
return;
|
480 |
|
481 |
s->tpr = 0;
|
482 |
s->spurious_vec = 0xff;
|
483 |
s->log_dest = 0;
|
484 |
s->dest_mode = 0xf;
|
485 |
memset(s->isr, 0, sizeof(s->isr)); |
486 |
memset(s->tmr, 0, sizeof(s->tmr)); |
487 |
memset(s->irr, 0, sizeof(s->irr)); |
488 |
for(i = 0; i < APIC_LVT_NB; i++) |
489 |
s->lvt[i] = 1 << 16; /* mask LVT */ |
490 |
s->esr = 0;
|
491 |
memset(s->icr, 0, sizeof(s->icr)); |
492 |
s->divide_conf = 0;
|
493 |
s->count_shift = 0;
|
494 |
s->initial_count = 0;
|
495 |
s->initial_count_load_time = 0;
|
496 |
s->next_time = 0;
|
497 |
s->wait_for_sipi = 1;
|
498 |
|
499 |
env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
500 |
} |
501 |
|
502 |
static void apic_startup(APICState *s, int vector_num) |
503 |
{ |
504 |
s->sipi_vector = vector_num; |
505 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
506 |
} |
507 |
|
508 |
void apic_sipi(CPUState *env)
|
509 |
{ |
510 |
APICState *s = env->apic_state; |
511 |
|
512 |
cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); |
513 |
|
514 |
if (!s->wait_for_sipi)
|
515 |
return;
|
516 |
|
517 |
env->eip = 0;
|
518 |
cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
519 |
env->segs[R_CS].limit, env->segs[R_CS].flags); |
520 |
env->halted = 0;
|
521 |
s->wait_for_sipi = 0;
|
522 |
} |
523 |
|
524 |
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
525 |
uint8_t delivery_mode, uint8_t vector_num, |
526 |
uint8_t polarity, uint8_t trigger_mode) |
527 |
{ |
528 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
529 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
530 |
APICState *apic_iter; |
531 |
|
532 |
switch (dest_shorthand) {
|
533 |
case 0: |
534 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
535 |
break;
|
536 |
case 1: |
537 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
538 |
set_bit(deliver_bitmask, s->idx); |
539 |
break;
|
540 |
case 2: |
541 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
542 |
break;
|
543 |
case 3: |
544 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
545 |
reset_bit(deliver_bitmask, s->idx); |
546 |
break;
|
547 |
} |
548 |
|
549 |
switch (delivery_mode) {
|
550 |
case APIC_DM_INIT:
|
551 |
{ |
552 |
int trig_mode = (s->icr[0] >> 15) & 1; |
553 |
int level = (s->icr[0] >> 14) & 1; |
554 |
if (level == 0 && trig_mode == 1) { |
555 |
foreach_apic(apic_iter, deliver_bitmask, |
556 |
apic_iter->arb_id = apic_iter->id ); |
557 |
return;
|
558 |
} |
559 |
} |
560 |
break;
|
561 |
|
562 |
case APIC_DM_SIPI:
|
563 |
foreach_apic(apic_iter, deliver_bitmask, |
564 |
apic_startup(apic_iter, vector_num) ); |
565 |
return;
|
566 |
} |
567 |
|
568 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
569 |
trigger_mode); |
570 |
} |
571 |
|
572 |
int apic_get_interrupt(CPUState *env)
|
573 |
{ |
574 |
APICState *s = env->apic_state; |
575 |
int intno;
|
576 |
|
577 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
578 |
IRQs */
|
579 |
if (!s)
|
580 |
return -1; |
581 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
582 |
return -1; |
583 |
|
584 |
/* XXX: spurious IRQ handling */
|
585 |
intno = get_highest_priority_int(s->irr); |
586 |
if (intno < 0) |
587 |
return -1; |
588 |
if (s->tpr && intno <= s->tpr)
|
589 |
return s->spurious_vec & 0xff; |
590 |
reset_bit(s->irr, intno); |
591 |
set_bit(s->isr, intno); |
592 |
apic_update_irq(s); |
593 |
return intno;
|
594 |
} |
595 |
|
596 |
int apic_accept_pic_intr(CPUState *env)
|
597 |
{ |
598 |
APICState *s = env->apic_state; |
599 |
uint32_t lvt0; |
600 |
|
601 |
if (!s)
|
602 |
return -1; |
603 |
|
604 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
605 |
|
606 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
607 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
608 |
return 1; |
609 |
|
610 |
return 0; |
611 |
} |
612 |
|
613 |
static uint32_t apic_get_current_count(APICState *s)
|
614 |
{ |
615 |
int64_t d; |
616 |
uint32_t val; |
617 |
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
618 |
s->count_shift; |
619 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
620 |
/* periodic */
|
621 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
622 |
} else {
|
623 |
if (d >= s->initial_count)
|
624 |
val = 0;
|
625 |
else
|
626 |
val = s->initial_count - d; |
627 |
} |
628 |
return val;
|
629 |
} |
630 |
|
631 |
static void apic_timer_update(APICState *s, int64_t current_time) |
632 |
{ |
633 |
int64_t next_time, d; |
634 |
|
635 |
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
636 |
d = (current_time - s->initial_count_load_time) >> |
637 |
s->count_shift; |
638 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
639 |
if (!s->initial_count)
|
640 |
goto no_timer;
|
641 |
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
642 |
} else {
|
643 |
if (d >= s->initial_count)
|
644 |
goto no_timer;
|
645 |
d = (uint64_t)s->initial_count + 1;
|
646 |
} |
647 |
next_time = s->initial_count_load_time + (d << s->count_shift); |
648 |
qemu_mod_timer(s->timer, next_time); |
649 |
s->next_time = next_time; |
650 |
} else {
|
651 |
no_timer:
|
652 |
qemu_del_timer(s->timer); |
653 |
} |
654 |
} |
655 |
|
656 |
static void apic_timer(void *opaque) |
657 |
{ |
658 |
APICState *s = opaque; |
659 |
|
660 |
apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
661 |
apic_timer_update(s, s->next_time); |
662 |
} |
663 |
|
664 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
665 |
{ |
666 |
return 0; |
667 |
} |
668 |
|
669 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
670 |
{ |
671 |
return 0; |
672 |
} |
673 |
|
674 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
675 |
{ |
676 |
} |
677 |
|
678 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
679 |
{ |
680 |
} |
681 |
|
682 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
683 |
{ |
684 |
CPUState *env; |
685 |
APICState *s; |
686 |
uint32_t val; |
687 |
int index;
|
688 |
|
689 |
env = cpu_single_env; |
690 |
if (!env)
|
691 |
return 0; |
692 |
s = env->apic_state; |
693 |
|
694 |
index = (addr >> 4) & 0xff; |
695 |
switch(index) {
|
696 |
case 0x02: /* id */ |
697 |
val = s->id << 24;
|
698 |
break;
|
699 |
case 0x03: /* version */ |
700 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
701 |
break;
|
702 |
case 0x08: |
703 |
val = s->tpr; |
704 |
break;
|
705 |
case 0x09: |
706 |
val = apic_get_arb_pri(s); |
707 |
break;
|
708 |
case 0x0a: |
709 |
/* ppr */
|
710 |
val = apic_get_ppr(s); |
711 |
break;
|
712 |
case 0x0b: |
713 |
val = 0;
|
714 |
break;
|
715 |
case 0x0d: |
716 |
val = s->log_dest << 24;
|
717 |
break;
|
718 |
case 0x0e: |
719 |
val = s->dest_mode << 28;
|
720 |
break;
|
721 |
case 0x0f: |
722 |
val = s->spurious_vec; |
723 |
break;
|
724 |
case 0x10 ... 0x17: |
725 |
val = s->isr[index & 7];
|
726 |
break;
|
727 |
case 0x18 ... 0x1f: |
728 |
val = s->tmr[index & 7];
|
729 |
break;
|
730 |
case 0x20 ... 0x27: |
731 |
val = s->irr[index & 7];
|
732 |
break;
|
733 |
case 0x28: |
734 |
val = s->esr; |
735 |
break;
|
736 |
case 0x30: |
737 |
case 0x31: |
738 |
val = s->icr[index & 1];
|
739 |
break;
|
740 |
case 0x32 ... 0x37: |
741 |
val = s->lvt[index - 0x32];
|
742 |
break;
|
743 |
case 0x38: |
744 |
val = s->initial_count; |
745 |
break;
|
746 |
case 0x39: |
747 |
val = apic_get_current_count(s); |
748 |
break;
|
749 |
case 0x3e: |
750 |
val = s->divide_conf; |
751 |
break;
|
752 |
default:
|
753 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
754 |
val = 0;
|
755 |
break;
|
756 |
} |
757 |
#ifdef DEBUG_APIC
|
758 |
printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
759 |
#endif
|
760 |
return val;
|
761 |
} |
762 |
|
763 |
static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
764 |
{ |
765 |
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
766 |
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
767 |
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
768 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
769 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
770 |
/* XXX: Ignore redirection hint. */
|
771 |
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
772 |
} |
773 |
|
774 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
775 |
{ |
776 |
CPUState *env; |
777 |
APICState *s; |
778 |
int index = (addr >> 4) & 0xff; |
779 |
if (addr > 0xfff || !index) { |
780 |
/* MSI and MMIO APIC are at the same memory location,
|
781 |
* but actually not on the global bus: MSI is on PCI bus
|
782 |
* APIC is connected directly to the CPU.
|
783 |
* Mapping them on the global bus happens to work because
|
784 |
* MSI registers are reserved in APIC MMIO and vice versa. */
|
785 |
apic_send_msi(addr, val); |
786 |
return;
|
787 |
} |
788 |
|
789 |
env = cpu_single_env; |
790 |
if (!env)
|
791 |
return;
|
792 |
s = env->apic_state; |
793 |
|
794 |
#ifdef DEBUG_APIC
|
795 |
printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
796 |
#endif
|
797 |
|
798 |
switch(index) {
|
799 |
case 0x02: |
800 |
s->id = (val >> 24);
|
801 |
break;
|
802 |
case 0x03: |
803 |
break;
|
804 |
case 0x08: |
805 |
s->tpr = val; |
806 |
apic_update_irq(s); |
807 |
break;
|
808 |
case 0x09: |
809 |
case 0x0a: |
810 |
break;
|
811 |
case 0x0b: /* EOI */ |
812 |
apic_eoi(s); |
813 |
break;
|
814 |
case 0x0d: |
815 |
s->log_dest = val >> 24;
|
816 |
break;
|
817 |
case 0x0e: |
818 |
s->dest_mode = val >> 28;
|
819 |
break;
|
820 |
case 0x0f: |
821 |
s->spurious_vec = val & 0x1ff;
|
822 |
apic_update_irq(s); |
823 |
break;
|
824 |
case 0x10 ... 0x17: |
825 |
case 0x18 ... 0x1f: |
826 |
case 0x20 ... 0x27: |
827 |
case 0x28: |
828 |
break;
|
829 |
case 0x30: |
830 |
s->icr[0] = val;
|
831 |
apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
832 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
833 |
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
834 |
break;
|
835 |
case 0x31: |
836 |
s->icr[1] = val;
|
837 |
break;
|
838 |
case 0x32 ... 0x37: |
839 |
{ |
840 |
int n = index - 0x32; |
841 |
s->lvt[n] = val; |
842 |
if (n == APIC_LVT_TIMER)
|
843 |
apic_timer_update(s, qemu_get_clock(vm_clock)); |
844 |
} |
845 |
break;
|
846 |
case 0x38: |
847 |
s->initial_count = val; |
848 |
s->initial_count_load_time = qemu_get_clock(vm_clock); |
849 |
apic_timer_update(s, s->initial_count_load_time); |
850 |
break;
|
851 |
case 0x39: |
852 |
break;
|
853 |
case 0x3e: |
854 |
{ |
855 |
int v;
|
856 |
s->divide_conf = val & 0xb;
|
857 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
858 |
s->count_shift = (v + 1) & 7; |
859 |
} |
860 |
break;
|
861 |
default:
|
862 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
863 |
break;
|
864 |
} |
865 |
} |
866 |
|
867 |
/* This function is only used for old state version 1 and 2 */
|
868 |
static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
869 |
{ |
870 |
APICState *s = opaque; |
871 |
int i;
|
872 |
|
873 |
if (version_id > 2) |
874 |
return -EINVAL;
|
875 |
|
876 |
/* XXX: what if the base changes? (registered memory regions) */
|
877 |
qemu_get_be32s(f, &s->apicbase); |
878 |
qemu_get_8s(f, &s->id); |
879 |
qemu_get_8s(f, &s->arb_id); |
880 |
qemu_get_8s(f, &s->tpr); |
881 |
qemu_get_be32s(f, &s->spurious_vec); |
882 |
qemu_get_8s(f, &s->log_dest); |
883 |
qemu_get_8s(f, &s->dest_mode); |
884 |
for (i = 0; i < 8; i++) { |
885 |
qemu_get_be32s(f, &s->isr[i]); |
886 |
qemu_get_be32s(f, &s->tmr[i]); |
887 |
qemu_get_be32s(f, &s->irr[i]); |
888 |
} |
889 |
for (i = 0; i < APIC_LVT_NB; i++) { |
890 |
qemu_get_be32s(f, &s->lvt[i]); |
891 |
} |
892 |
qemu_get_be32s(f, &s->esr); |
893 |
qemu_get_be32s(f, &s->icr[0]);
|
894 |
qemu_get_be32s(f, &s->icr[1]);
|
895 |
qemu_get_be32s(f, &s->divide_conf); |
896 |
s->count_shift=qemu_get_be32(f); |
897 |
qemu_get_be32s(f, &s->initial_count); |
898 |
s->initial_count_load_time=qemu_get_be64(f); |
899 |
s->next_time=qemu_get_be64(f); |
900 |
|
901 |
if (version_id >= 2) |
902 |
qemu_get_timer(f, s->timer); |
903 |
return 0; |
904 |
} |
905 |
|
906 |
static const VMStateDescription vmstate_apic = { |
907 |
.name = "apic",
|
908 |
.version_id = 3,
|
909 |
.minimum_version_id = 3,
|
910 |
.minimum_version_id_old = 1,
|
911 |
.load_state_old = apic_load_old, |
912 |
.fields = (VMStateField []) { |
913 |
VMSTATE_UINT32(apicbase, APICState), |
914 |
VMSTATE_UINT8(id, APICState), |
915 |
VMSTATE_UINT8(arb_id, APICState), |
916 |
VMSTATE_UINT8(tpr, APICState), |
917 |
VMSTATE_UINT32(spurious_vec, APICState), |
918 |
VMSTATE_UINT8(log_dest, APICState), |
919 |
VMSTATE_UINT8(dest_mode, APICState), |
920 |
VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
921 |
VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
922 |
VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
923 |
VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
924 |
VMSTATE_UINT32(esr, APICState), |
925 |
VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
926 |
VMSTATE_UINT32(divide_conf, APICState), |
927 |
VMSTATE_INT32(count_shift, APICState), |
928 |
VMSTATE_UINT32(initial_count, APICState), |
929 |
VMSTATE_INT64(initial_count_load_time, APICState), |
930 |
VMSTATE_INT64(next_time, APICState), |
931 |
VMSTATE_TIMER(timer, APICState), |
932 |
VMSTATE_END_OF_LIST() |
933 |
} |
934 |
}; |
935 |
|
936 |
static void apic_reset(void *opaque) |
937 |
{ |
938 |
APICState *s = opaque; |
939 |
int bsp;
|
940 |
|
941 |
cpu_synchronize_state(s->cpu_env); |
942 |
|
943 |
bsp = cpu_is_bsp(s->cpu_env); |
944 |
s->apicbase = 0xfee00000 |
|
945 |
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
946 |
|
947 |
cpu_reset(s->cpu_env); |
948 |
apic_init_reset(s->cpu_env); |
949 |
|
950 |
if (bsp) {
|
951 |
/*
|
952 |
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
953 |
* time typically by BIOS, so PIC interrupt can be delivered to the
|
954 |
* processor when local APIC is enabled.
|
955 |
*/
|
956 |
s->lvt[APIC_LVT_LINT0] = 0x700;
|
957 |
} |
958 |
} |
959 |
|
960 |
static CPUReadMemoryFunc * const apic_mem_read[3] = { |
961 |
apic_mem_readb, |
962 |
apic_mem_readw, |
963 |
apic_mem_readl, |
964 |
}; |
965 |
|
966 |
static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
967 |
apic_mem_writeb, |
968 |
apic_mem_writew, |
969 |
apic_mem_writel, |
970 |
}; |
971 |
|
972 |
int apic_init(CPUState *env)
|
973 |
{ |
974 |
APICState *s; |
975 |
|
976 |
if (last_apic_idx >= MAX_APICS)
|
977 |
return -1; |
978 |
s = qemu_mallocz(sizeof(APICState));
|
979 |
env->apic_state = s; |
980 |
s->idx = last_apic_idx++; |
981 |
s->id = env->cpuid_apic_id; |
982 |
s->cpu_env = env; |
983 |
|
984 |
msix_supported = 1;
|
985 |
|
986 |
/* XXX: mapping more APICs at the same memory location */
|
987 |
if (apic_io_memory == 0) { |
988 |
/* NOTE: the APIC is directly connected to the CPU - it is not
|
989 |
on the global memory bus. */
|
990 |
apic_io_memory = cpu_register_io_memory(apic_mem_read, |
991 |
apic_mem_write, NULL);
|
992 |
/* XXX: what if the base changes? */
|
993 |
cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, |
994 |
apic_io_memory); |
995 |
} |
996 |
s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
997 |
|
998 |
vmstate_register(s->idx, &vmstate_apic, s); |
999 |
qemu_register_reset(apic_reset, s); |
1000 |
|
1001 |
local_apics[s->idx] = s; |
1002 |
return 0; |
1003 |
} |