Revision bc814401 target-mips/op_helper.c

b/target-mips/op_helper.c
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static void fill_tlb (int idx)
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{
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    tlb_t *tlb;
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    int size;
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    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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    tlb = &env->tlb[idx];
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    tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
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    tlb->ASID = env->CP0_EntryHi & 0xFF;
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    size = env->CP0_PageMask >> 13;
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    size = 4 * (size + 1);
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    tlb->end = tlb->VPN + (1 << (8 + size));
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    tlb->end2 = tlb->end + (1 << (8 + size));
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    tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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    tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
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    tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
......
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{
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    tlb_t *tlb;
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    uint8_t ASID;
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    int size;
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    ASID = env->CP0_EntryHi & 0xFF;
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    tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
......
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    mips_tlb_flush_extra(env, MIPS_TLB_NB);
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    env->CP0_EntryHi = tlb->VPN | tlb->ASID;
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    size = (tlb->end - tlb->VPN) >> 12;
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    env->CP0_PageMask = (size - 1) << 13;
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    env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
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                        (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
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    env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |

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