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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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#define MIPS_DEBUG_DISAS
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#define GETPC() (__builtin_return_address(0)) |
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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void do_raise_exception_err (uint32_t exception, int error_code) |
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{ |
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#if 1 |
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if (logfile && exception < 0x100) |
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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T0 = 0;
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cpu_loop_exit(); |
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} |
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void do_raise_exception (uint32_t exception)
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{ |
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do_raise_exception_err(exception, 0);
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} |
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void do_restore_state (void *pc_ptr) |
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{ |
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TranslationBlock *tb; |
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unsigned long pc = (unsigned long) pc_ptr; |
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tb = tb_find_pc (pc); |
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cpu_restore_state (tb, env, pc, NULL);
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} |
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void do_raise_exception_direct (uint32_t exception)
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{ |
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do_restore_state (GETPC ()); |
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do_raise_exception_err (exception, 0);
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} |
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#endif
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#ifdef MIPS_HAS_MIPS64
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions. */
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void do_dsll (void) |
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{ |
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T0 = T0 << T1; |
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} |
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void do_dsll32 (void) |
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{ |
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T0 = T0 << (T1 + 32);
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} |
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void do_dsra (void) |
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{ |
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T0 = (int64_t)T0 >> T1; |
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} |
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void do_dsra32 (void) |
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{ |
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T0 = (int64_t)T0 >> (T1 + 32);
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} |
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void do_dsrl (void) |
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{ |
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T0 = T0 >> T1; |
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} |
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void do_dsrl32 (void) |
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{ |
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T0 = T0 >> (T1 + 32);
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} |
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void do_drotr (void) |
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{ |
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target_ulong tmp; |
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if (T1) {
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tmp = T0 << (0x40 - T1);
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T0 = (T0 >> T1) | tmp; |
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} else
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T0 = T1; |
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} |
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void do_drotr32 (void) |
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{ |
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target_ulong tmp; |
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if (T1) {
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tmp = T0 << (0x40 - (32 + T1)); |
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T0 = (T0 >> (32 + T1)) | tmp;
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} else
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T0 = T1; |
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} |
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void do_dsllv (void) |
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{ |
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T0 = T1 << (T0 & 0x3F);
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} |
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void do_dsrav (void) |
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{ |
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T0 = (int64_t)T1 >> (T0 & 0x3F);
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} |
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void do_dsrlv (void) |
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{ |
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T0 = T1 >> (T0 & 0x3F);
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} |
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void do_drotrv (void) |
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{ |
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target_ulong tmp; |
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T0 &= 0x3F;
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if (T0) {
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tmp = T1 << (0x40 - T0);
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T0 = (T1 >> T0) | tmp; |
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} else
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T0 = T1; |
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} |
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#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
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#endif /* MIPS_HAS_MIPS64 */ |
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/* 64 bits arithmetic for 32 bits hosts */
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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static inline uint64_t get_HILO (void) |
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{ |
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return (env->HI << 32) | (uint32_t)env->LO; |
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} |
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static inline void set_HILO (uint64_t HILO) |
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{ |
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env->LO = (int32_t)HILO; |
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env->HI = (int32_t)(HILO >> 32);
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} |
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void do_mult (void) |
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{ |
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set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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} |
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void do_multu (void) |
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{ |
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set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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} |
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void do_madd (void) |
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{ |
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int64_t tmp; |
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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set_HILO((int64_t)get_HILO() + tmp); |
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} |
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void do_maddu (void) |
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{ |
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uint64_t tmp; |
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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set_HILO(get_HILO() + tmp); |
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} |
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void do_msub (void) |
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{ |
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int64_t tmp; |
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
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set_HILO((int64_t)get_HILO() - tmp); |
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} |
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void do_msubu (void) |
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{ |
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uint64_t tmp; |
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
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set_HILO(get_HILO() - tmp); |
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} |
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#endif
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#ifdef MIPS_HAS_MIPS64
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void do_dmult (void) |
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{ |
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/* XXX */
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set_HILO((int64_t)T0 * (int64_t)T1); |
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} |
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void do_dmultu (void) |
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{ |
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/* XXX */
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set_HILO((uint64_t)T0 * (uint64_t)T1); |
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} |
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void do_ddiv (void) |
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{ |
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if (T1 != 0) { |
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env->LO = (int64_t)T0 / (int64_t)T1; |
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env->HI = (int64_t)T0 % (int64_t)T1; |
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} |
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} |
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void do_ddivu (void) |
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{ |
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if (T1 != 0) { |
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env->LO = T0 / T1; |
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env->HI = T0 % T1; |
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} |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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void do_mfc0_random (void) |
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{ |
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cpu_abort(env, "mfc0 random\n");
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} |
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void do_mfc0_count (void) |
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{ |
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cpu_abort(env, "mfc0 count\n");
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} |
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void cpu_mips_store_count(CPUState *env, uint32_t value)
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{ |
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cpu_abort(env, "mtc0 count\n");
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} |
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void cpu_mips_store_compare(CPUState *env, uint32_t value)
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{ |
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cpu_abort(env, "mtc0 compare\n");
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} |
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{ |
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cpu_abort(env, "mtc0 status debug\n");
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} |
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void do_mtc0_status_irqraise_debug (void) |
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{ |
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cpu_abort(env, "mtc0 status irqraise debug\n");
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} |
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void do_tlbwi (void) |
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{ |
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cpu_abort(env, "tlbwi\n");
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} |
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void do_tlbwr (void) |
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{ |
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cpu_abort(env, "tlbwr\n");
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} |
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void do_tlbp (void) |
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{ |
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cpu_abort(env, "tlbp\n");
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} |
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void do_tlbr (void) |
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{ |
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cpu_abort(env, "tlbr\n");
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} |
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{ |
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cpu_abort(env, "mips_tlb_flush\n");
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} |
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#else
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/* CP0 helpers */
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void do_mfc0_random (void) |
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{ |
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T0 = (int32_t)cpu_mips_get_random(env); |
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} |
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void do_mfc0_count (void) |
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{ |
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T0 = (int32_t)cpu_mips_get_count(env); |
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} |
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{ |
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const uint32_t mask = 0x0000FF00; |
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fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
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old, val, env->CP0_Cause, old & mask, val & mask, |
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env->CP0_Cause & mask); |
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} |
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void do_mtc0_status_irqraise_debug(void) |
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{ |
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fprintf(logfile, "Raise pending IRQs\n");
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} |
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#ifdef MIPS_USES_FPU
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#include "softfloat.h" |
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void fpu_handle_exception(void) |
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{ |
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#ifdef CONFIG_SOFTFLOAT
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int flags = get_float_exception_flags(&env->fp_status);
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unsigned int cpuflags = 0, enable, cause = 0; |
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enable = GET_FP_ENABLE(env->fcr31); |
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/* determine current flags */
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if (flags & float_flag_invalid) {
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cpuflags |= FP_INVALID; |
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cause |= FP_INVALID & enable; |
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} |
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if (flags & float_flag_divbyzero) {
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cpuflags |= FP_DIV0; |
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cause |= FP_DIV0 & enable; |
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} |
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if (flags & float_flag_overflow) {
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cpuflags |= FP_OVERFLOW; |
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cause |= FP_OVERFLOW & enable; |
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} |
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if (flags & float_flag_underflow) {
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cpuflags |= FP_UNDERFLOW; |
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cause |= FP_UNDERFLOW & enable; |
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} |
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if (flags & float_flag_inexact) {
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cpuflags |= FP_INEXACT; |
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cause |= FP_INEXACT & enable; |
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} |
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SET_FP_FLAGS(env->fcr31, cpuflags); |
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SET_FP_CAUSE(env->fcr31, cause); |
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#else
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SET_FP_FLAGS(env->fcr31, 0);
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SET_FP_CAUSE(env->fcr31, 0);
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#endif
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} |
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#endif /* MIPS_USES_FPU */ |
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/* TLB management */
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#if defined(MIPS_USES_R4K_TLB)
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void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
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{ |
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/* Flush qemu's TLB and discard all shadowed entries. */
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tlb_flush (env, flush_global); |
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env->tlb_in_use = MIPS_TLB_NB; |
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} |
378 |
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static void mips_tlb_flush_extra (CPUState *env, int first) |
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{ |
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/* Discard entries from env->tlb[first] onwards. */
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while (env->tlb_in_use > first) {
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invalidate_tlb(env, --env->tlb_in_use, 0);
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} |
385 |
} |
386 |
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static void fill_tlb (int idx) |
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{ |
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tlb_t *tlb; |
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/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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tlb = &env->tlb[idx]; |
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tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
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tlb->ASID = env->CP0_EntryHi & 0xFF;
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tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
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tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
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tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
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tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
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tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
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tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
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tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
403 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
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} |
405 |
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void do_tlbwi (void) |
407 |
{ |
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/* Discard cached TLB entries. We could avoid doing this if the
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tlbwi is just upgrading access permissions on the current entry;
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that might be a further win. */
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mips_tlb_flush_extra (env, MIPS_TLB_NB); |
412 |
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/* Wildly undefined effects for CP0_index containing a too high value and
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MIPS_TLB_NB not being a power of two. But so does real silicon. */
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invalidate_tlb(env, env->CP0_index & (MIPS_TLB_NB - 1), 0); |
416 |
fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
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} |
418 |
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419 |
void do_tlbwr (void) |
420 |
{ |
421 |
int r = cpu_mips_get_random(env);
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422 |
|
423 |
invalidate_tlb(env, r, 1);
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424 |
fill_tlb(r); |
425 |
} |
426 |
|
427 |
void do_tlbp (void) |
428 |
{ |
429 |
tlb_t *tlb; |
430 |
target_ulong tag; |
431 |
uint8_t ASID; |
432 |
int i;
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433 |
|
434 |
tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
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ASID = env->CP0_EntryHi & 0xFF;
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for (i = 0; i < MIPS_TLB_NB; i++) { |
437 |
tlb = &env->tlb[i]; |
438 |
/* Check ASID, virtual page number & size */
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439 |
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
440 |
/* TLB match */
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441 |
env->CP0_index = i; |
442 |
break;
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443 |
} |
444 |
} |
445 |
if (i == MIPS_TLB_NB) {
|
446 |
/* No match. Discard any shadow entries, if any of them match. */
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447 |
for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
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448 |
tlb = &env->tlb[i]; |
449 |
|
450 |
/* Check ASID, virtual page number & size */
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451 |
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
452 |
mips_tlb_flush_extra (env, i); |
453 |
break;
|
454 |
} |
455 |
} |
456 |
|
457 |
env->CP0_index |= 0x80000000;
|
458 |
} |
459 |
} |
460 |
|
461 |
void do_tlbr (void) |
462 |
{ |
463 |
tlb_t *tlb; |
464 |
uint8_t ASID; |
465 |
|
466 |
ASID = env->CP0_EntryHi & 0xFF;
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467 |
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
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468 |
|
469 |
/* If this will change the current ASID, flush qemu's TLB. */
|
470 |
if (ASID != tlb->ASID)
|
471 |
cpu_mips_tlb_flush (env, 1);
|
472 |
|
473 |
mips_tlb_flush_extra(env, MIPS_TLB_NB); |
474 |
|
475 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
476 |
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
477 |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
478 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
479 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
480 |
} |
481 |
#endif
|
482 |
|
483 |
#endif /* !CONFIG_USER_ONLY */ |
484 |
|
485 |
void dump_ldst (const unsigned char *func) |
486 |
{ |
487 |
if (loglevel)
|
488 |
fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1); |
489 |
} |
490 |
|
491 |
void dump_sc (void) |
492 |
{ |
493 |
if (loglevel) {
|
494 |
fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__, |
495 |
T1, T0, env->CP0_LLAddr); |
496 |
} |
497 |
} |
498 |
|
499 |
void debug_eret (void) |
500 |
{ |
501 |
if (loglevel) {
|
502 |
fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n", |
503 |
env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
504 |
env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
505 |
} |
506 |
} |
507 |
|
508 |
void do_pmon (int function) |
509 |
{ |
510 |
function /= 2;
|
511 |
switch (function) {
|
512 |
case 2: /* TODO: char inbyte(int waitflag); */ |
513 |
if (env->gpr[4] == 0) |
514 |
env->gpr[2] = -1; |
515 |
/* Fall through */
|
516 |
case 11: /* TODO: char inbyte (void); */ |
517 |
env->gpr[2] = -1; |
518 |
break;
|
519 |
case 3: |
520 |
case 12: |
521 |
printf("%c", (char)(env->gpr[4] & 0xFF)); |
522 |
break;
|
523 |
case 17: |
524 |
break;
|
525 |
case 158: |
526 |
{ |
527 |
unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
528 |
printf("%s", fmt);
|
529 |
} |
530 |
break;
|
531 |
} |
532 |
} |
533 |
|
534 |
#if !defined(CONFIG_USER_ONLY)
|
535 |
|
536 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
537 |
|
538 |
#define MMUSUFFIX _mmu
|
539 |
#define ALIGNED_ONLY
|
540 |
|
541 |
#define SHIFT 0 |
542 |
#include "softmmu_template.h" |
543 |
|
544 |
#define SHIFT 1 |
545 |
#include "softmmu_template.h" |
546 |
|
547 |
#define SHIFT 2 |
548 |
#include "softmmu_template.h" |
549 |
|
550 |
#define SHIFT 3 |
551 |
#include "softmmu_template.h" |
552 |
|
553 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
554 |
{ |
555 |
env->CP0_BadVAddr = addr; |
556 |
do_restore_state (retaddr); |
557 |
do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
558 |
} |
559 |
|
560 |
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
561 |
{ |
562 |
TranslationBlock *tb; |
563 |
CPUState *saved_env; |
564 |
unsigned long pc; |
565 |
int ret;
|
566 |
|
567 |
/* XXX: hack to restore env in all cases, even if not called from
|
568 |
generated code */
|
569 |
saved_env = env; |
570 |
env = cpu_single_env; |
571 |
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
572 |
if (ret) {
|
573 |
if (retaddr) {
|
574 |
/* now we have a real cpu fault */
|
575 |
pc = (unsigned long)retaddr; |
576 |
tb = tb_find_pc(pc); |
577 |
if (tb) {
|
578 |
/* the PC is inside the translated code. It means that we have
|
579 |
a virtual CPU fault */
|
580 |
cpu_restore_state(tb, env, pc, NULL);
|
581 |
} |
582 |
} |
583 |
do_raise_exception_err(env->exception_index, env->error_code); |
584 |
} |
585 |
env = saved_env; |
586 |
} |
587 |
|
588 |
#endif
|