root / hw / xtensa_sim.c @ bc927e48
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1 | 47d05a86 | Max Filippov | /*
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2 | 47d05a86 | Max Filippov | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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3 | 47d05a86 | Max Filippov | * All rights reserved.
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4 | 47d05a86 | Max Filippov | *
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5 | 47d05a86 | Max Filippov | * Redistribution and use in source and binary forms, with or without
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6 | 47d05a86 | Max Filippov | * modification, are permitted provided that the following conditions are met:
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7 | 47d05a86 | Max Filippov | * * Redistributions of source code must retain the above copyright
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8 | 47d05a86 | Max Filippov | * notice, this list of conditions and the following disclaimer.
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9 | 47d05a86 | Max Filippov | * * Redistributions in binary form must reproduce the above copyright
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10 | 47d05a86 | Max Filippov | * notice, this list of conditions and the following disclaimer in the
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11 | 47d05a86 | Max Filippov | * documentation and/or other materials provided with the distribution.
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12 | 47d05a86 | Max Filippov | * * Neither the name of the Open Source and Linux Lab nor the
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13 | 47d05a86 | Max Filippov | * names of its contributors may be used to endorse or promote products
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14 | 47d05a86 | Max Filippov | * derived from this software without specific prior written permission.
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15 | 47d05a86 | Max Filippov | *
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16 | 47d05a86 | Max Filippov | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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17 | 47d05a86 | Max Filippov | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 | 47d05a86 | Max Filippov | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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19 | 47d05a86 | Max Filippov | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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20 | 47d05a86 | Max Filippov | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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21 | 47d05a86 | Max Filippov | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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22 | 47d05a86 | Max Filippov | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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23 | 47d05a86 | Max Filippov | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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24 | 47d05a86 | Max Filippov | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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25 | 47d05a86 | Max Filippov | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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26 | 47d05a86 | Max Filippov | */
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27 | 47d05a86 | Max Filippov | |
28 | 47d05a86 | Max Filippov | #include "sysemu.h" |
29 | 47d05a86 | Max Filippov | #include "boards.h" |
30 | 47d05a86 | Max Filippov | #include "loader.h" |
31 | 47d05a86 | Max Filippov | #include "elf.h" |
32 | 47d05a86 | Max Filippov | #include "memory.h" |
33 | 47d05a86 | Max Filippov | #include "exec-memory.h" |
34 | 47d05a86 | Max Filippov | |
35 | 47d05a86 | Max Filippov | static uint64_t translate_phys_addr(void *env, uint64_t addr) |
36 | 47d05a86 | Max Filippov | { |
37 | 47d05a86 | Max Filippov | return cpu_get_phys_page_debug(env, addr);
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38 | 47d05a86 | Max Filippov | } |
39 | 47d05a86 | Max Filippov | |
40 | 11e7bfd7 | Andreas Färber | static void sim_reset(void *opaque) |
41 | 47d05a86 | Max Filippov | { |
42 | 11e7bfd7 | Andreas Färber | XtensaCPU *cpu = opaque; |
43 | 11e7bfd7 | Andreas Färber | |
44 | 11e7bfd7 | Andreas Färber | cpu_reset(CPU(cpu)); |
45 | 47d05a86 | Max Filippov | } |
46 | 47d05a86 | Max Filippov | |
47 | 50cd7214 | Max Filippov | static void xtensa_sim_init(QEMUMachineInitArgs *args) |
48 | 47d05a86 | Max Filippov | { |
49 | 06d26274 | Andreas Färber | XtensaCPU *cpu = NULL;
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50 | 5bfcb36e | Andreas Färber | CPUXtensaState *env = NULL;
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51 | 47d05a86 | Max Filippov | MemoryRegion *ram, *rom; |
52 | 50cd7214 | Max Filippov | ram_addr_t ram_size = args->ram_size; |
53 | 50cd7214 | Max Filippov | const char *cpu_model = args->cpu_model; |
54 | 50cd7214 | Max Filippov | const char *kernel_filename = args->kernel_filename; |
55 | 47d05a86 | Max Filippov | int n;
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56 | 47d05a86 | Max Filippov | |
57 | 50cd7214 | Max Filippov | if (!cpu_model) {
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58 | 50cd7214 | Max Filippov | cpu_model = XTENSA_DEFAULT_CPU_MODEL; |
59 | 50cd7214 | Max Filippov | } |
60 | 50cd7214 | Max Filippov | |
61 | 47d05a86 | Max Filippov | for (n = 0; n < smp_cpus; n++) { |
62 | 06d26274 | Andreas Färber | cpu = cpu_xtensa_init(cpu_model); |
63 | 06d26274 | Andreas Färber | if (cpu == NULL) { |
64 | 47d05a86 | Max Filippov | fprintf(stderr, "Unable to find CPU definition\n");
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65 | 47d05a86 | Max Filippov | exit(1);
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66 | 47d05a86 | Max Filippov | } |
67 | 06d26274 | Andreas Färber | env = &cpu->env; |
68 | 06d26274 | Andreas Färber | |
69 | 47d05a86 | Max Filippov | env->sregs[PRID] = n; |
70 | 11e7bfd7 | Andreas Färber | qemu_register_reset(sim_reset, cpu); |
71 | 47d05a86 | Max Filippov | /* Need MMU initialized prior to ELF loading,
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72 | 47d05a86 | Max Filippov | * so that ELF gets loaded into virtual addresses
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73 | 47d05a86 | Max Filippov | */
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74 | 11e7bfd7 | Andreas Färber | sim_reset(cpu); |
75 | 47d05a86 | Max Filippov | } |
76 | 47d05a86 | Max Filippov | |
77 | 47d05a86 | Max Filippov | ram = g_malloc(sizeof(*ram));
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78 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "xtensa.sram", ram_size);
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79 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
80 | 47d05a86 | Max Filippov | memory_region_add_subregion(get_system_memory(), 0, ram);
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81 | 47d05a86 | Max Filippov | |
82 | 47d05a86 | Max Filippov | rom = g_malloc(sizeof(*rom));
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83 | c5705a77 | Avi Kivity | memory_region_init_ram(rom, "xtensa.rom", 0x1000); |
84 | c5705a77 | Avi Kivity | vmstate_register_ram_global(rom); |
85 | 47d05a86 | Max Filippov | memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
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86 | 47d05a86 | Max Filippov | |
87 | 47d05a86 | Max Filippov | if (kernel_filename) {
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88 | 47d05a86 | Max Filippov | uint64_t elf_entry; |
89 | 47d05a86 | Max Filippov | uint64_t elf_lowaddr; |
90 | 47d05a86 | Max Filippov | #ifdef TARGET_WORDS_BIGENDIAN
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91 | 47d05a86 | Max Filippov | int success = load_elf(kernel_filename, translate_phys_addr, env,
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92 | 47d05a86 | Max Filippov | &elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); |
93 | 47d05a86 | Max Filippov | #else
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94 | 47d05a86 | Max Filippov | int success = load_elf(kernel_filename, translate_phys_addr, env,
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95 | 47d05a86 | Max Filippov | &elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0); |
96 | 47d05a86 | Max Filippov | #endif
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97 | 47d05a86 | Max Filippov | if (success > 0) { |
98 | 47d05a86 | Max Filippov | env->pc = elf_entry; |
99 | 47d05a86 | Max Filippov | } |
100 | 47d05a86 | Max Filippov | } |
101 | 47d05a86 | Max Filippov | } |
102 | 47d05a86 | Max Filippov | |
103 | 5e408573 | Max Filippov | static QEMUMachine xtensa_sim_machine = {
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104 | 5e408573 | Max Filippov | .name = "sim",
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105 | e38077ff | Max Filippov | .desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")", |
106 | 82e5d464 | Max Filippov | .is_default = true,
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107 | 5e408573 | Max Filippov | .init = xtensa_sim_init, |
108 | 47d05a86 | Max Filippov | .max_cpus = 4,
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109 | 47d05a86 | Max Filippov | }; |
110 | 47d05a86 | Max Filippov | |
111 | 5e408573 | Max Filippov | static void xtensa_sim_machine_init(void) |
112 | 47d05a86 | Max Filippov | { |
113 | 5e408573 | Max Filippov | qemu_register_machine(&xtensa_sim_machine); |
114 | 47d05a86 | Max Filippov | } |
115 | 47d05a86 | Max Filippov | |
116 | 5e408573 | Max Filippov | machine_init(xtensa_sim_machine_init); |