root / target-mips / cpu.h @ bc9ed47b
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1 | 6af0bf9c | bellard | #if !defined (__MIPS_CPU_H__)
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2 | 6af0bf9c | bellard | #define __MIPS_CPU_H__
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3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | #include "mips-defs.h" |
5 | 6af0bf9c | bellard | #include "cpu-defs.h" |
6 | 6af0bf9c | bellard | #include "config.h" |
7 | 6af0bf9c | bellard | #include "softfloat.h" |
8 | 6af0bf9c | bellard | |
9 | 6af0bf9c | bellard | typedef union fpr_t fpr_t; |
10 | 6af0bf9c | bellard | union fpr_t {
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11 | 6af0bf9c | bellard | double d;
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12 | 6af0bf9c | bellard | float f;
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13 | 6af0bf9c | bellard | uint32_t u[2];
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14 | 6af0bf9c | bellard | }; |
15 | 6af0bf9c | bellard | |
16 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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17 | 6af0bf9c | bellard | typedef struct tlb_t tlb_t; |
18 | 6af0bf9c | bellard | struct tlb_t {
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19 | 6af0bf9c | bellard | target_ulong VPN; |
20 | 6af0bf9c | bellard | target_ulong end; |
21 | 6af0bf9c | bellard | uint8_t ASID; |
22 | 6af0bf9c | bellard | uint8_t G; |
23 | 6af0bf9c | bellard | uint8_t C[2];
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24 | 6af0bf9c | bellard | uint8_t V[2];
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25 | 6af0bf9c | bellard | uint8_t D[2];
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26 | 6af0bf9c | bellard | target_ulong PFN[2];
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27 | 6af0bf9c | bellard | }; |
28 | 6af0bf9c | bellard | #endif
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29 | 6af0bf9c | bellard | |
30 | 6af0bf9c | bellard | typedef struct CPUMIPSState CPUMIPSState; |
31 | 6af0bf9c | bellard | struct CPUMIPSState {
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32 | 6af0bf9c | bellard | /* General integer registers */
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33 | 6af0bf9c | bellard | target_ulong gpr[32];
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34 | 6af0bf9c | bellard | /* Special registers */
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35 | 6af0bf9c | bellard | target_ulong PC; |
36 | 6af0bf9c | bellard | uint32_t HI, LO; |
37 | 6af0bf9c | bellard | uint32_t DCR; /* ? */
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38 | 6af0bf9c | bellard | #if defined(MIPS_USES_FPU)
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39 | 6af0bf9c | bellard | /* Floating point registers */
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40 | 6af0bf9c | bellard | fpr_t fpr[16];
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41 | 6af0bf9c | bellard | /* Floating point special purpose registers */
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42 | 6af0bf9c | bellard | uint32_t fcr0; |
43 | 6af0bf9c | bellard | uint32_t fcr25; |
44 | 6af0bf9c | bellard | uint32_t fcr26; |
45 | 6af0bf9c | bellard | uint32_t fcr28; |
46 | 6af0bf9c | bellard | uint32_t fcsr; |
47 | 6af0bf9c | bellard | #endif
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48 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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49 | 6af0bf9c | bellard | tlb_t tlb[16];
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50 | 6af0bf9c | bellard | #endif
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51 | 6af0bf9c | bellard | uint32_t CP0_index; |
52 | 6af0bf9c | bellard | uint32_t CP0_random; |
53 | 6af0bf9c | bellard | uint32_t CP0_EntryLo0; |
54 | 6af0bf9c | bellard | uint32_t CP0_EntryLo1; |
55 | 6af0bf9c | bellard | uint32_t CP0_Context; |
56 | 6af0bf9c | bellard | uint32_t CP0_PageMask; |
57 | 6af0bf9c | bellard | uint32_t CP0_Wired; |
58 | 6af0bf9c | bellard | uint32_t CP0_BadVAddr; |
59 | 6af0bf9c | bellard | uint32_t CP0_Count; |
60 | 6af0bf9c | bellard | uint32_t CP0_EntryHi; |
61 | 6af0bf9c | bellard | uint32_t CP0_Compare; |
62 | 6af0bf9c | bellard | uint32_t CP0_Status; |
63 | 6af0bf9c | bellard | #define CP0St_CU3 31 |
64 | 6af0bf9c | bellard | #define CP0St_CU2 30 |
65 | 6af0bf9c | bellard | #define CP0St_CU1 29 |
66 | 6af0bf9c | bellard | #define CP0St_CU0 28 |
67 | 6af0bf9c | bellard | #define CP0St_RP 27 |
68 | 6af0bf9c | bellard | #define CP0St_RE 25 |
69 | 6af0bf9c | bellard | #define CP0St_BEV 22 |
70 | 6af0bf9c | bellard | #define CP0St_TS 21 |
71 | 6af0bf9c | bellard | #define CP0St_SR 20 |
72 | 6af0bf9c | bellard | #define CP0St_NMI 19 |
73 | 6af0bf9c | bellard | #define CP0St_IM 8 |
74 | 6af0bf9c | bellard | #define CP0St_UM 4 |
75 | 6af0bf9c | bellard | #define CP0St_ERL 2 |
76 | 6af0bf9c | bellard | #define CP0St_EXL 1 |
77 | 6af0bf9c | bellard | #define CP0St_IE 0 |
78 | 6af0bf9c | bellard | uint32_t CP0_Cause; |
79 | 6af0bf9c | bellard | #define CP0Ca_IV 23 |
80 | 6af0bf9c | bellard | uint32_t CP0_EPC; |
81 | 6af0bf9c | bellard | uint32_t CP0_PRid; |
82 | 6af0bf9c | bellard | uint32_t CP0_Config0; |
83 | 6af0bf9c | bellard | #define CP0C0_M 31 |
84 | 6af0bf9c | bellard | #define CP0C0_K23 28 |
85 | 6af0bf9c | bellard | #define CP0C0_KU 25 |
86 | 6af0bf9c | bellard | #define CP0C0_MDU 20 |
87 | 6af0bf9c | bellard | #define CP0C0_MM 17 |
88 | 6af0bf9c | bellard | #define CP0C0_BM 16 |
89 | 6af0bf9c | bellard | #define CP0C0_BE 15 |
90 | 6af0bf9c | bellard | #define CP0C0_AT 13 |
91 | 6af0bf9c | bellard | #define CP0C0_AR 10 |
92 | 6af0bf9c | bellard | #define CP0C0_MT 7 |
93 | 6af0bf9c | bellard | #define CP0C0_K0 0 |
94 | 6af0bf9c | bellard | uint32_t CP0_Config1; |
95 | 6af0bf9c | bellard | #define CP0C1_MMU 25 |
96 | 6af0bf9c | bellard | #define CP0C1_IS 22 |
97 | 6af0bf9c | bellard | #define CP0C1_IL 19 |
98 | 6af0bf9c | bellard | #define CP0C1_IA 16 |
99 | 6af0bf9c | bellard | #define CP0C1_DS 13 |
100 | 6af0bf9c | bellard | #define CP0C1_DL 10 |
101 | 6af0bf9c | bellard | #define CP0C1_DA 7 |
102 | 6af0bf9c | bellard | #define CP0C1_PC 4 |
103 | 6af0bf9c | bellard | #define CP0C1_WR 3 |
104 | 6af0bf9c | bellard | #define CP0C1_CA 2 |
105 | 6af0bf9c | bellard | #define CP0C1_EP 1 |
106 | 6af0bf9c | bellard | #define CP0C1_FP 0 |
107 | 6af0bf9c | bellard | uint32_t CP0_LLAddr; |
108 | 6af0bf9c | bellard | uint32_t CP0_WatchLo; |
109 | 6af0bf9c | bellard | uint32_t CP0_WatchHi; |
110 | 6af0bf9c | bellard | uint32_t CP0_Debug; |
111 | 6af0bf9c | bellard | #define CPDB_DBD 31 |
112 | 6af0bf9c | bellard | #define CP0DB_DM 30 |
113 | 6af0bf9c | bellard | #define CP0DB_LSNM 28 |
114 | 6af0bf9c | bellard | #define CP0DB_Doze 27 |
115 | 6af0bf9c | bellard | #define CP0DB_Halt 26 |
116 | 6af0bf9c | bellard | #define CP0DB_CNT 25 |
117 | 6af0bf9c | bellard | #define CP0DB_IBEP 24 |
118 | 6af0bf9c | bellard | #define CP0DB_DBEP 21 |
119 | 6af0bf9c | bellard | #define CP0DB_IEXI 20 |
120 | 6af0bf9c | bellard | #define CP0DB_VER 15 |
121 | 6af0bf9c | bellard | #define CP0DB_DEC 10 |
122 | 6af0bf9c | bellard | #define CP0DB_SSt 8 |
123 | 6af0bf9c | bellard | #define CP0DB_DINT 5 |
124 | 6af0bf9c | bellard | #define CP0DB_DIB 4 |
125 | 6af0bf9c | bellard | #define CP0DB_DDBS 3 |
126 | 6af0bf9c | bellard | #define CP0DB_DDBL 2 |
127 | 6af0bf9c | bellard | #define CP0DB_DBp 1 |
128 | 6af0bf9c | bellard | #define CP0DB_DSS 0 |
129 | 6af0bf9c | bellard | uint32_t CP0_DEPC; |
130 | 6af0bf9c | bellard | uint32_t CP0_TagLo; |
131 | 6af0bf9c | bellard | uint32_t CP0_DataLo; |
132 | 6af0bf9c | bellard | uint32_t CP0_ErrorEPC; |
133 | 6af0bf9c | bellard | uint32_t CP0_DESAVE; |
134 | 6af0bf9c | bellard | /* Qemu */
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135 | 6af0bf9c | bellard | #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
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136 | 6af0bf9c | bellard | double ft0, ft1, ft2;
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137 | 6af0bf9c | bellard | #endif
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138 | 6af0bf9c | bellard | struct QEMUTimer *timer; /* Internal timer */ |
139 | 6af0bf9c | bellard | int interrupt_request;
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140 | 6af0bf9c | bellard | jmp_buf jmp_env; |
141 | 6af0bf9c | bellard | int exception_index;
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142 | 6af0bf9c | bellard | int error_code;
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143 | 6af0bf9c | bellard | int user_mode_only; /* user mode only simulation */ |
144 | 6af0bf9c | bellard | uint32_t hflags; /* CPU State */
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145 | 6af0bf9c | bellard | /* TMASK defines different execution modes */
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146 | 6af0bf9c | bellard | #define MIPS_HFLAGS_TMASK 0x00FF |
147 | 6af0bf9c | bellard | #define MIPS_HFLAG_MODE 0x001F /* execution modes */ |
148 | 6af0bf9c | bellard | #define MIPS_HFLAG_UM 0x0001 /* user mode */ |
149 | 6af0bf9c | bellard | #define MIPS_HFLAG_ERL 0x0002 /* Error mode */ |
150 | 6af0bf9c | bellard | #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */ |
151 | 6af0bf9c | bellard | #define MIPS_HFLAG_DM 0x0008 /* Debug mode */ |
152 | 6af0bf9c | bellard | #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ |
153 | 6af0bf9c | bellard | #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ |
154 | 6af0bf9c | bellard | #define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */ |
155 | 6af0bf9c | bellard | /* Those flags keep the branch state if the translation is interrupted
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156 | 6af0bf9c | bellard | * between the branch instruction and the delay slot
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157 | 6af0bf9c | bellard | */
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158 | 6af0bf9c | bellard | #define MIPS_HFLAG_BMASK 0x0F00 |
159 | 6af0bf9c | bellard | #define MIPS_HFLAG_B 0x0100 /* Unconditional branch */ |
160 | 6af0bf9c | bellard | #define MIPS_HFLAG_BC 0x0200 /* Conditional branch */ |
161 | 6af0bf9c | bellard | #define MIPS_HFLAG_BL 0x0400 /* Likely branch */ |
162 | 6af0bf9c | bellard | #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */ |
163 | 6af0bf9c | bellard | target_ulong btarget; /* Jump / branch target */
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164 | 6af0bf9c | bellard | int bcond; /* Branch condition (if needed) */ |
165 | 6af0bf9c | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
166 | 6af0bf9c | bellard | /* soft mmu support */
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167 | 6af0bf9c | bellard | /* in order to avoid passing too many arguments to the memory
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168 | 6af0bf9c | bellard | write helpers, we store some rarely used information in the CPU
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169 | 6af0bf9c | bellard | context) */
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170 | 6af0bf9c | bellard | target_ulong mem_write_pc; /* host pc at which the memory was
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171 | 6af0bf9c | bellard | written */
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172 | 6af0bf9c | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
173 | 6af0bf9c | bellard | memory was written */
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174 | 6af0bf9c | bellard | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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175 | 6af0bf9c | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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176 | 6af0bf9c | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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177 | 6af0bf9c | bellard | /* ice debug support */
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178 | 6af0bf9c | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; |
179 | 6af0bf9c | bellard | int nb_breakpoints;
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180 | 6af0bf9c | bellard | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
181 | 6af0bf9c | bellard | /* user data */
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182 | 6af0bf9c | bellard | void *opaque;
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183 | 6af0bf9c | bellard | }; |
184 | 6af0bf9c | bellard | |
185 | 6af0bf9c | bellard | #include "cpu-all.h" |
186 | 6af0bf9c | bellard | |
187 | 6af0bf9c | bellard | /* Memory access type :
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188 | 6af0bf9c | bellard | * may be needed for precise access rights control and precise exceptions.
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189 | 6af0bf9c | bellard | */
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190 | 6af0bf9c | bellard | enum {
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191 | 6af0bf9c | bellard | /* 1 bit to define user level / supervisor access */
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192 | 6af0bf9c | bellard | ACCESS_USER = 0x00,
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193 | 6af0bf9c | bellard | ACCESS_SUPER = 0x01,
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194 | 6af0bf9c | bellard | /* 1 bit to indicate direction */
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195 | 6af0bf9c | bellard | ACCESS_STORE = 0x02,
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196 | 6af0bf9c | bellard | /* Type of instruction that generated the access */
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197 | 6af0bf9c | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
198 | 6af0bf9c | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
199 | 6af0bf9c | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
200 | 6af0bf9c | bellard | }; |
201 | 6af0bf9c | bellard | |
202 | 6af0bf9c | bellard | /* Exceptions */
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203 | 6af0bf9c | bellard | enum {
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204 | 6af0bf9c | bellard | EXCP_NONE = -1,
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205 | 6af0bf9c | bellard | EXCP_RESET = 0,
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206 | 6af0bf9c | bellard | EXCP_SRESET, |
207 | 6af0bf9c | bellard | EXCP_DSS, |
208 | 6af0bf9c | bellard | EXCP_DINT, |
209 | 6af0bf9c | bellard | EXCP_NMI, |
210 | 6af0bf9c | bellard | EXCP_MCHECK, |
211 | 6af0bf9c | bellard | EXCP_EXT_INTERRUPT, |
212 | 6af0bf9c | bellard | EXCP_DFWATCH, |
213 | 6af0bf9c | bellard | EXCP_DIB, /* 8 */
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214 | 6af0bf9c | bellard | EXCP_IWATCH, |
215 | 6af0bf9c | bellard | EXCP_AdEL, |
216 | 6af0bf9c | bellard | EXCP_AdES, |
217 | 6af0bf9c | bellard | EXCP_TLBF, |
218 | 6af0bf9c | bellard | EXCP_IBE, |
219 | 6af0bf9c | bellard | EXCP_DBp, |
220 | 6af0bf9c | bellard | EXCP_SYSCALL, |
221 | 6af0bf9c | bellard | EXCP_BREAK, |
222 | 6af0bf9c | bellard | EXCP_CpU, /* 16 */
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223 | 6af0bf9c | bellard | EXCP_RI, |
224 | 6af0bf9c | bellard | EXCP_OVERFLOW, |
225 | 6af0bf9c | bellard | EXCP_TRAP, |
226 | 6af0bf9c | bellard | EXCP_DDBS, |
227 | 6af0bf9c | bellard | EXCP_DWATCH, |
228 | 6af0bf9c | bellard | EXCP_LAE, /* 22 */
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229 | 6af0bf9c | bellard | EXCP_SAE, |
230 | 6af0bf9c | bellard | EXCP_LTLBL, |
231 | 6af0bf9c | bellard | EXCP_TLBL, |
232 | 6af0bf9c | bellard | EXCP_TLBS, |
233 | 6af0bf9c | bellard | EXCP_DBE, |
234 | 6af0bf9c | bellard | EXCP_DDBL, |
235 | 6af0bf9c | bellard | EXCP_MTCP0 = 0x104, /* mtmsr instruction: */ |
236 | 6af0bf9c | bellard | /* may change privilege level */
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237 | 6af0bf9c | bellard | EXCP_BRANCH = 0x108, /* branch instruction */ |
238 | 6af0bf9c | bellard | EXCP_ERET = 0x10C, /* return from interrupt */ |
239 | 6af0bf9c | bellard | EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
240 | 6af0bf9c | bellard | EXCP_FLUSH = 0x109,
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241 | 6af0bf9c | bellard | }; |
242 | 6af0bf9c | bellard | |
243 | 6af0bf9c | bellard | /* MIPS opcodes */
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244 | 6af0bf9c | bellard | #define EXT_SPECIAL 0x100 |
245 | 6af0bf9c | bellard | #define EXT_SPECIAL2 0x200 |
246 | 6af0bf9c | bellard | #define EXT_REGIMM 0x300 |
247 | 6af0bf9c | bellard | #define EXT_CP0 0x400 |
248 | 6af0bf9c | bellard | #define EXT_CP1 0x500 |
249 | 6af0bf9c | bellard | #define EXT_CP2 0x600 |
250 | 6af0bf9c | bellard | #define EXT_CP3 0x700 |
251 | 6af0bf9c | bellard | |
252 | 6af0bf9c | bellard | enum {
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253 | 6af0bf9c | bellard | /* indirect opcode tables */
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254 | 6af0bf9c | bellard | OPC_SPECIAL = 0x00,
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255 | 6af0bf9c | bellard | OPC_BREGIMM = 0x01,
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256 | 6af0bf9c | bellard | OPC_CP0 = 0x10,
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257 | 6af0bf9c | bellard | OPC_CP1 = 0x11,
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258 | 6af0bf9c | bellard | OPC_CP2 = 0x12,
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259 | 6af0bf9c | bellard | OPC_CP3 = 0x13,
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260 | 6af0bf9c | bellard | OPC_SPECIAL2 = 0x1C,
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261 | 6af0bf9c | bellard | /* arithmetic with immediate */
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262 | 6af0bf9c | bellard | OPC_ADDI = 0x08,
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263 | 6af0bf9c | bellard | OPC_ADDIU = 0x09,
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264 | 6af0bf9c | bellard | OPC_SLTI = 0x0A,
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265 | 6af0bf9c | bellard | OPC_SLTIU = 0x0B,
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266 | 6af0bf9c | bellard | OPC_ANDI = 0x0C,
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267 | 6af0bf9c | bellard | OPC_ORI = 0x0D,
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268 | 6af0bf9c | bellard | OPC_XORI = 0x0E,
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269 | 6af0bf9c | bellard | OPC_LUI = 0x0F,
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270 | 6af0bf9c | bellard | /* Jump and branches */
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271 | 6af0bf9c | bellard | OPC_J = 0x02,
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272 | 6af0bf9c | bellard | OPC_JAL = 0x03,
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273 | 6af0bf9c | bellard | OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */ |
274 | 6af0bf9c | bellard | OPC_BEQL = 0x14,
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275 | 6af0bf9c | bellard | OPC_BNE = 0x05,
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276 | 6af0bf9c | bellard | OPC_BNEL = 0x15,
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277 | 6af0bf9c | bellard | OPC_BLEZ = 0x06,
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278 | 6af0bf9c | bellard | OPC_BLEZL = 0x16,
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279 | 6af0bf9c | bellard | OPC_BGTZ = 0x07,
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280 | 6af0bf9c | bellard | OPC_BGTZL = 0x17,
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281 | 6af0bf9c | bellard | OPC_JALX = 0x1D, /* MIPS 16 only */ |
282 | 6af0bf9c | bellard | /* Load and stores */
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283 | 6af0bf9c | bellard | OPC_LB = 0x20,
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284 | 6af0bf9c | bellard | OPC_LH = 0x21,
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285 | 6af0bf9c | bellard | OPC_LWL = 0x22,
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286 | 6af0bf9c | bellard | OPC_LW = 0x23,
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287 | 6af0bf9c | bellard | OPC_LBU = 0x24,
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288 | 6af0bf9c | bellard | OPC_LHU = 0x25,
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289 | 6af0bf9c | bellard | OPC_LWR = 0x26,
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290 | 6af0bf9c | bellard | OPC_SB = 0x28,
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291 | 6af0bf9c | bellard | OPC_SH = 0x29,
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292 | 6af0bf9c | bellard | OPC_SWL = 0x2A,
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293 | 6af0bf9c | bellard | OPC_SW = 0x2B,
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294 | 6af0bf9c | bellard | OPC_SWR = 0x2E,
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295 | 6af0bf9c | bellard | OPC_LL = 0x30,
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296 | 6af0bf9c | bellard | OPC_SC = 0x38,
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297 | 6af0bf9c | bellard | /* Floating point load/store */
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298 | 6af0bf9c | bellard | OPC_LWC1 = 0x31,
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299 | 6af0bf9c | bellard | OPC_LWC2 = 0x32,
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300 | 6af0bf9c | bellard | OPC_LDC1 = 0x35,
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301 | 6af0bf9c | bellard | OPC_LDC2 = 0x36,
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302 | 6af0bf9c | bellard | OPC_SWC1 = 0x39,
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303 | 6af0bf9c | bellard | OPC_SWC2 = 0x3A,
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304 | 6af0bf9c | bellard | OPC_SDC1 = 0x3D,
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305 | 6af0bf9c | bellard | OPC_SDC2 = 0x3E,
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306 | 6af0bf9c | bellard | /* Cache and prefetch */
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307 | 6af0bf9c | bellard | OPC_CACHE = 0x2F,
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308 | 6af0bf9c | bellard | OPC_PREF = 0x33,
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309 | 6af0bf9c | bellard | }; |
310 | 6af0bf9c | bellard | |
311 | 6af0bf9c | bellard | /* MIPS special opcodes */
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312 | 6af0bf9c | bellard | enum {
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313 | 6af0bf9c | bellard | /* Shifts */
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314 | 6af0bf9c | bellard | OPC_SLL = 0x00 | EXT_SPECIAL,
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315 | 6af0bf9c | bellard | /* NOP is SLL r0, r0, 0 */
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316 | 6af0bf9c | bellard | /* SSNOP is SLL r0, r0, 1 */
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317 | 6af0bf9c | bellard | OPC_SRL = 0x02 | EXT_SPECIAL,
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318 | 6af0bf9c | bellard | OPC_SRA = 0x03 | EXT_SPECIAL,
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319 | 6af0bf9c | bellard | OPC_SLLV = 0x04 | EXT_SPECIAL,
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320 | 6af0bf9c | bellard | OPC_SRLV = 0x06 | EXT_SPECIAL,
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321 | 6af0bf9c | bellard | OPC_SRAV = 0x07 | EXT_SPECIAL,
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322 | 6af0bf9c | bellard | /* Multiplication / division */
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323 | 6af0bf9c | bellard | OPC_MULT = 0x18 | EXT_SPECIAL,
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324 | 6af0bf9c | bellard | OPC_MULTU = 0x19 | EXT_SPECIAL,
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325 | 6af0bf9c | bellard | OPC_DIV = 0x1A | EXT_SPECIAL,
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326 | 6af0bf9c | bellard | OPC_DIVU = 0x1B | EXT_SPECIAL,
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327 | 6af0bf9c | bellard | /* 2 registers arithmetic / logic */
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328 | 6af0bf9c | bellard | OPC_ADD = 0x20 | EXT_SPECIAL,
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329 | 6af0bf9c | bellard | OPC_ADDU = 0x21 | EXT_SPECIAL,
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330 | 6af0bf9c | bellard | OPC_SUB = 0x22 | EXT_SPECIAL,
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331 | 6af0bf9c | bellard | OPC_SUBU = 0x23 | EXT_SPECIAL,
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332 | 6af0bf9c | bellard | OPC_AND = 0x24 | EXT_SPECIAL,
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333 | 6af0bf9c | bellard | OPC_OR = 0x25 | EXT_SPECIAL,
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334 | 6af0bf9c | bellard | OPC_XOR = 0x26 | EXT_SPECIAL,
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335 | 6af0bf9c | bellard | OPC_NOR = 0x27 | EXT_SPECIAL,
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336 | 6af0bf9c | bellard | OPC_SLT = 0x2A | EXT_SPECIAL,
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337 | 6af0bf9c | bellard | OPC_SLTU = 0x2B | EXT_SPECIAL,
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338 | 6af0bf9c | bellard | /* Jumps */
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339 | 6af0bf9c | bellard | OPC_JR = 0x08 | EXT_SPECIAL,
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340 | 6af0bf9c | bellard | OPC_JALR = 0x09 | EXT_SPECIAL,
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341 | 6af0bf9c | bellard | /* Traps */
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342 | 6af0bf9c | bellard | OPC_TGE = 0x30 | EXT_SPECIAL,
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343 | 6af0bf9c | bellard | OPC_TGEU = 0x31 | EXT_SPECIAL,
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344 | 6af0bf9c | bellard | OPC_TLT = 0x32 | EXT_SPECIAL,
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345 | 6af0bf9c | bellard | OPC_TLTU = 0x33 | EXT_SPECIAL,
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346 | 6af0bf9c | bellard | OPC_TEQ = 0x34 | EXT_SPECIAL,
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347 | 6af0bf9c | bellard | OPC_TNE = 0x36 | EXT_SPECIAL,
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348 | 6af0bf9c | bellard | /* HI / LO registers load & stores */
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349 | 6af0bf9c | bellard | OPC_MFHI = 0x10 | EXT_SPECIAL,
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350 | 6af0bf9c | bellard | OPC_MTHI = 0x11 | EXT_SPECIAL,
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351 | 6af0bf9c | bellard | OPC_MFLO = 0x12 | EXT_SPECIAL,
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352 | 6af0bf9c | bellard | OPC_MTLO = 0x13 | EXT_SPECIAL,
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353 | 6af0bf9c | bellard | /* Conditional moves */
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354 | 6af0bf9c | bellard | OPC_MOVZ = 0x0A | EXT_SPECIAL,
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355 | 6af0bf9c | bellard | OPC_MOVN = 0x0B | EXT_SPECIAL,
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356 | 6af0bf9c | bellard | |
357 | 6af0bf9c | bellard | OPC_MOVCI = 0x01 | EXT_SPECIAL,
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358 | 6af0bf9c | bellard | |
359 | 6af0bf9c | bellard | /* Special */
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360 | 6af0bf9c | bellard | OPC_PMON = 0x05 | EXT_SPECIAL,
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361 | 6af0bf9c | bellard | OPC_SYSCALL = 0x0C | EXT_SPECIAL,
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362 | 6af0bf9c | bellard | OPC_BREAK = 0x0D | EXT_SPECIAL,
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363 | 6af0bf9c | bellard | OPC_SYNC = 0x0F | EXT_SPECIAL,
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364 | 6af0bf9c | bellard | }; |
365 | 6af0bf9c | bellard | |
366 | 6af0bf9c | bellard | enum {
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367 | 6af0bf9c | bellard | /* Mutiply & xxx operations */
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368 | 6af0bf9c | bellard | OPC_MADD = 0x00 | EXT_SPECIAL2,
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369 | 6af0bf9c | bellard | OPC_MADDU = 0x01 | EXT_SPECIAL2,
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370 | 6af0bf9c | bellard | OPC_MUL = 0x02 | EXT_SPECIAL2,
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371 | 6af0bf9c | bellard | OPC_MSUB = 0x04 | EXT_SPECIAL2,
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372 | 6af0bf9c | bellard | OPC_MSUBU = 0x05 | EXT_SPECIAL2,
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373 | 6af0bf9c | bellard | /* Misc */
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374 | 6af0bf9c | bellard | OPC_CLZ = 0x20 | EXT_SPECIAL2,
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375 | 6af0bf9c | bellard | OPC_CLO = 0x21 | EXT_SPECIAL2,
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376 | 6af0bf9c | bellard | /* Special */
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377 | 6af0bf9c | bellard | OPC_SDBBP = 0x3F | EXT_SPECIAL2,
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378 | 6af0bf9c | bellard | }; |
379 | 6af0bf9c | bellard | |
380 | 6af0bf9c | bellard | /* Branch REGIMM */
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381 | 6af0bf9c | bellard | enum {
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382 | 6af0bf9c | bellard | OPC_BLTZ = 0x00 | EXT_REGIMM,
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383 | 6af0bf9c | bellard | OPC_BLTZL = 0x02 | EXT_REGIMM,
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384 | 6af0bf9c | bellard | OPC_BGEZ = 0x01 | EXT_REGIMM,
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385 | 6af0bf9c | bellard | OPC_BGEZL = 0x03 | EXT_REGIMM,
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386 | 6af0bf9c | bellard | OPC_BLTZAL = 0x10 | EXT_REGIMM,
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387 | 6af0bf9c | bellard | OPC_BLTZALL = 0x12 | EXT_REGIMM,
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388 | 6af0bf9c | bellard | OPC_BGEZAL = 0x11 | EXT_REGIMM,
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389 | 6af0bf9c | bellard | OPC_BGEZALL = 0x13 | EXT_REGIMM,
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390 | 6af0bf9c | bellard | OPC_TGEI = 0x08 | EXT_REGIMM,
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391 | 6af0bf9c | bellard | OPC_TGEIU = 0x09 | EXT_REGIMM,
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392 | 6af0bf9c | bellard | OPC_TLTI = 0x0A | EXT_REGIMM,
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393 | 6af0bf9c | bellard | OPC_TLTIU = 0x0B | EXT_REGIMM,
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394 | 6af0bf9c | bellard | OPC_TEQI = 0x0C | EXT_REGIMM,
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395 | 6af0bf9c | bellard | OPC_TNEI = 0x0E | EXT_REGIMM,
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396 | 6af0bf9c | bellard | }; |
397 | 6af0bf9c | bellard | |
398 | 6af0bf9c | bellard | enum {
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399 | 6af0bf9c | bellard | /* Coprocessor 0 (MMU) */
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400 | 6af0bf9c | bellard | OPC_MFC0 = 0x00 | EXT_CP0,
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401 | 6af0bf9c | bellard | OPC_MTC0 = 0x04 | EXT_CP0,
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402 | 6af0bf9c | bellard | OPC_TLBR = 0x01 | EXT_CP0,
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403 | 6af0bf9c | bellard | OPC_TLBWI = 0x02 | EXT_CP0,
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404 | 6af0bf9c | bellard | OPC_TLBWR = 0x06 | EXT_CP0,
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405 | 6af0bf9c | bellard | OPC_TLBP = 0x08 | EXT_CP0,
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406 | 6af0bf9c | bellard | OPC_ERET = 0x18 | EXT_CP0,
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407 | 6af0bf9c | bellard | OPC_DERET = 0x1F | EXT_CP0,
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408 | 6af0bf9c | bellard | OPC_WAIT = 0x20 | EXT_CP0,
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409 | 6af0bf9c | bellard | }; |
410 | 6af0bf9c | bellard | |
411 | 6af0bf9c | bellard | int cpu_mips_exec(CPUMIPSState *s);
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412 | 6af0bf9c | bellard | CPUMIPSState *cpu_mips_init(void);
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413 | 6af0bf9c | bellard | uint32_t cpu_mips_get_clock (void);
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414 | 6af0bf9c | bellard | |
415 | 6af0bf9c | bellard | #endif /* !defined (__MIPS_CPU_H__) */ |