target-openrisc: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new openrisc_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_OPENRISC_CPU....
target-openrisc: Drop OpenRISCCPUList
It was missed in 92a3136174f60ee45b113296cb2c2a5225b00369 (cpu:Introduce CPUListState struct) because its naming did not match the*CPUListState pattern. Use the generalized CPUListState instead.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-openrisc: Clean up triple QOM casts
Instead of calling openrisc_env_get_cpu(), casting to CPU via theENV_GET_CPU() compatibility macro and casting back to OPENRISC_CPU(),just call openrisc_env_get_cpu() directly.
ENV_GET_CPU() is meant as workaround for target-independent code only....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
qom: move include files to include/qom/
qapi: move include files to include/qobject/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
target-openrisc: remove conflicting definitions from cpu.h
On an ARM host, the registers definitions from cpu.h clashwith /usr/include/sys/ucontext.h. As there are unused, just removethem.
Cc: Jia Liu <proljc@gmail.com>Cc: qemu-stable@nongnu.orgReviewed-by: Peter Maydell <peter.maydell@linaro.org>...
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-or32: Add linux user support
Add QEMU OpenRISC linux user support.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-or32: Add system instructions
Add OpenRISC system instructions.
target-or32: Add timer support
Add OpenRISC timer support.
target-or32: Add PIC support
Add OpenRISC Programmable Interrupt Controller support.
target-or32: Add float instruction helpers
Add OpenRISC float instruction helpers.
target-or32: Add instruction translation
Add OpenRISC instruction tanslation routines.
target-or32: Add int instruction helpers
Add OpenRISC int instruction helpers.
target-or32: Add exception support
Add OpenRISC exception support.
target-or32: Add interrupt support
Add OpenRISC interrupt support.
target-or32: Add MMU support
Add OpenRISC MMU support.
target-or32: Add target stubs and QOM cpu
Add OpenRISC target stubs, QOM cpu and basic machine.