Revision bd568f18
b/target-ppc/op.c | ||
---|---|---|
46 | 46 |
do_raise_exception_err(PARAM1, PARAM2); |
47 | 47 |
} |
48 | 48 |
|
49 |
void OPPROTO op_update_nip (void) |
|
50 |
{ |
|
51 |
env->nip = (uint32_t)PARAM1; |
|
52 |
RETURN(); |
|
53 |
} |
|
54 |
|
|
55 |
#if defined(TARGET_PPC64) |
|
56 |
void OPPROTO op_update_nip_64 (void) |
|
57 |
{ |
|
58 |
env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; |
|
59 |
RETURN(); |
|
60 |
} |
|
61 |
#endif |
|
62 |
|
|
63 | 49 |
void OPPROTO op_debug (void) |
64 | 50 |
{ |
65 | 51 |
do_raise_exception(EXCP_DEBUG); |
... | ... | |
465 | 451 |
} |
466 | 452 |
|
467 | 453 |
/* Branch */ |
468 |
#define EIP env->nip |
|
469 |
|
|
470 | 454 |
void OPPROTO op_setlr (void) |
471 | 455 |
{ |
472 | 456 |
env->lr = (uint32_t)PARAM1; |
... | ... | |
481 | 465 |
} |
482 | 466 |
#endif |
483 | 467 |
|
484 |
void OPPROTO op_b_T1 (void) |
|
485 |
{ |
|
486 |
env->nip = (uint32_t)(T1 & ~3); |
|
487 |
RETURN(); |
|
488 |
} |
|
489 |
|
|
490 |
#if defined (TARGET_PPC64) |
|
491 |
void OPPROTO op_b_T1_64 (void) |
|
492 |
{ |
|
493 |
env->nip = (uint64_t)(T1 & ~3); |
|
494 |
RETURN(); |
|
495 |
} |
|
496 |
#endif |
|
497 |
|
|
498 | 468 |
void OPPROTO op_jz_T0 (void) |
499 | 469 |
{ |
500 | 470 |
if (!T0) |
b/target-ppc/translate.c | ||
---|---|---|
60 | 60 |
static TCGv cpu_fpr[32]; |
61 | 61 |
static TCGv cpu_avrh[32], cpu_avrl[32]; |
62 | 62 |
static TCGv cpu_crf[8]; |
63 |
static TCGv cpu_nip; |
|
63 | 64 |
|
64 | 65 |
/* dyngen register indexes */ |
65 | 66 |
static TCGv cpu_T[3]; |
... | ... | |
164 | 165 |
p += (i < 10) ? 6 : 7; |
165 | 166 |
} |
166 | 167 |
|
168 |
cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
|
169 |
offsetof(CPUState, nip), "nip"); |
|
170 |
|
|
167 | 171 |
/* register helpers */ |
168 | 172 |
#undef DEF_HELPER |
169 | 173 |
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
... | ... | |
268 | 272 |
{ |
269 | 273 |
#if defined(TARGET_PPC64) |
270 | 274 |
if (ctx->sf_mode) |
271 |
gen_op_update_nip_64(nip >> 32, nip);
|
|
275 |
tcg_gen_movi_tl(cpu_nip, nip);
|
|
272 | 276 |
else |
273 | 277 |
#endif |
274 |
gen_op_update_nip(nip);
|
|
278 |
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
|
|
275 | 279 |
} |
276 | 280 |
|
277 | 281 |
#define GEN_EXCP(ctx, excp, error) \ |
... | ... | |
2836 | 2840 |
tcg_gen_movi_tl(cpu_T[1], dest); |
2837 | 2841 |
#if defined(TARGET_PPC64) |
2838 | 2842 |
if (ctx->sf_mode) |
2839 |
gen_op_b_T1_64();
|
|
2843 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
|
|
2840 | 2844 |
else |
2841 | 2845 |
#endif |
2842 |
gen_op_b_T1();
|
|
2846 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
|
|
2843 | 2847 |
tcg_gen_exit_tb((long)tb + n); |
2844 | 2848 |
} else { |
2845 | 2849 |
tcg_gen_movi_tl(cpu_T[1], dest); |
2846 | 2850 |
#if defined(TARGET_PPC64) |
2847 | 2851 |
if (ctx->sf_mode) |
2848 |
gen_op_b_T1_64();
|
|
2852 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
|
|
2849 | 2853 |
else |
2850 | 2854 |
#endif |
2851 |
gen_op_b_T1();
|
|
2855 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
|
|
2852 | 2856 |
if (unlikely(ctx->singlestep_enabled)) { |
2853 | 2857 |
if ((ctx->singlestep_enabled & |
2854 | 2858 |
(CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
... | ... | |
2969 | 2973 |
} else { |
2970 | 2974 |
#if defined(TARGET_PPC64) |
2971 | 2975 |
if (ctx->sf_mode) |
2972 |
gen_op_b_T1_64();
|
|
2976 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
|
|
2973 | 2977 |
else |
2974 | 2978 |
#endif |
2975 |
gen_op_b_T1();
|
|
2979 |
tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
|
|
2976 | 2980 |
goto no_test; |
2977 | 2981 |
} |
2978 | 2982 |
break; |
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