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/*
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* QEMU LSI53C895A SCSI Host Bus Adapter emulation
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the LGPL.
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*/
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/* ??? Need to check if the {read,write}[wl] routines work properly on
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big-endian targets. */
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#include "hw.h" |
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#include "pci.h" |
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#include "scsi-disk.h" |
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#include "block_int.h" |
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|
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//#define DEBUG_LSI
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//#define DEBUG_LSI_REG
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|
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#ifdef DEBUG_LSI
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#define DPRINTF(fmt, ...) \
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do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0) |
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while(0) |
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0) |
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#endif
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|
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#define LSI_SCNTL0_TRG 0x01 |
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#define LSI_SCNTL0_AAP 0x02 |
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#define LSI_SCNTL0_EPC 0x08 |
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#define LSI_SCNTL0_WATN 0x10 |
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#define LSI_SCNTL0_START 0x20 |
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|
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#define LSI_SCNTL1_SST 0x01 |
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#define LSI_SCNTL1_IARB 0x02 |
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#define LSI_SCNTL1_AESP 0x04 |
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#define LSI_SCNTL1_RST 0x08 |
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#define LSI_SCNTL1_CON 0x10 |
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#define LSI_SCNTL1_DHP 0x20 |
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#define LSI_SCNTL1_ADB 0x40 |
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#define LSI_SCNTL1_EXC 0x80 |
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|
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#define LSI_SCNTL2_WSR 0x01 |
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#define LSI_SCNTL2_VUE0 0x02 |
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#define LSI_SCNTL2_VUE1 0x04 |
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#define LSI_SCNTL2_WSS 0x08 |
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#define LSI_SCNTL2_SLPHBEN 0x10 |
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#define LSI_SCNTL2_SLPMD 0x20 |
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#define LSI_SCNTL2_CHM 0x40 |
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#define LSI_SCNTL2_SDU 0x80 |
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|
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#define LSI_ISTAT0_DIP 0x01 |
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#define LSI_ISTAT0_SIP 0x02 |
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#define LSI_ISTAT0_INTF 0x04 |
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#define LSI_ISTAT0_CON 0x08 |
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#define LSI_ISTAT0_SEM 0x10 |
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#define LSI_ISTAT0_SIGP 0x20 |
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#define LSI_ISTAT0_SRST 0x40 |
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#define LSI_ISTAT0_ABRT 0x80 |
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|
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#define LSI_ISTAT1_SI 0x01 |
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#define LSI_ISTAT1_SRUN 0x02 |
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#define LSI_ISTAT1_FLSH 0x04 |
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|
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#define LSI_SSTAT0_SDP0 0x01 |
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#define LSI_SSTAT0_RST 0x02 |
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#define LSI_SSTAT0_WOA 0x04 |
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#define LSI_SSTAT0_LOA 0x08 |
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#define LSI_SSTAT0_AIP 0x10 |
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#define LSI_SSTAT0_OLF 0x20 |
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#define LSI_SSTAT0_ORF 0x40 |
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#define LSI_SSTAT0_ILF 0x80 |
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|
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#define LSI_SIST0_PAR 0x01 |
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#define LSI_SIST0_RST 0x02 |
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#define LSI_SIST0_UDC 0x04 |
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#define LSI_SIST0_SGE 0x08 |
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#define LSI_SIST0_RSL 0x10 |
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#define LSI_SIST0_SEL 0x20 |
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#define LSI_SIST0_CMP 0x40 |
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#define LSI_SIST0_MA 0x80 |
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|
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#define LSI_SIST1_HTH 0x01 |
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#define LSI_SIST1_GEN 0x02 |
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#define LSI_SIST1_STO 0x04 |
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#define LSI_SIST1_SBMC 0x10 |
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|
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#define LSI_SOCL_IO 0x01 |
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#define LSI_SOCL_CD 0x02 |
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#define LSI_SOCL_MSG 0x04 |
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#define LSI_SOCL_ATN 0x08 |
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#define LSI_SOCL_SEL 0x10 |
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#define LSI_SOCL_BSY 0x20 |
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#define LSI_SOCL_ACK 0x40 |
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#define LSI_SOCL_REQ 0x80 |
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|
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#define LSI_DSTAT_IID 0x01 |
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#define LSI_DSTAT_SIR 0x04 |
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#define LSI_DSTAT_SSI 0x08 |
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#define LSI_DSTAT_ABRT 0x10 |
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#define LSI_DSTAT_BF 0x20 |
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#define LSI_DSTAT_MDPE 0x40 |
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#define LSI_DSTAT_DFE 0x80 |
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#define LSI_DCNTL_COM 0x01 |
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#define LSI_DCNTL_IRQD 0x02 |
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#define LSI_DCNTL_STD 0x04 |
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#define LSI_DCNTL_IRQM 0x08 |
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#define LSI_DCNTL_SSM 0x10 |
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#define LSI_DCNTL_PFEN 0x20 |
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#define LSI_DCNTL_PFF 0x40 |
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#define LSI_DCNTL_CLSE 0x80 |
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|
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#define LSI_DMODE_MAN 0x01 |
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#define LSI_DMODE_BOF 0x02 |
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#define LSI_DMODE_ERMP 0x04 |
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#define LSI_DMODE_ERL 0x08 |
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#define LSI_DMODE_DIOM 0x10 |
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#define LSI_DMODE_SIOM 0x20 |
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#define LSI_CTEST2_DACK 0x01 |
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#define LSI_CTEST2_DREQ 0x02 |
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#define LSI_CTEST2_TEOP 0x04 |
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#define LSI_CTEST2_PCICIE 0x08 |
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#define LSI_CTEST2_CM 0x10 |
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#define LSI_CTEST2_CIO 0x20 |
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#define LSI_CTEST2_SIGP 0x40 |
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#define LSI_CTEST2_DDIR 0x80 |
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#define LSI_CTEST5_BL2 0x04 |
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#define LSI_CTEST5_DDIR 0x08 |
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#define LSI_CTEST5_MASR 0x10 |
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#define LSI_CTEST5_DFSN 0x20 |
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#define LSI_CTEST5_BBCK 0x40 |
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#define LSI_CTEST5_ADCK 0x80 |
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#define LSI_CCNTL0_DILS 0x01 |
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#define LSI_CCNTL0_DISFC 0x10 |
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#define LSI_CCNTL0_ENNDJ 0x20 |
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#define LSI_CCNTL0_PMJCTL 0x40 |
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#define LSI_CCNTL0_ENPMJ 0x80 |
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#define LSI_CCNTL1_EN64DBMV 0x01 |
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#define LSI_CCNTL1_EN64TIBMV 0x02 |
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#define LSI_CCNTL1_64TIMOD 0x04 |
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#define LSI_CCNTL1_DDAC 0x08 |
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#define LSI_CCNTL1_ZMOD 0x80 |
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#define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
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#define PHASE_DO 0 |
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#define PHASE_DI 1 |
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#define PHASE_CMD 2 |
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#define PHASE_ST 3 |
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#define PHASE_MO 6 |
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#define PHASE_MI 7 |
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#define PHASE_MASK 7 |
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/* Maximum length of MSG IN data. */
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#define LSI_MAX_MSGIN_LEN 8 |
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/* Flag set if this is a tagged command. */
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#define LSI_TAG_VALID (1 << 16) |
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typedef struct { |
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uint32_t tag; |
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uint32_t pending; |
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int out;
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} lsi_queue; |
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typedef struct { |
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PCIDevice pci_dev; |
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int mmio_io_addr;
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int ram_io_addr;
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uint32_t script_ram_base; |
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int carry; /* ??? Should this be an a visible register somewhere? */ |
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int sense;
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/* Action to take at the end of a MSG IN phase.
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0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
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int msg_action;
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int msg_len;
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uint8_t msg[LSI_MAX_MSGIN_LEN]; |
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/* 0 if SCRIPTS are running or stopped.
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* 1 if a Wait Reselect instruction has been issued.
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* 2 if processing DMA from lsi_execute_script.
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* 3 if a DMA operation is in progress. */
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int waiting;
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SCSIDevice *scsi_dev[LSI_MAX_DEVS]; |
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SCSIDevice *current_dev; |
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int current_lun;
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/* The tag is a combination of the device ID and the SCSI tag. */
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uint32_t current_tag; |
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uint32_t current_dma_len; |
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int command_complete;
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uint8_t *dma_buf; |
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lsi_queue *queue; |
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int queue_len;
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int active_commands;
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uint32_t dsa; |
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uint32_t temp; |
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uint32_t dnad; |
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uint32_t dbc; |
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uint8_t istat0; |
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uint8_t istat1; |
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uint8_t dcmd; |
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uint8_t dstat; |
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uint8_t dien; |
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uint8_t sist0; |
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uint8_t sist1; |
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uint8_t sien0; |
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uint8_t sien1; |
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uint8_t mbox0; |
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uint8_t mbox1; |
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uint8_t dfifo; |
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uint8_t ctest2; |
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uint8_t ctest3; |
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uint8_t ctest4; |
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uint8_t ctest5; |
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uint8_t ccntl0; |
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uint8_t ccntl1; |
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uint32_t dsp; |
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uint32_t dsps; |
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uint8_t dmode; |
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uint8_t dcntl; |
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uint8_t scntl0; |
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uint8_t scntl1; |
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uint8_t scntl2; |
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uint8_t scntl3; |
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uint8_t sstat0; |
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uint8_t sstat1; |
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uint8_t scid; |
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uint8_t sxfer; |
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uint8_t socl; |
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uint8_t sdid; |
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uint8_t ssid; |
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uint8_t sfbr; |
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uint8_t stest1; |
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uint8_t stest2; |
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uint8_t stest3; |
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uint8_t sidl; |
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uint8_t stime0; |
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uint8_t respid0; |
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uint8_t respid1; |
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uint32_t mmrs; |
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uint32_t mmws; |
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uint32_t sfs; |
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uint32_t drs; |
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uint32_t sbms; |
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uint32_t dbms; |
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uint32_t dnad64; |
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uint32_t pmjad1; |
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uint32_t pmjad2; |
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uint32_t rbc; |
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uint32_t ua; |
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uint32_t ia; |
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uint32_t sbc; |
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uint32_t csbc; |
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uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ |
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uint8_t sbr; |
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/* Script ram is stored as 32-bit words in host byteorder. */
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uint32_t script_ram[2048];
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} LSIState; |
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static void lsi_soft_reset(LSIState *s) |
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{ |
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DPRINTF("Reset\n");
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s->carry = 0;
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s->waiting = 0;
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s->dsa = 0;
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s->dnad = 0;
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s->dbc = 0;
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s->temp = 0;
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memset(s->scratch, 0, sizeof(s->scratch)); |
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s->istat0 = 0;
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s->istat1 = 0;
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s->dcmd = 0;
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s->dstat = 0;
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s->dien = 0;
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s->sist0 = 0;
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s->sist1 = 0;
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s->sien0 = 0;
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s->sien1 = 0;
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s->mbox0 = 0;
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s->mbox1 = 0;
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s->dfifo = 0;
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s->ctest2 = 0;
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s->ctest3 = 0;
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s->ctest4 = 0;
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s->ctest5 = 0;
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s->ccntl0 = 0;
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s->ccntl1 = 0;
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s->dsp = 0;
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s->dsps = 0;
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s->dmode = 0;
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s->dcntl = 0;
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s->scntl0 = 0xc0;
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s->scntl1 = 0;
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s->scntl2 = 0;
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s->scntl3 = 0;
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s->sstat0 = 0;
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s->sstat1 = 0;
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s->scid = 7;
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s->sxfer = 0;
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s->socl = 0;
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s->stest1 = 0;
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s->stest2 = 0;
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s->stest3 = 0;
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s->sidl = 0;
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s->stime0 = 0;
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s->respid0 = 0x80;
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s->respid1 = 0;
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s->mmrs = 0;
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s->mmws = 0;
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s->sfs = 0;
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s->drs = 0;
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s->sbms = 0;
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s->dbms = 0;
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s->dnad64 = 0;
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s->pmjad1 = 0;
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s->pmjad2 = 0;
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s->rbc = 0;
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s->ua = 0;
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s->ia = 0;
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s->sbc = 0;
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s->csbc = 0;
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s->sbr = 0;
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} |
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|
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static int lsi_dma_40bit(LSIState *s) |
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{ |
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if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
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return 1; |
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return 0; |
342 |
} |
343 |
|
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static int lsi_dma_ti64bit(LSIState *s) |
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{ |
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if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
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return 1; |
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return 0; |
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} |
350 |
|
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static int lsi_dma_64bit(LSIState *s) |
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{ |
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if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
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return 1; |
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return 0; |
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} |
357 |
|
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static uint8_t lsi_reg_readb(LSIState *s, int offset); |
359 |
static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val); |
360 |
static void lsi_execute_script(LSIState *s); |
361 |
|
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static inline uint32_t read_dword(LSIState *s, uint32_t addr) |
363 |
{ |
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uint32_t buf; |
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|
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/* Optimize reading from SCRIPTS RAM. */
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if ((addr & 0xffffe000) == s->script_ram_base) { |
368 |
return s->script_ram[(addr & 0x1fff) >> 2]; |
369 |
} |
370 |
cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
|
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return cpu_to_le32(buf);
|
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} |
373 |
|
374 |
static void lsi_stop_script(LSIState *s) |
375 |
{ |
376 |
s->istat1 &= ~LSI_ISTAT1_SRUN; |
377 |
} |
378 |
|
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static void lsi_update_irq(LSIState *s) |
380 |
{ |
381 |
int level;
|
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static int last_level; |
383 |
|
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/* It's unclear whether the DIP/SIP bits should be cleared when the
|
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Interrupt Status Registers are cleared or when istat0 is read.
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We currently do the formwer, which seems to work. */
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level = 0;
|
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if (s->dstat) {
|
389 |
if (s->dstat & s->dien)
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level = 1;
|
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s->istat0 |= LSI_ISTAT0_DIP; |
392 |
} else {
|
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s->istat0 &= ~LSI_ISTAT0_DIP; |
394 |
} |
395 |
|
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if (s->sist0 || s->sist1) {
|
397 |
if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
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level = 1;
|
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s->istat0 |= LSI_ISTAT0_SIP; |
400 |
} else {
|
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s->istat0 &= ~LSI_ISTAT0_SIP; |
402 |
} |
403 |
if (s->istat0 & LSI_ISTAT0_INTF)
|
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level = 1;
|
405 |
|
406 |
if (level != last_level) {
|
407 |
DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
|
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level, s->dstat, s->sist1, s->sist0); |
409 |
last_level = level; |
410 |
} |
411 |
qemu_set_irq(s->pci_dev.irq[0], level);
|
412 |
} |
413 |
|
414 |
/* Stop SCRIPTS execution and raise a SCSI interrupt. */
|
415 |
static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1) |
416 |
{ |
417 |
uint32_t mask0; |
418 |
uint32_t mask1; |
419 |
|
420 |
DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
|
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stat1, stat0, s->sist1, s->sist0); |
422 |
s->sist0 |= stat0; |
423 |
s->sist1 |= stat1; |
424 |
/* Stop processor on fatal or unmasked interrupt. As a special hack
|
425 |
we don't stop processing when raising STO. Instead continue
|
426 |
execution and stop at the next insn that accesses the SCSI bus. */
|
427 |
mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL); |
428 |
mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH); |
429 |
mask1 &= ~LSI_SIST1_STO; |
430 |
if (s->sist0 & mask0 || s->sist1 & mask1) {
|
431 |
lsi_stop_script(s); |
432 |
} |
433 |
lsi_update_irq(s); |
434 |
} |
435 |
|
436 |
/* Stop SCRIPTS execution and raise a DMA interrupt. */
|
437 |
static void lsi_script_dma_interrupt(LSIState *s, int stat) |
438 |
{ |
439 |
DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
|
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s->dstat |= stat; |
441 |
lsi_update_irq(s); |
442 |
lsi_stop_script(s); |
443 |
} |
444 |
|
445 |
static inline void lsi_set_phase(LSIState *s, int phase) |
446 |
{ |
447 |
s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase; |
448 |
} |
449 |
|
450 |
static void lsi_bad_phase(LSIState *s, int out, int new_phase) |
451 |
{ |
452 |
/* Trigger a phase mismatch. */
|
453 |
if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
|
454 |
if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
|
455 |
s->dsp = s->pmjad1; |
456 |
} else {
|
457 |
s->dsp = s->pmjad2; |
458 |
} |
459 |
DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
|
460 |
} else {
|
461 |
DPRINTF("Phase mismatch interrupt\n");
|
462 |
lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
|
463 |
lsi_stop_script(s); |
464 |
} |
465 |
lsi_set_phase(s, new_phase); |
466 |
} |
467 |
|
468 |
|
469 |
/* Resume SCRIPTS execution after a DMA operation. */
|
470 |
static void lsi_resume_script(LSIState *s) |
471 |
{ |
472 |
if (s->waiting != 2) { |
473 |
s->waiting = 0;
|
474 |
lsi_execute_script(s); |
475 |
} else {
|
476 |
s->waiting = 0;
|
477 |
} |
478 |
} |
479 |
|
480 |
/* Initiate a SCSI layer data transfer. */
|
481 |
static void lsi_do_dma(LSIState *s, int out) |
482 |
{ |
483 |
uint32_t count; |
484 |
target_phys_addr_t addr; |
485 |
|
486 |
if (!s->current_dma_len) {
|
487 |
/* Wait until data is available. */
|
488 |
DPRINTF("DMA no data available\n");
|
489 |
return;
|
490 |
} |
491 |
|
492 |
count = s->dbc; |
493 |
if (count > s->current_dma_len)
|
494 |
count = s->current_dma_len; |
495 |
|
496 |
addr = s->dnad; |
497 |
/* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
|
498 |
if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
|
499 |
addr |= ((uint64_t)s->dnad64 << 32);
|
500 |
else if (s->dbms) |
501 |
addr |= ((uint64_t)s->dbms << 32);
|
502 |
else if (s->sbms) |
503 |
addr |= ((uint64_t)s->sbms << 32);
|
504 |
|
505 |
DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count); |
506 |
s->csbc += count; |
507 |
s->dnad += count; |
508 |
s->dbc -= count; |
509 |
|
510 |
if (s->dma_buf == NULL) { |
511 |
s->dma_buf = s->current_dev->get_buf(s->current_dev, |
512 |
s->current_tag); |
513 |
} |
514 |
|
515 |
/* ??? Set SFBR to first data byte. */
|
516 |
if (out) {
|
517 |
cpu_physical_memory_read(addr, s->dma_buf, count); |
518 |
} else {
|
519 |
cpu_physical_memory_write(addr, s->dma_buf, count); |
520 |
} |
521 |
s->current_dma_len -= count; |
522 |
if (s->current_dma_len == 0) { |
523 |
s->dma_buf = NULL;
|
524 |
if (out) {
|
525 |
/* Write the data. */
|
526 |
s->current_dev->write_data(s->current_dev, s->current_tag); |
527 |
} else {
|
528 |
/* Request any remaining data. */
|
529 |
s->current_dev->read_data(s->current_dev, s->current_tag); |
530 |
} |
531 |
} else {
|
532 |
s->dma_buf += count; |
533 |
lsi_resume_script(s); |
534 |
} |
535 |
} |
536 |
|
537 |
|
538 |
/* Add a command to the queue. */
|
539 |
static void lsi_queue_command(LSIState *s) |
540 |
{ |
541 |
lsi_queue *p; |
542 |
|
543 |
DPRINTF("Queueing tag=0x%x\n", s->current_tag);
|
544 |
if (s->queue_len == s->active_commands) {
|
545 |
s->queue_len++; |
546 |
s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
|
547 |
} |
548 |
p = &s->queue[s->active_commands++]; |
549 |
p->tag = s->current_tag; |
550 |
p->pending = 0;
|
551 |
p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
552 |
} |
553 |
|
554 |
/* Queue a byte for a MSG IN phase. */
|
555 |
static void lsi_add_msg_byte(LSIState *s, uint8_t data) |
556 |
{ |
557 |
if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
|
558 |
BADF("MSG IN data too long\n");
|
559 |
} else {
|
560 |
DPRINTF("MSG IN 0x%02x\n", data);
|
561 |
s->msg[s->msg_len++] = data; |
562 |
} |
563 |
} |
564 |
|
565 |
/* Perform reselection to continue a command. */
|
566 |
static void lsi_reselect(LSIState *s, uint32_t tag) |
567 |
{ |
568 |
lsi_queue *p; |
569 |
int n;
|
570 |
int id;
|
571 |
|
572 |
p = NULL;
|
573 |
for (n = 0; n < s->active_commands; n++) { |
574 |
p = &s->queue[n]; |
575 |
if (p->tag == tag)
|
576 |
break;
|
577 |
} |
578 |
if (n == s->active_commands) {
|
579 |
BADF("Reselected non-existant command tag=0x%x\n", tag);
|
580 |
return;
|
581 |
} |
582 |
id = (tag >> 8) & 0xf; |
583 |
s->ssid = id | 0x80;
|
584 |
DPRINTF("Reselected target %d\n", id);
|
585 |
s->current_dev = s->scsi_dev[id]; |
586 |
s->current_tag = tag; |
587 |
s->scntl1 |= LSI_SCNTL1_CON; |
588 |
lsi_set_phase(s, PHASE_MI); |
589 |
s->msg_action = p->out ? 2 : 3; |
590 |
s->current_dma_len = p->pending; |
591 |
s->dma_buf = NULL;
|
592 |
lsi_add_msg_byte(s, 0x80);
|
593 |
if (s->current_tag & LSI_TAG_VALID) {
|
594 |
lsi_add_msg_byte(s, 0x20);
|
595 |
lsi_add_msg_byte(s, tag & 0xff);
|
596 |
} |
597 |
|
598 |
s->active_commands--; |
599 |
if (n != s->active_commands) {
|
600 |
s->queue[n] = s->queue[s->active_commands]; |
601 |
} |
602 |
} |
603 |
|
604 |
/* Record that data is available for a queued command. Returns zero if
|
605 |
the device was reselected, nonzero if the IO is deferred. */
|
606 |
static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg) |
607 |
{ |
608 |
lsi_queue *p; |
609 |
int i;
|
610 |
for (i = 0; i < s->active_commands; i++) { |
611 |
p = &s->queue[i]; |
612 |
if (p->tag == tag) {
|
613 |
if (p->pending) {
|
614 |
BADF("Multiple IO pending for tag %d\n", tag);
|
615 |
} |
616 |
p->pending = arg; |
617 |
if (s->waiting == 1) { |
618 |
/* Reselect device. */
|
619 |
lsi_reselect(s, tag); |
620 |
return 0; |
621 |
} else {
|
622 |
DPRINTF("Queueing IO tag=0x%x\n", tag);
|
623 |
p->pending = arg; |
624 |
return 1; |
625 |
} |
626 |
} |
627 |
} |
628 |
BADF("IO with unknown tag %d\n", tag);
|
629 |
return 1; |
630 |
} |
631 |
|
632 |
/* Callback to indicate that the SCSI layer has completed a transfer. */
|
633 |
static void lsi_command_complete(void *opaque, int reason, uint32_t tag, |
634 |
uint32_t arg) |
635 |
{ |
636 |
LSIState *s = (LSIState *)opaque; |
637 |
int out;
|
638 |
|
639 |
out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
640 |
if (reason == SCSI_REASON_DONE) {
|
641 |
DPRINTF("Command complete sense=%d\n", (int)arg); |
642 |
s->sense = arg; |
643 |
s->command_complete = 2;
|
644 |
if (s->waiting && s->dbc != 0) { |
645 |
/* Raise phase mismatch for short transfers. */
|
646 |
lsi_bad_phase(s, out, PHASE_ST); |
647 |
} else {
|
648 |
lsi_set_phase(s, PHASE_ST); |
649 |
} |
650 |
lsi_resume_script(s); |
651 |
return;
|
652 |
} |
653 |
|
654 |
if (s->waiting == 1 || tag != s->current_tag) { |
655 |
if (lsi_queue_tag(s, tag, arg))
|
656 |
return;
|
657 |
} |
658 |
DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
|
659 |
s->current_dma_len = arg; |
660 |
s->command_complete = 1;
|
661 |
if (!s->waiting)
|
662 |
return;
|
663 |
if (s->waiting == 1 || s->dbc == 0) { |
664 |
lsi_resume_script(s); |
665 |
} else {
|
666 |
lsi_do_dma(s, out); |
667 |
} |
668 |
} |
669 |
|
670 |
static void lsi_do_command(LSIState *s) |
671 |
{ |
672 |
uint8_t buf[16];
|
673 |
int n;
|
674 |
|
675 |
DPRINTF("Send command len=%d\n", s->dbc);
|
676 |
if (s->dbc > 16) |
677 |
s->dbc = 16;
|
678 |
cpu_physical_memory_read(s->dnad, buf, s->dbc); |
679 |
s->sfbr = buf[0];
|
680 |
s->command_complete = 0;
|
681 |
n = s->current_dev->send_command(s->current_dev, s->current_tag, buf, |
682 |
s->current_lun); |
683 |
if (n > 0) { |
684 |
lsi_set_phase(s, PHASE_DI); |
685 |
s->current_dev->read_data(s->current_dev, s->current_tag); |
686 |
} else if (n < 0) { |
687 |
lsi_set_phase(s, PHASE_DO); |
688 |
s->current_dev->write_data(s->current_dev, s->current_tag); |
689 |
} |
690 |
|
691 |
if (!s->command_complete) {
|
692 |
if (n) {
|
693 |
/* Command did not complete immediately so disconnect. */
|
694 |
lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */ |
695 |
lsi_add_msg_byte(s, 4); /* DISCONNECT */ |
696 |
/* wait data */
|
697 |
lsi_set_phase(s, PHASE_MI); |
698 |
s->msg_action = 1;
|
699 |
lsi_queue_command(s); |
700 |
} else {
|
701 |
/* wait command complete */
|
702 |
lsi_set_phase(s, PHASE_DI); |
703 |
} |
704 |
} |
705 |
} |
706 |
|
707 |
static void lsi_do_status(LSIState *s) |
708 |
{ |
709 |
uint8_t sense; |
710 |
DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
|
711 |
if (s->dbc != 1) |
712 |
BADF("Bad Status move\n");
|
713 |
s->dbc = 1;
|
714 |
sense = s->sense; |
715 |
s->sfbr = sense; |
716 |
cpu_physical_memory_write(s->dnad, &sense, 1);
|
717 |
lsi_set_phase(s, PHASE_MI); |
718 |
s->msg_action = 1;
|
719 |
lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */ |
720 |
} |
721 |
|
722 |
static void lsi_disconnect(LSIState *s) |
723 |
{ |
724 |
s->scntl1 &= ~LSI_SCNTL1_CON; |
725 |
s->sstat1 &= ~PHASE_MASK; |
726 |
} |
727 |
|
728 |
static void lsi_do_msgin(LSIState *s) |
729 |
{ |
730 |
int len;
|
731 |
DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
|
732 |
s->sfbr = s->msg[0];
|
733 |
len = s->msg_len; |
734 |
if (len > s->dbc)
|
735 |
len = s->dbc; |
736 |
cpu_physical_memory_write(s->dnad, s->msg, len); |
737 |
/* Linux drivers rely on the last byte being in the SIDL. */
|
738 |
s->sidl = s->msg[len - 1];
|
739 |
s->msg_len -= len; |
740 |
if (s->msg_len) {
|
741 |
memmove(s->msg, s->msg + len, s->msg_len); |
742 |
} else {
|
743 |
/* ??? Check if ATN (not yet implemented) is asserted and maybe
|
744 |
switch to PHASE_MO. */
|
745 |
switch (s->msg_action) {
|
746 |
case 0: |
747 |
lsi_set_phase(s, PHASE_CMD); |
748 |
break;
|
749 |
case 1: |
750 |
lsi_disconnect(s); |
751 |
break;
|
752 |
case 2: |
753 |
lsi_set_phase(s, PHASE_DO); |
754 |
break;
|
755 |
case 3: |
756 |
lsi_set_phase(s, PHASE_DI); |
757 |
break;
|
758 |
default:
|
759 |
abort(); |
760 |
} |
761 |
} |
762 |
} |
763 |
|
764 |
/* Read the next byte during a MSGOUT phase. */
|
765 |
static uint8_t lsi_get_msgbyte(LSIState *s)
|
766 |
{ |
767 |
uint8_t data; |
768 |
cpu_physical_memory_read(s->dnad, &data, 1);
|
769 |
s->dnad++; |
770 |
s->dbc--; |
771 |
return data;
|
772 |
} |
773 |
|
774 |
static void lsi_do_msgout(LSIState *s) |
775 |
{ |
776 |
uint8_t msg; |
777 |
int len;
|
778 |
|
779 |
DPRINTF("MSG out len=%d\n", s->dbc);
|
780 |
while (s->dbc) {
|
781 |
msg = lsi_get_msgbyte(s); |
782 |
s->sfbr = msg; |
783 |
|
784 |
switch (msg) {
|
785 |
case 0x00: |
786 |
DPRINTF("MSG: Disconnect\n");
|
787 |
lsi_disconnect(s); |
788 |
break;
|
789 |
case 0x08: |
790 |
DPRINTF("MSG: No Operation\n");
|
791 |
lsi_set_phase(s, PHASE_CMD); |
792 |
break;
|
793 |
case 0x01: |
794 |
len = lsi_get_msgbyte(s); |
795 |
msg = lsi_get_msgbyte(s); |
796 |
DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
|
797 |
switch (msg) {
|
798 |
case 1: |
799 |
DPRINTF("SDTR (ignored)\n");
|
800 |
s->dbc -= 2;
|
801 |
break;
|
802 |
case 3: |
803 |
DPRINTF("WDTR (ignored)\n");
|
804 |
s->dbc -= 1;
|
805 |
break;
|
806 |
default:
|
807 |
goto bad;
|
808 |
} |
809 |
break;
|
810 |
case 0x20: /* SIMPLE queue */ |
811 |
s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
812 |
DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff); |
813 |
break;
|
814 |
case 0x21: /* HEAD of queue */ |
815 |
BADF("HEAD queue not implemented\n");
|
816 |
s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
817 |
break;
|
818 |
case 0x22: /* ORDERED queue */ |
819 |
BADF("ORDERED queue not implemented\n");
|
820 |
s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
821 |
break;
|
822 |
default:
|
823 |
if ((msg & 0x80) == 0) { |
824 |
goto bad;
|
825 |
} |
826 |
s->current_lun = msg & 7;
|
827 |
DPRINTF("Select LUN %d\n", s->current_lun);
|
828 |
lsi_set_phase(s, PHASE_CMD); |
829 |
break;
|
830 |
} |
831 |
} |
832 |
return;
|
833 |
bad:
|
834 |
BADF("Unimplemented message 0x%02x\n", msg);
|
835 |
lsi_set_phase(s, PHASE_MI); |
836 |
lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */ |
837 |
s->msg_action = 0;
|
838 |
} |
839 |
|
840 |
/* Sign extend a 24-bit value. */
|
841 |
static inline int32_t sxt24(int32_t n) |
842 |
{ |
843 |
return (n << 8) >> 8; |
844 |
} |
845 |
|
846 |
#define LSI_BUF_SIZE 4096 |
847 |
static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count) |
848 |
{ |
849 |
int n;
|
850 |
uint8_t buf[LSI_BUF_SIZE]; |
851 |
|
852 |
DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
|
853 |
while (count) {
|
854 |
n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count; |
855 |
cpu_physical_memory_read(src, buf, n); |
856 |
cpu_physical_memory_write(dest, buf, n); |
857 |
src += n; |
858 |
dest += n; |
859 |
count -= n; |
860 |
} |
861 |
} |
862 |
|
863 |
static void lsi_wait_reselect(LSIState *s) |
864 |
{ |
865 |
int i;
|
866 |
DPRINTF("Wait Reselect\n");
|
867 |
if (s->current_dma_len)
|
868 |
BADF("Reselect with pending DMA\n");
|
869 |
for (i = 0; i < s->active_commands; i++) { |
870 |
if (s->queue[i].pending) {
|
871 |
lsi_reselect(s, s->queue[i].tag); |
872 |
break;
|
873 |
} |
874 |
} |
875 |
if (s->current_dma_len == 0) { |
876 |
s->waiting = 1;
|
877 |
} |
878 |
} |
879 |
|
880 |
static void lsi_execute_script(LSIState *s) |
881 |
{ |
882 |
uint32_t insn; |
883 |
uint32_t addr, addr_high; |
884 |
int opcode;
|
885 |
int insn_processed = 0; |
886 |
|
887 |
s->istat1 |= LSI_ISTAT1_SRUN; |
888 |
again:
|
889 |
insn_processed++; |
890 |
insn = read_dword(s, s->dsp); |
891 |
if (!insn) {
|
892 |
/* If we receive an empty opcode increment the DSP by 4 bytes
|
893 |
instead of 8 and execute the next opcode at that location */
|
894 |
s->dsp += 4;
|
895 |
goto again;
|
896 |
} |
897 |
addr = read_dword(s, s->dsp + 4);
|
898 |
addr_high = 0;
|
899 |
DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
|
900 |
s->dsps = addr; |
901 |
s->dcmd = insn >> 24;
|
902 |
s->dsp += 8;
|
903 |
switch (insn >> 30) { |
904 |
case 0: /* Block move. */ |
905 |
if (s->sist1 & LSI_SIST1_STO) {
|
906 |
DPRINTF("Delayed select timeout\n");
|
907 |
lsi_stop_script(s); |
908 |
break;
|
909 |
} |
910 |
s->dbc = insn & 0xffffff;
|
911 |
s->rbc = s->dbc; |
912 |
/* ??? Set ESA. */
|
913 |
s->ia = s->dsp - 8;
|
914 |
if (insn & (1 << 29)) { |
915 |
/* Indirect addressing. */
|
916 |
addr = read_dword(s, addr); |
917 |
} else if (insn & (1 << 28)) { |
918 |
uint32_t buf[2];
|
919 |
int32_t offset; |
920 |
/* Table indirect addressing. */
|
921 |
|
922 |
/* 32-bit Table indirect */
|
923 |
offset = sxt24(addr); |
924 |
cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
|
925 |
/* byte count is stored in bits 0:23 only */
|
926 |
s->dbc = cpu_to_le32(buf[0]) & 0xffffff; |
927 |
s->rbc = s->dbc; |
928 |
addr = cpu_to_le32(buf[1]);
|
929 |
|
930 |
/* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
|
931 |
* table, bits [31:24] */
|
932 |
if (lsi_dma_40bit(s))
|
933 |
addr_high = cpu_to_le32(buf[0]) >> 24; |
934 |
else if (lsi_dma_ti64bit(s)) { |
935 |
int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f; |
936 |
switch (selector) {
|
937 |
case 0 ... 0x0f: |
938 |
/* offset index into scratch registers since
|
939 |
* TI64 mode can use registers C to R */
|
940 |
addr_high = s->scratch[2 + selector];
|
941 |
break;
|
942 |
case 0x10: |
943 |
addr_high = s->mmrs; |
944 |
break;
|
945 |
case 0x11: |
946 |
addr_high = s->mmws; |
947 |
break;
|
948 |
case 0x12: |
949 |
addr_high = s->sfs; |
950 |
break;
|
951 |
case 0x13: |
952 |
addr_high = s->drs; |
953 |
break;
|
954 |
case 0x14: |
955 |
addr_high = s->sbms; |
956 |
break;
|
957 |
case 0x15: |
958 |
addr_high = s->dbms; |
959 |
break;
|
960 |
default:
|
961 |
BADF("Illegal selector specified (0x%x > 0x15)"
|
962 |
" for 64-bit DMA block move", selector);
|
963 |
break;
|
964 |
} |
965 |
} |
966 |
} else if (lsi_dma_64bit(s)) { |
967 |
/* fetch a 3rd dword if 64-bit direct move is enabled and
|
968 |
only if we're not doing table indirect or indirect addressing */
|
969 |
s->dbms = read_dword(s, s->dsp); |
970 |
s->dsp += 4;
|
971 |
s->ia = s->dsp - 12;
|
972 |
} |
973 |
if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) { |
974 |
DPRINTF("Wrong phase got %d expected %d\n",
|
975 |
s->sstat1 & PHASE_MASK, (insn >> 24) & 7); |
976 |
lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
|
977 |
break;
|
978 |
} |
979 |
s->dnad = addr; |
980 |
s->dnad64 = addr_high; |
981 |
switch (s->sstat1 & 0x7) { |
982 |
case PHASE_DO:
|
983 |
s->waiting = 2;
|
984 |
lsi_do_dma(s, 1);
|
985 |
if (s->waiting)
|
986 |
s->waiting = 3;
|
987 |
break;
|
988 |
case PHASE_DI:
|
989 |
s->waiting = 2;
|
990 |
lsi_do_dma(s, 0);
|
991 |
if (s->waiting)
|
992 |
s->waiting = 3;
|
993 |
break;
|
994 |
case PHASE_CMD:
|
995 |
lsi_do_command(s); |
996 |
break;
|
997 |
case PHASE_ST:
|
998 |
lsi_do_status(s); |
999 |
break;
|
1000 |
case PHASE_MO:
|
1001 |
lsi_do_msgout(s); |
1002 |
break;
|
1003 |
case PHASE_MI:
|
1004 |
lsi_do_msgin(s); |
1005 |
break;
|
1006 |
default:
|
1007 |
BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
|
1008 |
exit(1);
|
1009 |
} |
1010 |
s->dfifo = s->dbc & 0xff;
|
1011 |
s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3); |
1012 |
s->sbc = s->dbc; |
1013 |
s->rbc -= s->dbc; |
1014 |
s->ua = addr + s->dbc; |
1015 |
break;
|
1016 |
|
1017 |
case 1: /* IO or Read/Write instruction. */ |
1018 |
opcode = (insn >> 27) & 7; |
1019 |
if (opcode < 5) { |
1020 |
uint32_t id; |
1021 |
|
1022 |
if (insn & (1 << 25)) { |
1023 |
id = read_dword(s, s->dsa + sxt24(insn)); |
1024 |
} else {
|
1025 |
id = addr; |
1026 |
} |
1027 |
id = (id >> 16) & 0xf; |
1028 |
if (insn & (1 << 26)) { |
1029 |
addr = s->dsp + sxt24(addr); |
1030 |
} |
1031 |
s->dnad = addr; |
1032 |
switch (opcode) {
|
1033 |
case 0: /* Select */ |
1034 |
s->sdid = id; |
1035 |
if (s->current_dma_len && (s->ssid & 0xf) == id) { |
1036 |
DPRINTF("Already reselected by target %d\n", id);
|
1037 |
break;
|
1038 |
} |
1039 |
s->sstat0 |= LSI_SSTAT0_WOA; |
1040 |
s->scntl1 &= ~LSI_SCNTL1_IARB; |
1041 |
if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
|
1042 |
DPRINTF("Selected absent target %d\n", id);
|
1043 |
lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
|
1044 |
lsi_disconnect(s); |
1045 |
break;
|
1046 |
} |
1047 |
DPRINTF("Selected target %d%s\n",
|
1048 |
id, insn & (1 << 3) ? " ATN" : ""); |
1049 |
/* ??? Linux drivers compain when this is set. Maybe
|
1050 |
it only applies in low-level mode (unimplemented).
|
1051 |
lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
|
1052 |
s->current_dev = s->scsi_dev[id]; |
1053 |
s->current_tag = id << 8;
|
1054 |
s->scntl1 |= LSI_SCNTL1_CON; |
1055 |
if (insn & (1 << 3)) { |
1056 |
s->socl |= LSI_SOCL_ATN; |
1057 |
} |
1058 |
lsi_set_phase(s, PHASE_MO); |
1059 |
break;
|
1060 |
case 1: /* Disconnect */ |
1061 |
DPRINTF("Wait Disconect\n");
|
1062 |
s->scntl1 &= ~LSI_SCNTL1_CON; |
1063 |
break;
|
1064 |
case 2: /* Wait Reselect */ |
1065 |
lsi_wait_reselect(s); |
1066 |
break;
|
1067 |
case 3: /* Set */ |
1068 |
DPRINTF("Set%s%s%s%s\n",
|
1069 |
insn & (1 << 3) ? " ATN" : "", |
1070 |
insn & (1 << 6) ? " ACK" : "", |
1071 |
insn & (1 << 9) ? " TM" : "", |
1072 |
insn & (1 << 10) ? " CC" : ""); |
1073 |
if (insn & (1 << 3)) { |
1074 |
s->socl |= LSI_SOCL_ATN; |
1075 |
lsi_set_phase(s, PHASE_MO); |
1076 |
} |
1077 |
if (insn & (1 << 9)) { |
1078 |
BADF("Target mode not implemented\n");
|
1079 |
exit(1);
|
1080 |
} |
1081 |
if (insn & (1 << 10)) |
1082 |
s->carry = 1;
|
1083 |
break;
|
1084 |
case 4: /* Clear */ |
1085 |
DPRINTF("Clear%s%s%s%s\n",
|
1086 |
insn & (1 << 3) ? " ATN" : "", |
1087 |
insn & (1 << 6) ? " ACK" : "", |
1088 |
insn & (1 << 9) ? " TM" : "", |
1089 |
insn & (1 << 10) ? " CC" : ""); |
1090 |
if (insn & (1 << 3)) { |
1091 |
s->socl &= ~LSI_SOCL_ATN; |
1092 |
} |
1093 |
if (insn & (1 << 10)) |
1094 |
s->carry = 0;
|
1095 |
break;
|
1096 |
} |
1097 |
} else {
|
1098 |
uint8_t op0; |
1099 |
uint8_t op1; |
1100 |
uint8_t data8; |
1101 |
int reg;
|
1102 |
int operator;
|
1103 |
#ifdef DEBUG_LSI
|
1104 |
static const char *opcode_names[3] = |
1105 |
{"Write", "Read", "Read-Modify-Write"}; |
1106 |
static const char *operator_names[8] = |
1107 |
{"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"}; |
1108 |
#endif
|
1109 |
|
1110 |
reg = ((insn >> 16) & 0x7f) | (insn & 0x80); |
1111 |
data8 = (insn >> 8) & 0xff; |
1112 |
opcode = (insn >> 27) & 7; |
1113 |
operator = (insn >> 24) & 7; |
1114 |
DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
|
1115 |
opcode_names[opcode - 5], reg,
|
1116 |
operator_names[operator], data8, s->sfbr, |
1117 |
(insn & (1 << 23)) ? " SFBR" : ""); |
1118 |
op0 = op1 = 0;
|
1119 |
switch (opcode) {
|
1120 |
case 5: /* From SFBR */ |
1121 |
op0 = s->sfbr; |
1122 |
op1 = data8; |
1123 |
break;
|
1124 |
case 6: /* To SFBR */ |
1125 |
if (operator)
|
1126 |
op0 = lsi_reg_readb(s, reg); |
1127 |
op1 = data8; |
1128 |
break;
|
1129 |
case 7: /* Read-modify-write */ |
1130 |
if (operator)
|
1131 |
op0 = lsi_reg_readb(s, reg); |
1132 |
if (insn & (1 << 23)) { |
1133 |
op1 = s->sfbr; |
1134 |
} else {
|
1135 |
op1 = data8; |
1136 |
} |
1137 |
break;
|
1138 |
} |
1139 |
|
1140 |
switch (operator) {
|
1141 |
case 0: /* move */ |
1142 |
op0 = op1; |
1143 |
break;
|
1144 |
case 1: /* Shift left */ |
1145 |
op1 = op0 >> 7;
|
1146 |
op0 = (op0 << 1) | s->carry;
|
1147 |
s->carry = op1; |
1148 |
break;
|
1149 |
case 2: /* OR */ |
1150 |
op0 |= op1; |
1151 |
break;
|
1152 |
case 3: /* XOR */ |
1153 |
op0 ^= op1; |
1154 |
break;
|
1155 |
case 4: /* AND */ |
1156 |
op0 &= op1; |
1157 |
break;
|
1158 |
case 5: /* SHR */ |
1159 |
op1 = op0 & 1;
|
1160 |
op0 = (op0 >> 1) | (s->carry << 7); |
1161 |
s->carry = op1; |
1162 |
break;
|
1163 |
case 6: /* ADD */ |
1164 |
op0 += op1; |
1165 |
s->carry = op0 < op1; |
1166 |
break;
|
1167 |
case 7: /* ADC */ |
1168 |
op0 += op1 + s->carry; |
1169 |
if (s->carry)
|
1170 |
s->carry = op0 <= op1; |
1171 |
else
|
1172 |
s->carry = op0 < op1; |
1173 |
break;
|
1174 |
} |
1175 |
|
1176 |
switch (opcode) {
|
1177 |
case 5: /* From SFBR */ |
1178 |
case 7: /* Read-modify-write */ |
1179 |
lsi_reg_writeb(s, reg, op0); |
1180 |
break;
|
1181 |
case 6: /* To SFBR */ |
1182 |
s->sfbr = op0; |
1183 |
break;
|
1184 |
} |
1185 |
} |
1186 |
break;
|
1187 |
|
1188 |
case 2: /* Transfer Control. */ |
1189 |
{ |
1190 |
int cond;
|
1191 |
int jmp;
|
1192 |
|
1193 |
if ((insn & 0x002e0000) == 0) { |
1194 |
DPRINTF("NOP\n");
|
1195 |
break;
|
1196 |
} |
1197 |
if (s->sist1 & LSI_SIST1_STO) {
|
1198 |
DPRINTF("Delayed select timeout\n");
|
1199 |
lsi_stop_script(s); |
1200 |
break;
|
1201 |
} |
1202 |
cond = jmp = (insn & (1 << 19)) != 0; |
1203 |
if (cond == jmp && (insn & (1 << 21))) { |
1204 |
DPRINTF("Compare carry %d\n", s->carry == jmp);
|
1205 |
cond = s->carry != 0;
|
1206 |
} |
1207 |
if (cond == jmp && (insn & (1 << 17))) { |
1208 |
DPRINTF("Compare phase %d %c= %d\n",
|
1209 |
(s->sstat1 & PHASE_MASK), |
1210 |
jmp ? '=' : '!', |
1211 |
((insn >> 24) & 7)); |
1212 |
cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7); |
1213 |
} |
1214 |
if (cond == jmp && (insn & (1 << 18))) { |
1215 |
uint8_t mask; |
1216 |
|
1217 |
mask = (~insn >> 8) & 0xff; |
1218 |
DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
|
1219 |
s->sfbr, mask, jmp ? '=' : '!', insn & mask); |
1220 |
cond = (s->sfbr & mask) == (insn & mask); |
1221 |
} |
1222 |
if (cond == jmp) {
|
1223 |
if (insn & (1 << 23)) { |
1224 |
/* Relative address. */
|
1225 |
addr = s->dsp + sxt24(addr); |
1226 |
} |
1227 |
switch ((insn >> 27) & 7) { |
1228 |
case 0: /* Jump */ |
1229 |
DPRINTF("Jump to 0x%08x\n", addr);
|
1230 |
s->dsp = addr; |
1231 |
break;
|
1232 |
case 1: /* Call */ |
1233 |
DPRINTF("Call 0x%08x\n", addr);
|
1234 |
s->temp = s->dsp; |
1235 |
s->dsp = addr; |
1236 |
break;
|
1237 |
case 2: /* Return */ |
1238 |
DPRINTF("Return to 0x%08x\n", s->temp);
|
1239 |
s->dsp = s->temp; |
1240 |
break;
|
1241 |
case 3: /* Interrupt */ |
1242 |
DPRINTF("Interrupt 0x%08x\n", s->dsps);
|
1243 |
if ((insn & (1 << 20)) != 0) { |
1244 |
s->istat0 |= LSI_ISTAT0_INTF; |
1245 |
lsi_update_irq(s); |
1246 |
} else {
|
1247 |
lsi_script_dma_interrupt(s, LSI_DSTAT_SIR); |
1248 |
} |
1249 |
break;
|
1250 |
default:
|
1251 |
DPRINTF("Illegal transfer control\n");
|
1252 |
lsi_script_dma_interrupt(s, LSI_DSTAT_IID); |
1253 |
break;
|
1254 |
} |
1255 |
} else {
|
1256 |
DPRINTF("Control condition failed\n");
|
1257 |
} |
1258 |
} |
1259 |
break;
|
1260 |
|
1261 |
case 3: |
1262 |
if ((insn & (1 << 29)) == 0) { |
1263 |
/* Memory move. */
|
1264 |
uint32_t dest; |
1265 |
/* ??? The docs imply the destination address is loaded into
|
1266 |
the TEMP register. However the Linux drivers rely on
|
1267 |
the value being presrved. */
|
1268 |
dest = read_dword(s, s->dsp); |
1269 |
s->dsp += 4;
|
1270 |
lsi_memcpy(s, dest, addr, insn & 0xffffff);
|
1271 |
} else {
|
1272 |
uint8_t data[7];
|
1273 |
int reg;
|
1274 |
int n;
|
1275 |
int i;
|
1276 |
|
1277 |
if (insn & (1 << 28)) { |
1278 |
addr = s->dsa + sxt24(addr); |
1279 |
} |
1280 |
n = (insn & 7);
|
1281 |
reg = (insn >> 16) & 0xff; |
1282 |
if (insn & (1 << 24)) { |
1283 |
cpu_physical_memory_read(addr, data, n); |
1284 |
DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
|
1285 |
addr, *(int *)data);
|
1286 |
for (i = 0; i < n; i++) { |
1287 |
lsi_reg_writeb(s, reg + i, data[i]); |
1288 |
} |
1289 |
} else {
|
1290 |
DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
|
1291 |
for (i = 0; i < n; i++) { |
1292 |
data[i] = lsi_reg_readb(s, reg + i); |
1293 |
} |
1294 |
cpu_physical_memory_write(addr, data, n); |
1295 |
} |
1296 |
} |
1297 |
} |
1298 |
if (insn_processed > 10000 && !s->waiting) { |
1299 |
/* Some windows drivers make the device spin waiting for a memory
|
1300 |
location to change. If we have been executed a lot of code then
|
1301 |
assume this is the case and force an unexpected device disconnect.
|
1302 |
This is apparently sufficient to beat the drivers into submission.
|
1303 |
*/
|
1304 |
if (!(s->sien0 & LSI_SIST0_UDC))
|
1305 |
fprintf(stderr, "inf. loop with UDC masked\n");
|
1306 |
lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
|
1307 |
lsi_disconnect(s); |
1308 |
} else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) { |
1309 |
if (s->dcntl & LSI_DCNTL_SSM) {
|
1310 |
lsi_script_dma_interrupt(s, LSI_DSTAT_SSI); |
1311 |
} else {
|
1312 |
goto again;
|
1313 |
} |
1314 |
} |
1315 |
DPRINTF("SCRIPTS execution stopped\n");
|
1316 |
} |
1317 |
|
1318 |
static uint8_t lsi_reg_readb(LSIState *s, int offset) |
1319 |
{ |
1320 |
uint8_t tmp; |
1321 |
#define CASE_GET_REG24(name, addr) \
|
1322 |
case addr: return s->name & 0xff; \ |
1323 |
case addr + 1: return (s->name >> 8) & 0xff; \ |
1324 |
case addr + 2: return (s->name >> 16) & 0xff; |
1325 |
|
1326 |
#define CASE_GET_REG32(name, addr) \
|
1327 |
case addr: return s->name & 0xff; \ |
1328 |
case addr + 1: return (s->name >> 8) & 0xff; \ |
1329 |
case addr + 2: return (s->name >> 16) & 0xff; \ |
1330 |
case addr + 3: return (s->name >> 24) & 0xff; |
1331 |
|
1332 |
#ifdef DEBUG_LSI_REG
|
1333 |
DPRINTF("Read reg %x\n", offset);
|
1334 |
#endif
|
1335 |
switch (offset) {
|
1336 |
case 0x00: /* SCNTL0 */ |
1337 |
return s->scntl0;
|
1338 |
case 0x01: /* SCNTL1 */ |
1339 |
return s->scntl1;
|
1340 |
case 0x02: /* SCNTL2 */ |
1341 |
return s->scntl2;
|
1342 |
case 0x03: /* SCNTL3 */ |
1343 |
return s->scntl3;
|
1344 |
case 0x04: /* SCID */ |
1345 |
return s->scid;
|
1346 |
case 0x05: /* SXFER */ |
1347 |
return s->sxfer;
|
1348 |
case 0x06: /* SDID */ |
1349 |
return s->sdid;
|
1350 |
case 0x07: /* GPREG0 */ |
1351 |
return 0x7f; |
1352 |
case 0x08: /* Revision ID */ |
1353 |
return 0x00; |
1354 |
case 0xa: /* SSID */ |
1355 |
return s->ssid;
|
1356 |
case 0xb: /* SBCL */ |
1357 |
/* ??? This is not correct. However it's (hopefully) only
|
1358 |
used for diagnostics, so should be ok. */
|
1359 |
return 0; |
1360 |
case 0xc: /* DSTAT */ |
1361 |
tmp = s->dstat | 0x80;
|
1362 |
if ((s->istat0 & LSI_ISTAT0_INTF) == 0) |
1363 |
s->dstat = 0;
|
1364 |
lsi_update_irq(s); |
1365 |
return tmp;
|
1366 |
case 0x0d: /* SSTAT0 */ |
1367 |
return s->sstat0;
|
1368 |
case 0x0e: /* SSTAT1 */ |
1369 |
return s->sstat1;
|
1370 |
case 0x0f: /* SSTAT2 */ |
1371 |
return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2; |
1372 |
CASE_GET_REG32(dsa, 0x10)
|
1373 |
case 0x14: /* ISTAT0 */ |
1374 |
return s->istat0;
|
1375 |
case 0x15: /* ISTAT1 */ |
1376 |
return s->istat1;
|
1377 |
case 0x16: /* MBOX0 */ |
1378 |
return s->mbox0;
|
1379 |
case 0x17: /* MBOX1 */ |
1380 |
return s->mbox1;
|
1381 |
case 0x18: /* CTEST0 */ |
1382 |
return 0xff; |
1383 |
case 0x19: /* CTEST1 */ |
1384 |
return 0; |
1385 |
case 0x1a: /* CTEST2 */ |
1386 |
tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM; |
1387 |
if (s->istat0 & LSI_ISTAT0_SIGP) {
|
1388 |
s->istat0 &= ~LSI_ISTAT0_SIGP; |
1389 |
tmp |= LSI_CTEST2_SIGP; |
1390 |
} |
1391 |
return tmp;
|
1392 |
case 0x1b: /* CTEST3 */ |
1393 |
return s->ctest3;
|
1394 |
CASE_GET_REG32(temp, 0x1c)
|
1395 |
case 0x20: /* DFIFO */ |
1396 |
return 0; |
1397 |
case 0x21: /* CTEST4 */ |
1398 |
return s->ctest4;
|
1399 |
case 0x22: /* CTEST5 */ |
1400 |
return s->ctest5;
|
1401 |
case 0x23: /* CTEST6 */ |
1402 |
return 0; |
1403 |
CASE_GET_REG24(dbc, 0x24)
|
1404 |
case 0x27: /* DCMD */ |
1405 |
return s->dcmd;
|
1406 |
CASE_GET_REG32(dsp, 0x2c)
|
1407 |
CASE_GET_REG32(dsps, 0x30)
|
1408 |
CASE_GET_REG32(scratch[0], 0x34) |
1409 |
case 0x38: /* DMODE */ |
1410 |
return s->dmode;
|
1411 |
case 0x39: /* DIEN */ |
1412 |
return s->dien;
|
1413 |
case 0x3a: /* SBR */ |
1414 |
return s->sbr;
|
1415 |
case 0x3b: /* DCNTL */ |
1416 |
return s->dcntl;
|
1417 |
case 0x40: /* SIEN0 */ |
1418 |
return s->sien0;
|
1419 |
case 0x41: /* SIEN1 */ |
1420 |
return s->sien1;
|
1421 |
case 0x42: /* SIST0 */ |
1422 |
tmp = s->sist0; |
1423 |
s->sist0 = 0;
|
1424 |
lsi_update_irq(s); |
1425 |
return tmp;
|
1426 |
case 0x43: /* SIST1 */ |
1427 |
tmp = s->sist1; |
1428 |
s->sist1 = 0;
|
1429 |
lsi_update_irq(s); |
1430 |
return tmp;
|
1431 |
case 0x46: /* MACNTL */ |
1432 |
return 0x0f; |
1433 |
case 0x47: /* GPCNTL0 */ |
1434 |
return 0x0f; |
1435 |
case 0x48: /* STIME0 */ |
1436 |
return s->stime0;
|
1437 |
case 0x4a: /* RESPID0 */ |
1438 |
return s->respid0;
|
1439 |
case 0x4b: /* RESPID1 */ |
1440 |
return s->respid1;
|
1441 |
case 0x4d: /* STEST1 */ |
1442 |
return s->stest1;
|
1443 |
case 0x4e: /* STEST2 */ |
1444 |
return s->stest2;
|
1445 |
case 0x4f: /* STEST3 */ |
1446 |
return s->stest3;
|
1447 |
case 0x50: /* SIDL */ |
1448 |
/* This is needed by the linux drivers. We currently only update it
|
1449 |
during the MSG IN phase. */
|
1450 |
return s->sidl;
|
1451 |
case 0x52: /* STEST4 */ |
1452 |
return 0xe0; |
1453 |
case 0x56: /* CCNTL0 */ |
1454 |
return s->ccntl0;
|
1455 |
case 0x57: /* CCNTL1 */ |
1456 |
return s->ccntl1;
|
1457 |
case 0x58: /* SBDL */ |
1458 |
/* Some drivers peek at the data bus during the MSG IN phase. */
|
1459 |
if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
|
1460 |
return s->msg[0]; |
1461 |
return 0; |
1462 |
case 0x59: /* SBDL high */ |
1463 |
return 0; |
1464 |
CASE_GET_REG32(mmrs, 0xa0)
|
1465 |
CASE_GET_REG32(mmws, 0xa4)
|
1466 |
CASE_GET_REG32(sfs, 0xa8)
|
1467 |
CASE_GET_REG32(drs, 0xac)
|
1468 |
CASE_GET_REG32(sbms, 0xb0)
|
1469 |
CASE_GET_REG32(dbms, 0xb4)
|
1470 |
CASE_GET_REG32(dnad64, 0xb8)
|
1471 |
CASE_GET_REG32(pmjad1, 0xc0)
|
1472 |
CASE_GET_REG32(pmjad2, 0xc4)
|
1473 |
CASE_GET_REG32(rbc, 0xc8)
|
1474 |
CASE_GET_REG32(ua, 0xcc)
|
1475 |
CASE_GET_REG32(ia, 0xd4)
|
1476 |
CASE_GET_REG32(sbc, 0xd8)
|
1477 |
CASE_GET_REG32(csbc, 0xdc)
|
1478 |
} |
1479 |
if (offset >= 0x5c && offset < 0xa0) { |
1480 |
int n;
|
1481 |
int shift;
|
1482 |
n = (offset - 0x58) >> 2; |
1483 |
shift = (offset & 3) * 8; |
1484 |
return (s->scratch[n] >> shift) & 0xff; |
1485 |
} |
1486 |
BADF("readb 0x%x\n", offset);
|
1487 |
exit(1);
|
1488 |
#undef CASE_GET_REG24
|
1489 |
#undef CASE_GET_REG32
|
1490 |
} |
1491 |
|
1492 |
static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) |
1493 |
{ |
1494 |
#define CASE_SET_REG32(name, addr) \
|
1495 |
case addr : s->name &= 0xffffff00; s->name |= val; break; \ |
1496 |
case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \ |
1497 |
case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \ |
1498 |
case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break; |
1499 |
|
1500 |
#ifdef DEBUG_LSI_REG
|
1501 |
DPRINTF("Write reg %x = %02x\n", offset, val);
|
1502 |
#endif
|
1503 |
switch (offset) {
|
1504 |
case 0x00: /* SCNTL0 */ |
1505 |
s->scntl0 = val; |
1506 |
if (val & LSI_SCNTL0_START) {
|
1507 |
BADF("Start sequence not implemented\n");
|
1508 |
} |
1509 |
break;
|
1510 |
case 0x01: /* SCNTL1 */ |
1511 |
s->scntl1 = val & ~LSI_SCNTL1_SST; |
1512 |
if (val & LSI_SCNTL1_IARB) {
|
1513 |
BADF("Immediate Arbritration not implemented\n");
|
1514 |
} |
1515 |
if (val & LSI_SCNTL1_RST) {
|
1516 |
s->sstat0 |= LSI_SSTAT0_RST; |
1517 |
lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
|
1518 |
} else {
|
1519 |
s->sstat0 &= ~LSI_SSTAT0_RST; |
1520 |
} |
1521 |
break;
|
1522 |
case 0x02: /* SCNTL2 */ |
1523 |
val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS); |
1524 |
s->scntl2 = val; |
1525 |
break;
|
1526 |
case 0x03: /* SCNTL3 */ |
1527 |
s->scntl3 = val; |
1528 |
break;
|
1529 |
case 0x04: /* SCID */ |
1530 |
s->scid = val; |
1531 |
break;
|
1532 |
case 0x05: /* SXFER */ |
1533 |
s->sxfer = val; |
1534 |
break;
|
1535 |
case 0x06: /* SDID */ |
1536 |
if ((val & 0xf) != (s->ssid & 0xf)) |
1537 |
BADF("Destination ID does not match SSID\n");
|
1538 |
s->sdid = val & 0xf;
|
1539 |
break;
|
1540 |
case 0x07: /* GPREG0 */ |
1541 |
break;
|
1542 |
case 0x08: /* SFBR */ |
1543 |
/* The CPU is not allowed to write to this register. However the
|
1544 |
SCRIPTS register move instructions are. */
|
1545 |
s->sfbr = val; |
1546 |
break;
|
1547 |
case 0x0a: case 0x0b: |
1548 |
/* Openserver writes to these readonly registers on startup */
|
1549 |
return;
|
1550 |
case 0x0c: case 0x0d: case 0x0e: case 0x0f: |
1551 |
/* Linux writes to these readonly registers on startup. */
|
1552 |
return;
|
1553 |
CASE_SET_REG32(dsa, 0x10)
|
1554 |
case 0x14: /* ISTAT0 */ |
1555 |
s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0); |
1556 |
if (val & LSI_ISTAT0_ABRT) {
|
1557 |
lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT); |
1558 |
} |
1559 |
if (val & LSI_ISTAT0_INTF) {
|
1560 |
s->istat0 &= ~LSI_ISTAT0_INTF; |
1561 |
lsi_update_irq(s); |
1562 |
} |
1563 |
if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) { |
1564 |
DPRINTF("Woken by SIGP\n");
|
1565 |
s->waiting = 0;
|
1566 |
s->dsp = s->dnad; |
1567 |
lsi_execute_script(s); |
1568 |
} |
1569 |
if (val & LSI_ISTAT0_SRST) {
|
1570 |
lsi_soft_reset(s); |
1571 |
} |
1572 |
break;
|
1573 |
case 0x16: /* MBOX0 */ |
1574 |
s->mbox0 = val; |
1575 |
break;
|
1576 |
case 0x17: /* MBOX1 */ |
1577 |
s->mbox1 = val; |
1578 |
break;
|
1579 |
case 0x1a: /* CTEST2 */ |
1580 |
s->ctest2 = val & LSI_CTEST2_PCICIE; |
1581 |
break;
|
1582 |
case 0x1b: /* CTEST3 */ |
1583 |
s->ctest3 = val & 0x0f;
|
1584 |
break;
|
1585 |
CASE_SET_REG32(temp, 0x1c)
|
1586 |
case 0x21: /* CTEST4 */ |
1587 |
if (val & 7) { |
1588 |
BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
|
1589 |
} |
1590 |
s->ctest4 = val; |
1591 |
break;
|
1592 |
case 0x22: /* CTEST5 */ |
1593 |
if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
|
1594 |
BADF("CTEST5 DMA increment not implemented\n");
|
1595 |
} |
1596 |
s->ctest5 = val; |
1597 |
break;
|
1598 |
case 0x2c: /* DSP[0:7] */ |
1599 |
s->dsp &= 0xffffff00;
|
1600 |
s->dsp |= val; |
1601 |
break;
|
1602 |
case 0x2d: /* DSP[8:15] */ |
1603 |
s->dsp &= 0xffff00ff;
|
1604 |
s->dsp |= val << 8;
|
1605 |
break;
|
1606 |
case 0x2e: /* DSP[16:23] */ |
1607 |
s->dsp &= 0xff00ffff;
|
1608 |
s->dsp |= val << 16;
|
1609 |
break;
|
1610 |
case 0x2f: /* DSP[24:31] */ |
1611 |
s->dsp &= 0x00ffffff;
|
1612 |
s->dsp |= val << 24;
|
1613 |
if ((s->dmode & LSI_DMODE_MAN) == 0 |
1614 |
&& (s->istat1 & LSI_ISTAT1_SRUN) == 0)
|
1615 |
lsi_execute_script(s); |
1616 |
break;
|
1617 |
CASE_SET_REG32(dsps, 0x30)
|
1618 |
CASE_SET_REG32(scratch[0], 0x34) |
1619 |
case 0x38: /* DMODE */ |
1620 |
if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
|
1621 |
BADF("IO mappings not implemented\n");
|
1622 |
} |
1623 |
s->dmode = val; |
1624 |
break;
|
1625 |
case 0x39: /* DIEN */ |
1626 |
s->dien = val; |
1627 |
lsi_update_irq(s); |
1628 |
break;
|
1629 |
case 0x3a: /* SBR */ |
1630 |
s->sbr = val; |
1631 |
break;
|
1632 |
case 0x3b: /* DCNTL */ |
1633 |
s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD); |
1634 |
if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0) |
1635 |
lsi_execute_script(s); |
1636 |
break;
|
1637 |
case 0x40: /* SIEN0 */ |
1638 |
s->sien0 = val; |
1639 |
lsi_update_irq(s); |
1640 |
break;
|
1641 |
case 0x41: /* SIEN1 */ |
1642 |
s->sien1 = val; |
1643 |
lsi_update_irq(s); |
1644 |
break;
|
1645 |
case 0x47: /* GPCNTL0 */ |
1646 |
break;
|
1647 |
case 0x48: /* STIME0 */ |
1648 |
s->stime0 = val; |
1649 |
break;
|
1650 |
case 0x49: /* STIME1 */ |
1651 |
if (val & 0xf) { |
1652 |
DPRINTF("General purpose timer not implemented\n");
|
1653 |
/* ??? Raising the interrupt immediately seems to be sufficient
|
1654 |
to keep the FreeBSD driver happy. */
|
1655 |
lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
|
1656 |
} |
1657 |
break;
|
1658 |
case 0x4a: /* RESPID0 */ |
1659 |
s->respid0 = val; |
1660 |
break;
|
1661 |
case 0x4b: /* RESPID1 */ |
1662 |
s->respid1 = val; |
1663 |
break;
|
1664 |
case 0x4d: /* STEST1 */ |
1665 |
s->stest1 = val; |
1666 |
break;
|
1667 |
case 0x4e: /* STEST2 */ |
1668 |
if (val & 1) { |
1669 |
BADF("Low level mode not implemented\n");
|
1670 |
} |
1671 |
s->stest2 = val; |
1672 |
break;
|
1673 |
case 0x4f: /* STEST3 */ |
1674 |
if (val & 0x41) { |
1675 |
BADF("SCSI FIFO test mode not implemented\n");
|
1676 |
} |
1677 |
s->stest3 = val; |
1678 |
break;
|
1679 |
case 0x56: /* CCNTL0 */ |
1680 |
s->ccntl0 = val; |
1681 |
break;
|
1682 |
case 0x57: /* CCNTL1 */ |
1683 |
s->ccntl1 = val; |
1684 |
break;
|
1685 |
CASE_SET_REG32(mmrs, 0xa0)
|
1686 |
CASE_SET_REG32(mmws, 0xa4)
|
1687 |
CASE_SET_REG32(sfs, 0xa8)
|
1688 |
CASE_SET_REG32(drs, 0xac)
|
1689 |
CASE_SET_REG32(sbms, 0xb0)
|
1690 |
CASE_SET_REG32(dbms, 0xb4)
|
1691 |
CASE_SET_REG32(dnad64, 0xb8)
|
1692 |
CASE_SET_REG32(pmjad1, 0xc0)
|
1693 |
CASE_SET_REG32(pmjad2, 0xc4)
|
1694 |
CASE_SET_REG32(rbc, 0xc8)
|
1695 |
CASE_SET_REG32(ua, 0xcc)
|
1696 |
CASE_SET_REG32(ia, 0xd4)
|
1697 |
CASE_SET_REG32(sbc, 0xd8)
|
1698 |
CASE_SET_REG32(csbc, 0xdc)
|
1699 |
default:
|
1700 |
if (offset >= 0x5c && offset < 0xa0) { |
1701 |
int n;
|
1702 |
int shift;
|
1703 |
n = (offset - 0x58) >> 2; |
1704 |
shift = (offset & 3) * 8; |
1705 |
s->scratch[n] &= ~(0xff << shift);
|
1706 |
s->scratch[n] |= (val & 0xff) << shift;
|
1707 |
} else {
|
1708 |
BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
|
1709 |
} |
1710 |
} |
1711 |
#undef CASE_SET_REG32
|
1712 |
} |
1713 |
|
1714 |
static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1715 |
{ |
1716 |
LSIState *s = (LSIState *)opaque; |
1717 |
|
1718 |
lsi_reg_writeb(s, addr & 0xff, val);
|
1719 |
} |
1720 |
|
1721 |
static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1722 |
{ |
1723 |
LSIState *s = (LSIState *)opaque; |
1724 |
|
1725 |
addr &= 0xff;
|
1726 |
lsi_reg_writeb(s, addr, val & 0xff);
|
1727 |
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1728 |
} |
1729 |
|
1730 |
static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1731 |
{ |
1732 |
LSIState *s = (LSIState *)opaque; |
1733 |
|
1734 |
addr &= 0xff;
|
1735 |
lsi_reg_writeb(s, addr, val & 0xff);
|
1736 |
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1737 |
lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); |
1738 |
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); |
1739 |
} |
1740 |
|
1741 |
static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr) |
1742 |
{ |
1743 |
LSIState *s = (LSIState *)opaque; |
1744 |
|
1745 |
return lsi_reg_readb(s, addr & 0xff); |
1746 |
} |
1747 |
|
1748 |
static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) |
1749 |
{ |
1750 |
LSIState *s = (LSIState *)opaque; |
1751 |
uint32_t val; |
1752 |
|
1753 |
addr &= 0xff;
|
1754 |
val = lsi_reg_readb(s, addr); |
1755 |
val |= lsi_reg_readb(s, addr + 1) << 8; |
1756 |
return val;
|
1757 |
} |
1758 |
|
1759 |
static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr) |
1760 |
{ |
1761 |
LSIState *s = (LSIState *)opaque; |
1762 |
uint32_t val; |
1763 |
addr &= 0xff;
|
1764 |
val = lsi_reg_readb(s, addr); |
1765 |
val |= lsi_reg_readb(s, addr + 1) << 8; |
1766 |
val |= lsi_reg_readb(s, addr + 2) << 16; |
1767 |
val |= lsi_reg_readb(s, addr + 3) << 24; |
1768 |
return val;
|
1769 |
} |
1770 |
|
1771 |
static CPUReadMemoryFunc *lsi_mmio_readfn[3] = { |
1772 |
lsi_mmio_readb, |
1773 |
lsi_mmio_readw, |
1774 |
lsi_mmio_readl, |
1775 |
}; |
1776 |
|
1777 |
static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = { |
1778 |
lsi_mmio_writeb, |
1779 |
lsi_mmio_writew, |
1780 |
lsi_mmio_writel, |
1781 |
}; |
1782 |
|
1783 |
static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
1784 |
{ |
1785 |
LSIState *s = (LSIState *)opaque; |
1786 |
uint32_t newval; |
1787 |
int shift;
|
1788 |
|
1789 |
addr &= 0x1fff;
|
1790 |
newval = s->script_ram[addr >> 2];
|
1791 |
shift = (addr & 3) * 8; |
1792 |
newval &= ~(0xff << shift);
|
1793 |
newval |= val << shift; |
1794 |
s->script_ram[addr >> 2] = newval;
|
1795 |
} |
1796 |
|
1797 |
static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
1798 |
{ |
1799 |
LSIState *s = (LSIState *)opaque; |
1800 |
uint32_t newval; |
1801 |
|
1802 |
addr &= 0x1fff;
|
1803 |
newval = s->script_ram[addr >> 2];
|
1804 |
if (addr & 2) { |
1805 |
newval = (newval & 0xffff) | (val << 16); |
1806 |
} else {
|
1807 |
newval = (newval & 0xffff0000) | val;
|
1808 |
} |
1809 |
s->script_ram[addr >> 2] = newval;
|
1810 |
} |
1811 |
|
1812 |
|
1813 |
static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1814 |
{ |
1815 |
LSIState *s = (LSIState *)opaque; |
1816 |
|
1817 |
addr &= 0x1fff;
|
1818 |
s->script_ram[addr >> 2] = val;
|
1819 |
} |
1820 |
|
1821 |
static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) |
1822 |
{ |
1823 |
LSIState *s = (LSIState *)opaque; |
1824 |
uint32_t val; |
1825 |
|
1826 |
addr &= 0x1fff;
|
1827 |
val = s->script_ram[addr >> 2];
|
1828 |
val >>= (addr & 3) * 8; |
1829 |
return val & 0xff; |
1830 |
} |
1831 |
|
1832 |
static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) |
1833 |
{ |
1834 |
LSIState *s = (LSIState *)opaque; |
1835 |
uint32_t val; |
1836 |
|
1837 |
addr &= 0x1fff;
|
1838 |
val = s->script_ram[addr >> 2];
|
1839 |
if (addr & 2) |
1840 |
val >>= 16;
|
1841 |
return le16_to_cpu(val);
|
1842 |
} |
1843 |
|
1844 |
static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr) |
1845 |
{ |
1846 |
LSIState *s = (LSIState *)opaque; |
1847 |
|
1848 |
addr &= 0x1fff;
|
1849 |
return le32_to_cpu(s->script_ram[addr >> 2]); |
1850 |
} |
1851 |
|
1852 |
static CPUReadMemoryFunc *lsi_ram_readfn[3] = { |
1853 |
lsi_ram_readb, |
1854 |
lsi_ram_readw, |
1855 |
lsi_ram_readl, |
1856 |
}; |
1857 |
|
1858 |
static CPUWriteMemoryFunc *lsi_ram_writefn[3] = { |
1859 |
lsi_ram_writeb, |
1860 |
lsi_ram_writew, |
1861 |
lsi_ram_writel, |
1862 |
}; |
1863 |
|
1864 |
static uint32_t lsi_io_readb(void *opaque, uint32_t addr) |
1865 |
{ |
1866 |
LSIState *s = (LSIState *)opaque; |
1867 |
return lsi_reg_readb(s, addr & 0xff); |
1868 |
} |
1869 |
|
1870 |
static uint32_t lsi_io_readw(void *opaque, uint32_t addr) |
1871 |
{ |
1872 |
LSIState *s = (LSIState *)opaque; |
1873 |
uint32_t val; |
1874 |
addr &= 0xff;
|
1875 |
val = lsi_reg_readb(s, addr); |
1876 |
val |= lsi_reg_readb(s, addr + 1) << 8; |
1877 |
return val;
|
1878 |
} |
1879 |
|
1880 |
static uint32_t lsi_io_readl(void *opaque, uint32_t addr) |
1881 |
{ |
1882 |
LSIState *s = (LSIState *)opaque; |
1883 |
uint32_t val; |
1884 |
addr &= 0xff;
|
1885 |
val = lsi_reg_readb(s, addr); |
1886 |
val |= lsi_reg_readb(s, addr + 1) << 8; |
1887 |
val |= lsi_reg_readb(s, addr + 2) << 16; |
1888 |
val |= lsi_reg_readb(s, addr + 3) << 24; |
1889 |
return val;
|
1890 |
} |
1891 |
|
1892 |
static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val) |
1893 |
{ |
1894 |
LSIState *s = (LSIState *)opaque; |
1895 |
lsi_reg_writeb(s, addr & 0xff, val);
|
1896 |
} |
1897 |
|
1898 |
static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val) |
1899 |
{ |
1900 |
LSIState *s = (LSIState *)opaque; |
1901 |
addr &= 0xff;
|
1902 |
lsi_reg_writeb(s, addr, val & 0xff);
|
1903 |
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1904 |
} |
1905 |
|
1906 |
static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val) |
1907 |
{ |
1908 |
LSIState *s = (LSIState *)opaque; |
1909 |
addr &= 0xff;
|
1910 |
lsi_reg_writeb(s, addr, val & 0xff);
|
1911 |
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); |
1912 |
lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); |
1913 |
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); |
1914 |
} |
1915 |
|
1916 |
static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num, |
1917 |
uint32_t addr, uint32_t size, int type)
|
1918 |
{ |
1919 |
LSIState *s = (LSIState *)pci_dev; |
1920 |
|
1921 |
DPRINTF("Mapping IO at %08x\n", addr);
|
1922 |
|
1923 |
register_ioport_write(addr, 256, 1, lsi_io_writeb, s); |
1924 |
register_ioport_read(addr, 256, 1, lsi_io_readb, s); |
1925 |
register_ioport_write(addr, 256, 2, lsi_io_writew, s); |
1926 |
register_ioport_read(addr, 256, 2, lsi_io_readw, s); |
1927 |
register_ioport_write(addr, 256, 4, lsi_io_writel, s); |
1928 |
register_ioport_read(addr, 256, 4, lsi_io_readl, s); |
1929 |
} |
1930 |
|
1931 |
static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num, |
1932 |
uint32_t addr, uint32_t size, int type)
|
1933 |
{ |
1934 |
LSIState *s = (LSIState *)pci_dev; |
1935 |
|
1936 |
DPRINTF("Mapping ram at %08x\n", addr);
|
1937 |
s->script_ram_base = addr; |
1938 |
cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr); |
1939 |
} |
1940 |
|
1941 |
static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
1942 |
uint32_t addr, uint32_t size, int type)
|
1943 |
{ |
1944 |
LSIState *s = (LSIState *)pci_dev; |
1945 |
|
1946 |
DPRINTF("Mapping registers at %08x\n", addr);
|
1947 |
cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr); |
1948 |
} |
1949 |
|
1950 |
void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id) |
1951 |
{ |
1952 |
LSIState *s = (LSIState *)host; |
1953 |
|
1954 |
if (id < 0) { |
1955 |
for (id = 0; id < LSI_MAX_DEVS; id++) { |
1956 |
if (s->scsi_dev[id] == NULL) |
1957 |
break;
|
1958 |
} |
1959 |
} |
1960 |
if (id >= LSI_MAX_DEVS) {
|
1961 |
BADF("Bad Device ID %d\n", id);
|
1962 |
return;
|
1963 |
} |
1964 |
if (s->scsi_dev[id]) {
|
1965 |
DPRINTF("Destroying device %d\n", id);
|
1966 |
s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
1967 |
} |
1968 |
DPRINTF("Attaching block device %d\n", id);
|
1969 |
s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
|
1970 |
if (s->scsi_dev[id] == NULL) |
1971 |
s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
|
1972 |
bd->private = &s->pci_dev; |
1973 |
} |
1974 |
|
1975 |
static int lsi_scsi_uninit(PCIDevice *d) |
1976 |
{ |
1977 |
LSIState *s = (LSIState *) d; |
1978 |
|
1979 |
cpu_unregister_io_memory(s->mmio_io_addr); |
1980 |
cpu_unregister_io_memory(s->ram_io_addr); |
1981 |
|
1982 |
qemu_free(s->queue); |
1983 |
|
1984 |
return 0; |
1985 |
} |
1986 |
|
1987 |
static void lsi_scsi_init(PCIDevice *dev) |
1988 |
{ |
1989 |
LSIState *s = (LSIState *)dev; |
1990 |
uint8_t *pci_conf; |
1991 |
|
1992 |
pci_conf = s->pci_dev.config; |
1993 |
|
1994 |
/* PCI Vendor ID (word) */
|
1995 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC); |
1996 |
/* PCI device ID (word) */
|
1997 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A); |
1998 |
/* PCI base class code */
|
1999 |
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI); |
2000 |
/* PCI subsystem ID */
|
2001 |
pci_conf[0x2e] = 0x00; |
2002 |
pci_conf[0x2f] = 0x10; |
2003 |
/* PCI latency timer = 255 */
|
2004 |
pci_conf[0x0d] = 0xff; |
2005 |
/* Interrupt pin 1 */
|
2006 |
pci_conf[0x3d] = 0x01; |
2007 |
|
2008 |
s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn, |
2009 |
lsi_mmio_writefn, s); |
2010 |
s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn, |
2011 |
lsi_ram_writefn, s); |
2012 |
|
2013 |
pci_register_bar((struct PCIDevice *)s, 0, 256, |
2014 |
PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc); |
2015 |
pci_register_bar((struct PCIDevice *)s, 1, 0x400, |
2016 |
PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc); |
2017 |
pci_register_bar((struct PCIDevice *)s, 2, 0x2000, |
2018 |
PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc); |
2019 |
s->queue = qemu_malloc(sizeof(lsi_queue));
|
2020 |
s->queue_len = 1;
|
2021 |
s->active_commands = 0;
|
2022 |
s->pci_dev.unregister = lsi_scsi_uninit; |
2023 |
|
2024 |
lsi_soft_reset(s); |
2025 |
|
2026 |
scsi_bus_new(&dev->qdev, lsi_scsi_attach); |
2027 |
} |
2028 |
|
2029 |
static void lsi53c895a_register_devices(void) |
2030 |
{ |
2031 |
pci_qdev_register("lsi53c895a", sizeof(LSIState), lsi_scsi_init); |
2032 |
} |
2033 |
|
2034 |
device_init(lsi53c895a_register_devices); |