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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 16450 UART emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-char.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 80cabfad | bellard | |
29 | 80cabfad | bellard | //#define DEBUG_SERIAL
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30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
32 | 80cabfad | bellard | |
33 | 80cabfad | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
34 | 80cabfad | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
35 | 80cabfad | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
36 | 80cabfad | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
37 | 80cabfad | bellard | |
38 | 80cabfad | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
39 | 80cabfad | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
40 | 80cabfad | bellard | |
41 | 80cabfad | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
42 | 80cabfad | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
43 | 80cabfad | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
44 | 80cabfad | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
45 | 80cabfad | bellard | |
46 | 80cabfad | bellard | /*
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47 | 80cabfad | bellard | * These are the definitions for the Modem Control Register
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48 | 80cabfad | bellard | */
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49 | 80cabfad | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
50 | 80cabfad | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
51 | 80cabfad | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
52 | 80cabfad | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
53 | 80cabfad | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
54 | 80cabfad | bellard | |
55 | 80cabfad | bellard | /*
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56 | 80cabfad | bellard | * These are the definitions for the Modem Status Register
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57 | 80cabfad | bellard | */
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58 | 80cabfad | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
59 | 80cabfad | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
60 | 80cabfad | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
61 | 80cabfad | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
62 | 80cabfad | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
63 | 80cabfad | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
64 | 80cabfad | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
65 | 80cabfad | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
66 | 80cabfad | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
67 | 80cabfad | bellard | |
68 | 80cabfad | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
69 | 80cabfad | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
70 | 80cabfad | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
71 | 80cabfad | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
72 | 80cabfad | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
73 | 80cabfad | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
74 | 80cabfad | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
75 | 80cabfad | bellard | |
76 | b41a2cd1 | bellard | struct SerialState {
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77 | 508d92d0 | bellard | uint16_t divider; |
78 | 80cabfad | bellard | uint8_t rbr; /* receive register */
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79 | 80cabfad | bellard | uint8_t ier; |
80 | 80cabfad | bellard | uint8_t iir; /* read only */
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81 | 80cabfad | bellard | uint8_t lcr; |
82 | 80cabfad | bellard | uint8_t mcr; |
83 | 80cabfad | bellard | uint8_t lsr; /* read only */
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84 | 3e749fe1 | bellard | uint8_t msr; /* read only */
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85 | 80cabfad | bellard | uint8_t scr; |
86 | 80cabfad | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
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87 | 80cabfad | bellard | it can be reset while reading iir */
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88 | 80cabfad | bellard | int thr_ipending;
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89 | d537cf6c | pbrook | qemu_irq irq; |
90 | 82c643ff | bellard | CharDriverState *chr; |
91 | f8d179e3 | bellard | int last_break_enable;
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92 | 71db710f | blueswir1 | target_phys_addr_t base; |
93 | e5d13e2f | bellard | int it_shift;
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94 | b41a2cd1 | bellard | }; |
95 | 80cabfad | bellard | |
96 | b41a2cd1 | bellard | static void serial_update_irq(SerialState *s) |
97 | 80cabfad | bellard | { |
98 | 80cabfad | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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99 | 80cabfad | bellard | s->iir = UART_IIR_RDI; |
100 | 80cabfad | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
101 | 80cabfad | bellard | s->iir = UART_IIR_THRI; |
102 | 80cabfad | bellard | } else {
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103 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
104 | 80cabfad | bellard | } |
105 | 80cabfad | bellard | if (s->iir != UART_IIR_NO_INT) {
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106 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
107 | 80cabfad | bellard | } else {
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108 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
109 | 80cabfad | bellard | } |
110 | 80cabfad | bellard | } |
111 | 80cabfad | bellard | |
112 | f8d179e3 | bellard | static void serial_update_parameters(SerialState *s) |
113 | f8d179e3 | bellard | { |
114 | f8d179e3 | bellard | int speed, parity, data_bits, stop_bits;
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115 | 2122c51a | bellard | QEMUSerialSetParams ssp; |
116 | f8d179e3 | bellard | |
117 | f8d179e3 | bellard | if (s->lcr & 0x08) { |
118 | f8d179e3 | bellard | if (s->lcr & 0x10) |
119 | f8d179e3 | bellard | parity = 'E';
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120 | f8d179e3 | bellard | else
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121 | f8d179e3 | bellard | parity = 'O';
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122 | f8d179e3 | bellard | } else {
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123 | f8d179e3 | bellard | parity = 'N';
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124 | f8d179e3 | bellard | } |
125 | 5fafdf24 | ths | if (s->lcr & 0x04) |
126 | f8d179e3 | bellard | stop_bits = 2;
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127 | f8d179e3 | bellard | else
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128 | f8d179e3 | bellard | stop_bits = 1;
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129 | f8d179e3 | bellard | data_bits = (s->lcr & 0x03) + 5; |
130 | f8d179e3 | bellard | if (s->divider == 0) |
131 | f8d179e3 | bellard | return;
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132 | f8d179e3 | bellard | speed = 115200 / s->divider;
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133 | 2122c51a | bellard | ssp.speed = speed; |
134 | 2122c51a | bellard | ssp.parity = parity; |
135 | 2122c51a | bellard | ssp.data_bits = data_bits; |
136 | 2122c51a | bellard | ssp.stop_bits = stop_bits; |
137 | 2122c51a | bellard | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
138 | 2122c51a | bellard | #if 0
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139 | 5fafdf24 | ths | printf("speed=%d parity=%c data=%d stop=%d\n",
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140 | f8d179e3 | bellard | speed, parity, data_bits, stop_bits);
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141 | f8d179e3 | bellard | #endif
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142 | f8d179e3 | bellard | } |
143 | f8d179e3 | bellard | |
144 | b41a2cd1 | bellard | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
145 | 80cabfad | bellard | { |
146 | b41a2cd1 | bellard | SerialState *s = opaque; |
147 | 80cabfad | bellard | unsigned char ch; |
148 | 3b46e624 | ths | |
149 | 80cabfad | bellard | addr &= 7;
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150 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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151 | 80cabfad | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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152 | 80cabfad | bellard | #endif
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153 | 80cabfad | bellard | switch(addr) {
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154 | 80cabfad | bellard | default:
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155 | 80cabfad | bellard | case 0: |
156 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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157 | 80cabfad | bellard | s->divider = (s->divider & 0xff00) | val;
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158 | f8d179e3 | bellard | serial_update_parameters(s); |
159 | 80cabfad | bellard | } else {
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160 | 80cabfad | bellard | s->thr_ipending = 0;
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161 | 80cabfad | bellard | s->lsr &= ~UART_LSR_THRE; |
162 | b41a2cd1 | bellard | serial_update_irq(s); |
163 | 82c643ff | bellard | ch = val; |
164 | 82c643ff | bellard | qemu_chr_write(s->chr, &ch, 1);
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165 | 80cabfad | bellard | s->thr_ipending = 1;
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166 | 80cabfad | bellard | s->lsr |= UART_LSR_THRE; |
167 | 80cabfad | bellard | s->lsr |= UART_LSR_TEMT; |
168 | b41a2cd1 | bellard | serial_update_irq(s); |
169 | 80cabfad | bellard | } |
170 | 80cabfad | bellard | break;
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171 | 80cabfad | bellard | case 1: |
172 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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173 | 80cabfad | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
174 | f8d179e3 | bellard | serial_update_parameters(s); |
175 | 80cabfad | bellard | } else {
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176 | 60e336db | bellard | s->ier = val & 0x0f;
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177 | 60e336db | bellard | if (s->lsr & UART_LSR_THRE) {
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178 | 60e336db | bellard | s->thr_ipending = 1;
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179 | 60e336db | bellard | } |
180 | b41a2cd1 | bellard | serial_update_irq(s); |
181 | 80cabfad | bellard | } |
182 | 80cabfad | bellard | break;
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183 | 80cabfad | bellard | case 2: |
184 | 80cabfad | bellard | break;
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185 | 80cabfad | bellard | case 3: |
186 | f8d179e3 | bellard | { |
187 | f8d179e3 | bellard | int break_enable;
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188 | f8d179e3 | bellard | s->lcr = val; |
189 | f8d179e3 | bellard | serial_update_parameters(s); |
190 | f8d179e3 | bellard | break_enable = (val >> 6) & 1; |
191 | f8d179e3 | bellard | if (break_enable != s->last_break_enable) {
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192 | f8d179e3 | bellard | s->last_break_enable = break_enable; |
193 | 5fafdf24 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
194 | 2122c51a | bellard | &break_enable); |
195 | f8d179e3 | bellard | } |
196 | f8d179e3 | bellard | } |
197 | 80cabfad | bellard | break;
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198 | 80cabfad | bellard | case 4: |
199 | 60e336db | bellard | s->mcr = val & 0x1f;
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200 | 80cabfad | bellard | break;
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201 | 80cabfad | bellard | case 5: |
202 | 80cabfad | bellard | break;
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203 | 80cabfad | bellard | case 6: |
204 | 80cabfad | bellard | break;
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205 | 80cabfad | bellard | case 7: |
206 | 80cabfad | bellard | s->scr = val; |
207 | 80cabfad | bellard | break;
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208 | 80cabfad | bellard | } |
209 | 80cabfad | bellard | } |
210 | 80cabfad | bellard | |
211 | b41a2cd1 | bellard | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
212 | 80cabfad | bellard | { |
213 | b41a2cd1 | bellard | SerialState *s = opaque; |
214 | 80cabfad | bellard | uint32_t ret; |
215 | 80cabfad | bellard | |
216 | 80cabfad | bellard | addr &= 7;
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217 | 80cabfad | bellard | switch(addr) {
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218 | 80cabfad | bellard | default:
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219 | 80cabfad | bellard | case 0: |
220 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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221 | 5fafdf24 | ths | ret = s->divider & 0xff;
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222 | 80cabfad | bellard | } else {
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223 | 80cabfad | bellard | ret = s->rbr; |
224 | 80cabfad | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
225 | b41a2cd1 | bellard | serial_update_irq(s); |
226 | bd9bdce6 | balrog | qemu_chr_accept_input(s->chr); |
227 | 80cabfad | bellard | } |
228 | 80cabfad | bellard | break;
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229 | 80cabfad | bellard | case 1: |
230 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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231 | 80cabfad | bellard | ret = (s->divider >> 8) & 0xff; |
232 | 80cabfad | bellard | } else {
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233 | 80cabfad | bellard | ret = s->ier; |
234 | 80cabfad | bellard | } |
235 | 80cabfad | bellard | break;
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236 | 80cabfad | bellard | case 2: |
237 | 80cabfad | bellard | ret = s->iir; |
238 | 80cabfad | bellard | /* reset THR pending bit */
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239 | 80cabfad | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
240 | 80cabfad | bellard | s->thr_ipending = 0;
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241 | b41a2cd1 | bellard | serial_update_irq(s); |
242 | 80cabfad | bellard | break;
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243 | 80cabfad | bellard | case 3: |
244 | 80cabfad | bellard | ret = s->lcr; |
245 | 80cabfad | bellard | break;
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246 | 80cabfad | bellard | case 4: |
247 | 80cabfad | bellard | ret = s->mcr; |
248 | 80cabfad | bellard | break;
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249 | 80cabfad | bellard | case 5: |
250 | 80cabfad | bellard | ret = s->lsr; |
251 | 80cabfad | bellard | break;
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252 | 80cabfad | bellard | case 6: |
253 | 80cabfad | bellard | if (s->mcr & UART_MCR_LOOP) {
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254 | 80cabfad | bellard | /* in loopback, the modem output pins are connected to the
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255 | 80cabfad | bellard | inputs */
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256 | 80cabfad | bellard | ret = (s->mcr & 0x0c) << 4; |
257 | 80cabfad | bellard | ret |= (s->mcr & 0x02) << 3; |
258 | 80cabfad | bellard | ret |= (s->mcr & 0x01) << 5; |
259 | 80cabfad | bellard | } else {
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260 | 80cabfad | bellard | ret = s->msr; |
261 | 80cabfad | bellard | } |
262 | 80cabfad | bellard | break;
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263 | 80cabfad | bellard | case 7: |
264 | 80cabfad | bellard | ret = s->scr; |
265 | 80cabfad | bellard | break;
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266 | 80cabfad | bellard | } |
267 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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268 | 80cabfad | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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269 | 80cabfad | bellard | #endif
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270 | 80cabfad | bellard | return ret;
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271 | 80cabfad | bellard | } |
272 | 80cabfad | bellard | |
273 | 82c643ff | bellard | static int serial_can_receive(SerialState *s) |
274 | 80cabfad | bellard | { |
275 | 80cabfad | bellard | return !(s->lsr & UART_LSR_DR);
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276 | 80cabfad | bellard | } |
277 | 80cabfad | bellard | |
278 | 82c643ff | bellard | static void serial_receive_byte(SerialState *s, int ch) |
279 | 80cabfad | bellard | { |
280 | 80cabfad | bellard | s->rbr = ch; |
281 | 80cabfad | bellard | s->lsr |= UART_LSR_DR; |
282 | b41a2cd1 | bellard | serial_update_irq(s); |
283 | 80cabfad | bellard | } |
284 | 80cabfad | bellard | |
285 | 82c643ff | bellard | static void serial_receive_break(SerialState *s) |
286 | 80cabfad | bellard | { |
287 | 80cabfad | bellard | s->rbr = 0;
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288 | 80cabfad | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
289 | b41a2cd1 | bellard | serial_update_irq(s); |
290 | 80cabfad | bellard | } |
291 | 80cabfad | bellard | |
292 | b41a2cd1 | bellard | static int serial_can_receive1(void *opaque) |
293 | 80cabfad | bellard | { |
294 | b41a2cd1 | bellard | SerialState *s = opaque; |
295 | b41a2cd1 | bellard | return serial_can_receive(s);
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296 | b41a2cd1 | bellard | } |
297 | b41a2cd1 | bellard | |
298 | b41a2cd1 | bellard | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
299 | b41a2cd1 | bellard | { |
300 | b41a2cd1 | bellard | SerialState *s = opaque; |
301 | b41a2cd1 | bellard | serial_receive_byte(s, buf[0]);
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302 | b41a2cd1 | bellard | } |
303 | 80cabfad | bellard | |
304 | 82c643ff | bellard | static void serial_event(void *opaque, int event) |
305 | 82c643ff | bellard | { |
306 | 82c643ff | bellard | SerialState *s = opaque; |
307 | 82c643ff | bellard | if (event == CHR_EVENT_BREAK)
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308 | 82c643ff | bellard | serial_receive_break(s); |
309 | 82c643ff | bellard | } |
310 | 82c643ff | bellard | |
311 | 8738a8d0 | bellard | static void serial_save(QEMUFile *f, void *opaque) |
312 | 8738a8d0 | bellard | { |
313 | 8738a8d0 | bellard | SerialState *s = opaque; |
314 | 8738a8d0 | bellard | |
315 | 508d92d0 | bellard | qemu_put_be16s(f,&s->divider); |
316 | 8738a8d0 | bellard | qemu_put_8s(f,&s->rbr); |
317 | 8738a8d0 | bellard | qemu_put_8s(f,&s->ier); |
318 | 8738a8d0 | bellard | qemu_put_8s(f,&s->iir); |
319 | 8738a8d0 | bellard | qemu_put_8s(f,&s->lcr); |
320 | 8738a8d0 | bellard | qemu_put_8s(f,&s->mcr); |
321 | 8738a8d0 | bellard | qemu_put_8s(f,&s->lsr); |
322 | 8738a8d0 | bellard | qemu_put_8s(f,&s->msr); |
323 | 8738a8d0 | bellard | qemu_put_8s(f,&s->scr); |
324 | 8738a8d0 | bellard | } |
325 | 8738a8d0 | bellard | |
326 | 8738a8d0 | bellard | static int serial_load(QEMUFile *f, void *opaque, int version_id) |
327 | 8738a8d0 | bellard | { |
328 | 8738a8d0 | bellard | SerialState *s = opaque; |
329 | 8738a8d0 | bellard | |
330 | 508d92d0 | bellard | if(version_id > 2) |
331 | 8738a8d0 | bellard | return -EINVAL;
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332 | 8738a8d0 | bellard | |
333 | 508d92d0 | bellard | if (version_id >= 2) |
334 | 508d92d0 | bellard | qemu_get_be16s(f, &s->divider); |
335 | 508d92d0 | bellard | else
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336 | 508d92d0 | bellard | s->divider = qemu_get_byte(f); |
337 | 8738a8d0 | bellard | qemu_get_8s(f,&s->rbr); |
338 | 8738a8d0 | bellard | qemu_get_8s(f,&s->ier); |
339 | 8738a8d0 | bellard | qemu_get_8s(f,&s->iir); |
340 | 8738a8d0 | bellard | qemu_get_8s(f,&s->lcr); |
341 | 8738a8d0 | bellard | qemu_get_8s(f,&s->mcr); |
342 | 8738a8d0 | bellard | qemu_get_8s(f,&s->lsr); |
343 | 8738a8d0 | bellard | qemu_get_8s(f,&s->msr); |
344 | 8738a8d0 | bellard | qemu_get_8s(f,&s->scr); |
345 | 8738a8d0 | bellard | |
346 | 8738a8d0 | bellard | return 0; |
347 | 8738a8d0 | bellard | } |
348 | 8738a8d0 | bellard | |
349 | b41a2cd1 | bellard | /* If fd is zero, it means that the serial device uses the console */
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350 | d537cf6c | pbrook | SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
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351 | b41a2cd1 | bellard | { |
352 | b41a2cd1 | bellard | SerialState *s; |
353 | b41a2cd1 | bellard | |
354 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(SerialState));
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355 | b41a2cd1 | bellard | if (!s)
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356 | b41a2cd1 | bellard | return NULL; |
357 | 80cabfad | bellard | s->irq = irq; |
358 | 80cabfad | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
359 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
360 | 3e749fe1 | bellard | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
361 | b41a2cd1 | bellard | |
362 | 508d92d0 | bellard | register_savevm("serial", base, 2, serial_save, serial_load, s); |
363 | 8738a8d0 | bellard | |
364 | b41a2cd1 | bellard | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
365 | b41a2cd1 | bellard | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
366 | 82c643ff | bellard | s->chr = chr; |
367 | e5b0bc44 | pbrook | qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
368 | e5b0bc44 | pbrook | serial_event, s); |
369 | b41a2cd1 | bellard | return s;
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370 | 80cabfad | bellard | } |
371 | e5d13e2f | bellard | |
372 | e5d13e2f | bellard | /* Memory mapped interface */
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373 | a4bc3afc | ths | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
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374 | e5d13e2f | bellard | { |
375 | e5d13e2f | bellard | SerialState *s = opaque; |
376 | e5d13e2f | bellard | |
377 | e5d13e2f | bellard | return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
378 | e5d13e2f | bellard | } |
379 | e5d13e2f | bellard | |
380 | a4bc3afc | ths | void serial_mm_writeb (void *opaque, |
381 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
382 | e5d13e2f | bellard | { |
383 | e5d13e2f | bellard | SerialState *s = opaque; |
384 | e5d13e2f | bellard | |
385 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
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386 | e5d13e2f | bellard | } |
387 | e5d13e2f | bellard | |
388 | a4bc3afc | ths | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
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389 | e5d13e2f | bellard | { |
390 | e5d13e2f | bellard | SerialState *s = opaque; |
391 | e918ee04 | ths | uint32_t val; |
392 | e5d13e2f | bellard | |
393 | e918ee04 | ths | val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
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394 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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395 | e918ee04 | ths | val = bswap16(val); |
396 | e918ee04 | ths | #endif
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397 | e918ee04 | ths | return val;
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398 | e5d13e2f | bellard | } |
399 | e5d13e2f | bellard | |
400 | a4bc3afc | ths | void serial_mm_writew (void *opaque, |
401 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
402 | e5d13e2f | bellard | { |
403 | e5d13e2f | bellard | SerialState *s = opaque; |
404 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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405 | e918ee04 | ths | value = bswap16(value); |
406 | e918ee04 | ths | #endif
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407 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
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408 | e5d13e2f | bellard | } |
409 | e5d13e2f | bellard | |
410 | a4bc3afc | ths | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
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411 | e5d13e2f | bellard | { |
412 | e5d13e2f | bellard | SerialState *s = opaque; |
413 | e918ee04 | ths | uint32_t val; |
414 | e5d13e2f | bellard | |
415 | e918ee04 | ths | val = serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
416 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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417 | e918ee04 | ths | val = bswap32(val); |
418 | e918ee04 | ths | #endif
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419 | e918ee04 | ths | return val;
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420 | e5d13e2f | bellard | } |
421 | e5d13e2f | bellard | |
422 | a4bc3afc | ths | void serial_mm_writel (void *opaque, |
423 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
424 | e5d13e2f | bellard | { |
425 | e5d13e2f | bellard | SerialState *s = opaque; |
426 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
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427 | e918ee04 | ths | value = bswap32(value); |
428 | e918ee04 | ths | #endif
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429 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
430 | e5d13e2f | bellard | } |
431 | e5d13e2f | bellard | |
432 | e5d13e2f | bellard | static CPUReadMemoryFunc *serial_mm_read[] = {
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433 | e5d13e2f | bellard | &serial_mm_readb, |
434 | e5d13e2f | bellard | &serial_mm_readw, |
435 | e5d13e2f | bellard | &serial_mm_readl, |
436 | e5d13e2f | bellard | }; |
437 | e5d13e2f | bellard | |
438 | e5d13e2f | bellard | static CPUWriteMemoryFunc *serial_mm_write[] = {
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439 | e5d13e2f | bellard | &serial_mm_writeb, |
440 | e5d13e2f | bellard | &serial_mm_writew, |
441 | e5d13e2f | bellard | &serial_mm_writel, |
442 | e5d13e2f | bellard | }; |
443 | e5d13e2f | bellard | |
444 | 71db710f | blueswir1 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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445 | d537cf6c | pbrook | qemu_irq irq, CharDriverState *chr, |
446 | a4bc3afc | ths | int ioregister)
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447 | e5d13e2f | bellard | { |
448 | e5d13e2f | bellard | SerialState *s; |
449 | e5d13e2f | bellard | int s_io_memory;
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450 | e5d13e2f | bellard | |
451 | e5d13e2f | bellard | s = qemu_mallocz(sizeof(SerialState));
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452 | e5d13e2f | bellard | if (!s)
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453 | e5d13e2f | bellard | return NULL; |
454 | e5d13e2f | bellard | s->irq = irq; |
455 | e5d13e2f | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
456 | e5d13e2f | bellard | s->iir = UART_IIR_NO_INT; |
457 | 3e749fe1 | bellard | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
458 | e5d13e2f | bellard | s->base = base; |
459 | e5d13e2f | bellard | s->it_shift = it_shift; |
460 | e5d13e2f | bellard | |
461 | 508d92d0 | bellard | register_savevm("serial", base, 2, serial_save, serial_load, s); |
462 | e5d13e2f | bellard | |
463 | a4bc3afc | ths | if (ioregister) {
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464 | a4bc3afc | ths | s_io_memory = cpu_register_io_memory(0, serial_mm_read,
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465 | a4bc3afc | ths | serial_mm_write, s); |
466 | a4bc3afc | ths | cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
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467 | a4bc3afc | ths | } |
468 | e5d13e2f | bellard | s->chr = chr; |
469 | e5b0bc44 | pbrook | qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
470 | e5b0bc44 | pbrook | serial_event, s); |
471 | e5d13e2f | bellard | return s;
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472 | e5d13e2f | bellard | } |