Revision bdb78cae
| b/hw/escc.c | ||
|---|---|---|
| 113 | 113 |
int e0_mode, led_mode, caps_lock_mode, num_lock_mode; |
| 114 | 114 |
int disabled; |
| 115 | 115 |
int clock; |
| 116 |
uint32_t vmstate_dummy; |
|
| 116 | 117 |
} ChannelState; |
| 117 | 118 |
|
| 118 | 119 |
struct SerialState {
|
| ... | ... | |
| 326 | 327 |
clear_queue(s); |
| 327 | 328 |
} |
| 328 | 329 |
|
| 329 |
static void escc_reset(void *opaque)
|
|
| 330 |
static void escc_reset(DeviceState *d)
|
|
| 330 | 331 |
{
|
| 331 |
SerialState *s = opaque; |
|
| 332 |
SerialState *s = container_of(d, SerialState, busdev.qdev); |
|
| 333 |
|
|
| 332 | 334 |
escc_reset_chn(&s->chn[0]); |
| 333 | 335 |
escc_reset_chn(&s->chn[1]); |
| 334 | 336 |
} |
| ... | ... | |
| 547 | 549 |
escc_reset_chn(&serial->chn[1]); |
| 548 | 550 |
return; |
| 549 | 551 |
case MINTR_RST_ALL: |
| 550 |
escc_reset(serial);
|
|
| 552 |
escc_reset(&serial->busdev.qdev);
|
|
| 551 | 553 |
return; |
| 552 | 554 |
} |
| 553 | 555 |
break; |
| ... | ... | |
| 666 | 668 |
NULL, |
| 667 | 669 |
}; |
| 668 | 670 |
|
| 669 |
static void escc_save_chn(QEMUFile *f, ChannelState *s) |
|
| 670 |
{
|
|
| 671 |
uint32_t tmp = 0; |
|
| 672 |
|
|
| 673 |
qemu_put_be32s(f, &tmp); /* unused, was IRQ. */ |
|
| 674 |
qemu_put_be32s(f, &s->reg); |
|
| 675 |
qemu_put_be32s(f, &s->rxint); |
|
| 676 |
qemu_put_be32s(f, &s->txint); |
|
| 677 |
qemu_put_be32s(f, &s->rxint_under_svc); |
|
| 678 |
qemu_put_be32s(f, &s->txint_under_svc); |
|
| 679 |
qemu_put_8s(f, &s->rx); |
|
| 680 |
qemu_put_8s(f, &s->tx); |
|
| 681 |
qemu_put_buffer(f, s->wregs, SERIAL_REGS); |
|
| 682 |
qemu_put_buffer(f, s->rregs, SERIAL_REGS); |
|
| 683 |
} |
|
| 684 |
|
|
| 685 |
static void escc_save(QEMUFile *f, void *opaque) |
|
| 686 |
{
|
|
| 687 |
SerialState *s = opaque; |
|
| 688 |
|
|
| 689 |
escc_save_chn(f, &s->chn[0]); |
|
| 690 |
escc_save_chn(f, &s->chn[1]); |
|
| 691 |
} |
|
| 692 |
|
|
| 693 |
static int escc_load_chn(QEMUFile *f, ChannelState *s, int version_id) |
|
| 694 |
{
|
|
| 695 |
uint32_t tmp; |
|
| 696 |
|
|
| 697 |
if (version_id > 2) |
|
| 698 |
return -EINVAL; |
|
| 699 |
|
|
| 700 |
qemu_get_be32s(f, &tmp); /* unused */ |
|
| 701 |
qemu_get_be32s(f, &s->reg); |
|
| 702 |
qemu_get_be32s(f, &s->rxint); |
|
| 703 |
qemu_get_be32s(f, &s->txint); |
|
| 704 |
if (version_id >= 2) {
|
|
| 705 |
qemu_get_be32s(f, &s->rxint_under_svc); |
|
| 706 |
qemu_get_be32s(f, &s->txint_under_svc); |
|
| 671 |
static const VMStateDescription vmstate_escc_chn = {
|
|
| 672 |
.name ="escc_chn", |
|
| 673 |
.version_id = 2, |
|
| 674 |
.minimum_version_id = 1, |
|
| 675 |
.minimum_version_id_old = 1, |
|
| 676 |
.fields = (VMStateField []) {
|
|
| 677 |
VMSTATE_UINT32(vmstate_dummy, ChannelState), |
|
| 678 |
VMSTATE_UINT32(reg, ChannelState), |
|
| 679 |
VMSTATE_UINT32(rxint, ChannelState), |
|
| 680 |
VMSTATE_UINT32(txint, ChannelState), |
|
| 681 |
VMSTATE_UINT32(rxint_under_svc, ChannelState), |
|
| 682 |
VMSTATE_UINT32(txint_under_svc, ChannelState), |
|
| 683 |
VMSTATE_UINT8(rx, ChannelState), |
|
| 684 |
VMSTATE_UINT8(tx, ChannelState), |
|
| 685 |
VMSTATE_BUFFER(wregs, ChannelState), |
|
| 686 |
VMSTATE_BUFFER(rregs, ChannelState), |
|
| 687 |
VMSTATE_END_OF_LIST() |
|
| 707 | 688 |
} |
| 708 |
qemu_get_8s(f, &s->rx); |
|
| 709 |
qemu_get_8s(f, &s->tx); |
|
| 710 |
qemu_get_buffer(f, s->wregs, SERIAL_REGS); |
|
| 711 |
qemu_get_buffer(f, s->rregs, SERIAL_REGS); |
|
| 712 |
return 0; |
|
| 713 |
} |
|
| 714 |
|
|
| 715 |
static int escc_load(QEMUFile *f, void *opaque, int version_id) |
|
| 716 |
{
|
|
| 717 |
SerialState *s = opaque; |
|
| 718 |
int ret; |
|
| 719 |
|
|
| 720 |
ret = escc_load_chn(f, &s->chn[0], version_id); |
|
| 721 |
if (ret != 0) |
|
| 722 |
return ret; |
|
| 723 |
ret = escc_load_chn(f, &s->chn[1], version_id); |
|
| 724 |
return ret; |
|
| 689 |
}; |
|
| 725 | 690 |
|
| 726 |
} |
|
| 691 |
static const VMStateDescription vmstate_escc = {
|
|
| 692 |
.name ="escc", |
|
| 693 |
.version_id = 2, |
|
| 694 |
.minimum_version_id = 1, |
|
| 695 |
.minimum_version_id_old = 1, |
|
| 696 |
.fields = (VMStateField []) {
|
|
| 697 |
VMSTATE_STRUCT_ARRAY(chn, SerialState, 2, 2, vmstate_escc_chn, |
|
| 698 |
ChannelState), |
|
| 699 |
VMSTATE_END_OF_LIST() |
|
| 700 |
} |
|
| 701 |
}; |
|
| 727 | 702 |
|
| 728 | 703 |
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB, |
| 729 | 704 |
CharDriverState *chrA, CharDriverState *chrB, |
| ... | ... | |
| 942 | 917 |
if (s->chn[1].type == kbd) {
|
| 943 | 918 |
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]); |
| 944 | 919 |
} |
| 945 |
register_savevm("escc", -1, 2, escc_save, escc_load, s);
|
|
| 946 |
qemu_register_reset(escc_reset, s); |
|
| 947 |
escc_reset(s); |
|
| 920 |
escc_reset(&s->busdev.qdev); |
|
| 921 |
|
|
| 948 | 922 |
return 0; |
| 949 | 923 |
} |
| 950 | 924 |
|
| ... | ... | |
| 952 | 926 |
.init = escc_init1, |
| 953 | 927 |
.qdev.name = "escc", |
| 954 | 928 |
.qdev.size = sizeof(SerialState), |
| 929 |
.qdev.vmsd = &vmstate_escc, |
|
| 930 |
.qdev.reset = escc_reset, |
|
| 955 | 931 |
.qdev.props = (Property[]) {
|
| 956 | 932 |
DEFINE_PROP_UINT32("frequency", SerialState, frequency, 0),
|
| 957 | 933 |
DEFINE_PROP_UINT32("it_shift", SerialState, it_shift, 0),
|
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