root / hw / slavio_intctl.c @ bde7600c
History | View | Annotate | Download (10.9 kB)
1 | e80cfcfc | bellard | /*
|
---|---|---|---|
2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO interrupt controller emulation
|
3 | e80cfcfc | bellard | *
|
4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | e80cfcfc | bellard | *
|
6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
|
9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
|
12 | e80cfcfc | bellard | *
|
13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
|
15 | e80cfcfc | bellard | *
|
16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | e80cfcfc | bellard | * THE SOFTWARE.
|
23 | e80cfcfc | bellard | */
|
24 | e80cfcfc | bellard | #include "vl.h" |
25 | e80cfcfc | bellard | //#define DEBUG_IRQ_COUNT
|
26 | 66321a11 | bellard | //#define DEBUG_IRQ
|
27 | 66321a11 | bellard | |
28 | 66321a11 | bellard | #ifdef DEBUG_IRQ
|
29 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
|
30 | 66321a11 | bellard | do { printf("IRQ: " fmt , ##args); } while (0) |
31 | 66321a11 | bellard | #else
|
32 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
|
33 | 66321a11 | bellard | #endif
|
34 | e80cfcfc | bellard | |
35 | e80cfcfc | bellard | /*
|
36 | e80cfcfc | bellard | * Registers of interrupt controller in sun4m.
|
37 | e80cfcfc | bellard | *
|
38 | e80cfcfc | bellard | * This is the interrupt controller part of chip STP2001 (Slave I/O), also
|
39 | e80cfcfc | bellard | * produced as NCR89C105. See
|
40 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
41 | e80cfcfc | bellard | *
|
42 | e80cfcfc | bellard | * There is a system master controller and one for each cpu.
|
43 | e80cfcfc | bellard | *
|
44 | e80cfcfc | bellard | */
|
45 | e80cfcfc | bellard | |
46 | e80cfcfc | bellard | #define MAX_CPUS 16 |
47 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
48 | e80cfcfc | bellard | |
49 | e80cfcfc | bellard | typedef struct SLAVIO_INTCTLState { |
50 | e80cfcfc | bellard | uint32_t intreg_pending[MAX_CPUS]; |
51 | e80cfcfc | bellard | uint32_t intregm_pending; |
52 | e80cfcfc | bellard | uint32_t intregm_disabled; |
53 | e80cfcfc | bellard | uint32_t target_cpu; |
54 | e80cfcfc | bellard | #ifdef DEBUG_IRQ_COUNT
|
55 | e80cfcfc | bellard | uint64_t irq_count[32];
|
56 | e80cfcfc | bellard | #endif
|
57 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS]; |
58 | e0353fe2 | blueswir1 | const uint32_t *intbit_to_level;
|
59 | d7edfd27 | blueswir1 | uint32_t cputimer_bit; |
60 | b3a23197 | blueswir1 | uint32_t pil_out[MAX_CPUS]; |
61 | e80cfcfc | bellard | } SLAVIO_INTCTLState; |
62 | e80cfcfc | bellard | |
63 | e80cfcfc | bellard | #define INTCTL_MAXADDR 0xf |
64 | 5aca8c3b | blueswir1 | #define INTCTL_SIZE (INTCTL_MAXADDR + 1) |
65 | c6fdf5fc | blueswir1 | #define INTCTLM_MAXADDR 0x13 |
66 | 5aca8c3b | blueswir1 | #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1) |
67 | c6fdf5fc | blueswir1 | #define INTCTLM_MASK 0x1f |
68 | 66321a11 | bellard | static void slavio_check_interrupts(void *opaque); |
69 | e80cfcfc | bellard | |
70 | e80cfcfc | bellard | // per-cpu interrupt controller
|
71 | e80cfcfc | bellard | static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) |
72 | e80cfcfc | bellard | { |
73 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
74 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
75 | e80cfcfc | bellard | int cpu;
|
76 | e80cfcfc | bellard | |
77 | e80cfcfc | bellard | cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; |
78 | e80cfcfc | bellard | saddr = (addr & INTCTL_MAXADDR) >> 2;
|
79 | e80cfcfc | bellard | switch (saddr) {
|
80 | e80cfcfc | bellard | case 0: |
81 | dd4131b3 | blueswir1 | ret = s->intreg_pending[cpu]; |
82 | dd4131b3 | blueswir1 | break;
|
83 | e80cfcfc | bellard | default:
|
84 | dd4131b3 | blueswir1 | ret = 0;
|
85 | dd4131b3 | blueswir1 | break;
|
86 | e80cfcfc | bellard | } |
87 | 1569fc29 | blueswir1 | DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret); |
88 | dd4131b3 | blueswir1 | |
89 | dd4131b3 | blueswir1 | return ret;
|
90 | e80cfcfc | bellard | } |
91 | e80cfcfc | bellard | |
92 | e80cfcfc | bellard | static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
93 | e80cfcfc | bellard | { |
94 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
95 | e80cfcfc | bellard | uint32_t saddr; |
96 | e80cfcfc | bellard | int cpu;
|
97 | e80cfcfc | bellard | |
98 | e80cfcfc | bellard | cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12; |
99 | e80cfcfc | bellard | saddr = (addr & INTCTL_MAXADDR) >> 2;
|
100 | 1569fc29 | blueswir1 | DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val); |
101 | e80cfcfc | bellard | switch (saddr) {
|
102 | e80cfcfc | bellard | case 1: // clear pending softints |
103 | e80cfcfc | bellard | if (val & 0x4000) |
104 | e80cfcfc | bellard | val |= 80000000;
|
105 | e80cfcfc | bellard | val &= 0xfffe0000;
|
106 | e80cfcfc | bellard | s->intreg_pending[cpu] &= ~val; |
107 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
108 | 66321a11 | bellard | DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
109 | e80cfcfc | bellard | break;
|
110 | e80cfcfc | bellard | case 2: // set softint |
111 | e80cfcfc | bellard | val &= 0xfffe0000;
|
112 | e80cfcfc | bellard | s->intreg_pending[cpu] |= val; |
113 | ba3c64fb | bellard | slavio_check_interrupts(s); |
114 | 66321a11 | bellard | DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
|
115 | e80cfcfc | bellard | break;
|
116 | e80cfcfc | bellard | default:
|
117 | e80cfcfc | bellard | break;
|
118 | e80cfcfc | bellard | } |
119 | e80cfcfc | bellard | } |
120 | e80cfcfc | bellard | |
121 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = { |
122 | e80cfcfc | bellard | slavio_intctl_mem_readl, |
123 | e80cfcfc | bellard | slavio_intctl_mem_readl, |
124 | e80cfcfc | bellard | slavio_intctl_mem_readl, |
125 | e80cfcfc | bellard | }; |
126 | e80cfcfc | bellard | |
127 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = { |
128 | e80cfcfc | bellard | slavio_intctl_mem_writel, |
129 | e80cfcfc | bellard | slavio_intctl_mem_writel, |
130 | e80cfcfc | bellard | slavio_intctl_mem_writel, |
131 | e80cfcfc | bellard | }; |
132 | e80cfcfc | bellard | |
133 | e80cfcfc | bellard | // master system interrupt controller
|
134 | e80cfcfc | bellard | static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr) |
135 | e80cfcfc | bellard | { |
136 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
137 | dd4131b3 | blueswir1 | uint32_t saddr, ret; |
138 | e80cfcfc | bellard | |
139 | e80cfcfc | bellard | saddr = (addr & INTCTLM_MAXADDR) >> 2;
|
140 | e80cfcfc | bellard | switch (saddr) {
|
141 | e80cfcfc | bellard | case 0: |
142 | dd4131b3 | blueswir1 | ret = s->intregm_pending & 0x7fffffff;
|
143 | dd4131b3 | blueswir1 | break;
|
144 | e80cfcfc | bellard | case 1: |
145 | dd4131b3 | blueswir1 | ret = s->intregm_disabled; |
146 | dd4131b3 | blueswir1 | break;
|
147 | e80cfcfc | bellard | case 4: |
148 | dd4131b3 | blueswir1 | ret = s->target_cpu; |
149 | dd4131b3 | blueswir1 | break;
|
150 | e80cfcfc | bellard | default:
|
151 | dd4131b3 | blueswir1 | ret = 0;
|
152 | dd4131b3 | blueswir1 | break;
|
153 | e80cfcfc | bellard | } |
154 | 1569fc29 | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
155 | dd4131b3 | blueswir1 | |
156 | dd4131b3 | blueswir1 | return ret;
|
157 | e80cfcfc | bellard | } |
158 | e80cfcfc | bellard | |
159 | e80cfcfc | bellard | static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
160 | e80cfcfc | bellard | { |
161 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
162 | e80cfcfc | bellard | uint32_t saddr; |
163 | e80cfcfc | bellard | |
164 | c6fdf5fc | blueswir1 | saddr = (addr & INTCTLM_MASK) >> 2;
|
165 | 1569fc29 | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
166 | e80cfcfc | bellard | switch (saddr) {
|
167 | e80cfcfc | bellard | case 2: // clear (enable) |
168 | 6bae7071 | bellard | // Force clear unused bits
|
169 | 3475187d | bellard | val &= ~0x4fb2007f;
|
170 | e80cfcfc | bellard | s->intregm_disabled &= ~val; |
171 | 66321a11 | bellard | DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
172 | 66321a11 | bellard | slavio_check_interrupts(s); |
173 | e80cfcfc | bellard | break;
|
174 | e80cfcfc | bellard | case 3: // set (disable, clear pending) |
175 | 6bae7071 | bellard | // Force clear unused bits
|
176 | 3475187d | bellard | val &= ~0x4fb2007f;
|
177 | e80cfcfc | bellard | s->intregm_disabled |= val; |
178 | e80cfcfc | bellard | s->intregm_pending &= ~val; |
179 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
180 | 66321a11 | bellard | DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
|
181 | e80cfcfc | bellard | break;
|
182 | e80cfcfc | bellard | case 4: |
183 | e80cfcfc | bellard | s->target_cpu = val & (MAX_CPUS - 1);
|
184 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
185 | 66321a11 | bellard | DPRINTF("Set master irq cpu %d\n", s->target_cpu);
|
186 | e80cfcfc | bellard | break;
|
187 | e80cfcfc | bellard | default:
|
188 | e80cfcfc | bellard | break;
|
189 | e80cfcfc | bellard | } |
190 | e80cfcfc | bellard | } |
191 | e80cfcfc | bellard | |
192 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = { |
193 | e80cfcfc | bellard | slavio_intctlm_mem_readl, |
194 | e80cfcfc | bellard | slavio_intctlm_mem_readl, |
195 | e80cfcfc | bellard | slavio_intctlm_mem_readl, |
196 | e80cfcfc | bellard | }; |
197 | e80cfcfc | bellard | |
198 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = { |
199 | e80cfcfc | bellard | slavio_intctlm_mem_writel, |
200 | e80cfcfc | bellard | slavio_intctlm_mem_writel, |
201 | e80cfcfc | bellard | slavio_intctlm_mem_writel, |
202 | e80cfcfc | bellard | }; |
203 | e80cfcfc | bellard | |
204 | e80cfcfc | bellard | void slavio_pic_info(void *opaque) |
205 | e80cfcfc | bellard | { |
206 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
207 | e80cfcfc | bellard | int i;
|
208 | e80cfcfc | bellard | |
209 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
210 | e80cfcfc | bellard | term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
|
211 | e80cfcfc | bellard | } |
212 | e80cfcfc | bellard | term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
|
213 | e80cfcfc | bellard | } |
214 | e80cfcfc | bellard | |
215 | e80cfcfc | bellard | void slavio_irq_info(void *opaque) |
216 | e80cfcfc | bellard | { |
217 | e80cfcfc | bellard | #ifndef DEBUG_IRQ_COUNT
|
218 | e80cfcfc | bellard | term_printf("irq statistic code not compiled.\n");
|
219 | e80cfcfc | bellard | #else
|
220 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
221 | e80cfcfc | bellard | int i;
|
222 | e80cfcfc | bellard | int64_t count; |
223 | e80cfcfc | bellard | |
224 | e80cfcfc | bellard | term_printf("IRQ statistics:\n");
|
225 | e80cfcfc | bellard | for (i = 0; i < 32; i++) { |
226 | e80cfcfc | bellard | count = s->irq_count[i]; |
227 | e80cfcfc | bellard | if (count > 0) |
228 | 26a76461 | bellard | term_printf("%2d: %" PRId64 "\n", i, count); |
229 | e80cfcfc | bellard | } |
230 | e80cfcfc | bellard | #endif
|
231 | e80cfcfc | bellard | } |
232 | e80cfcfc | bellard | |
233 | 66321a11 | bellard | static void slavio_check_interrupts(void *opaque) |
234 | 66321a11 | bellard | { |
235 | 66321a11 | bellard | SLAVIO_INTCTLState *s = opaque; |
236 | 327ac2e7 | blueswir1 | uint32_t pending = s->intregm_pending, pil_pending; |
237 | 327ac2e7 | blueswir1 | unsigned int i, j; |
238 | 66321a11 | bellard | |
239 | 66321a11 | bellard | pending &= ~s->intregm_disabled; |
240 | 66321a11 | bellard | |
241 | b3a23197 | blueswir1 | DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
|
242 | ba3c64fb | bellard | for (i = 0; i < MAX_CPUS; i++) { |
243 | 327ac2e7 | blueswir1 | pil_pending = 0;
|
244 | b3a23197 | blueswir1 | if (pending && !(s->intregm_disabled & 0x80000000) && |
245 | b3a23197 | blueswir1 | (i == s->target_cpu)) { |
246 | b3a23197 | blueswir1 | for (j = 0; j < 32; j++) { |
247 | 327ac2e7 | blueswir1 | if (pending & (1 << j)) |
248 | 327ac2e7 | blueswir1 | pil_pending |= 1 << s->intbit_to_level[j];
|
249 | b3a23197 | blueswir1 | } |
250 | b3a23197 | blueswir1 | } |
251 | 327ac2e7 | blueswir1 | pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe; |
252 | 327ac2e7 | blueswir1 | |
253 | 327ac2e7 | blueswir1 | for (j = 0; j < MAX_PILS; j++) { |
254 | 327ac2e7 | blueswir1 | if (pil_pending & (1 << j)) { |
255 | 327ac2e7 | blueswir1 | if (!(s->pil_out[i] & (1 << j))) |
256 | 327ac2e7 | blueswir1 | qemu_irq_raise(s->cpu_irqs[i][j]); |
257 | 327ac2e7 | blueswir1 | } else {
|
258 | 327ac2e7 | blueswir1 | if (s->pil_out[i] & (1 << j)) |
259 | 327ac2e7 | blueswir1 | qemu_irq_lower(s->cpu_irqs[i][j]); |
260 | ba3c64fb | bellard | } |
261 | ba3c64fb | bellard | } |
262 | 327ac2e7 | blueswir1 | s->pil_out[i] = pil_pending; |
263 | ba3c64fb | bellard | } |
264 | 66321a11 | bellard | } |
265 | 66321a11 | bellard | |
266 | e80cfcfc | bellard | /*
|
267 | e80cfcfc | bellard | * "irq" here is the bit number in the system interrupt register to
|
268 | e80cfcfc | bellard | * separate serial and keyboard interrupts sharing a level.
|
269 | e80cfcfc | bellard | */
|
270 | d7edfd27 | blueswir1 | static void slavio_set_irq(void *opaque, int irq, int level) |
271 | e80cfcfc | bellard | { |
272 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
273 | b3a23197 | blueswir1 | uint32_t mask = 1 << irq;
|
274 | b3a23197 | blueswir1 | uint32_t pil = s->intbit_to_level[irq]; |
275 | b3a23197 | blueswir1 | |
276 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
|
277 | b3a23197 | blueswir1 | level); |
278 | b3a23197 | blueswir1 | if (pil > 0) { |
279 | b3a23197 | blueswir1 | if (level) {
|
280 | 327ac2e7 | blueswir1 | #ifdef DEBUG_IRQ_COUNT
|
281 | 327ac2e7 | blueswir1 | s->irq_count[pil]++; |
282 | 327ac2e7 | blueswir1 | #endif
|
283 | b3a23197 | blueswir1 | s->intregm_pending |= mask; |
284 | b3a23197 | blueswir1 | s->intreg_pending[s->target_cpu] |= 1 << pil;
|
285 | b3a23197 | blueswir1 | } else {
|
286 | b3a23197 | blueswir1 | s->intregm_pending &= ~mask; |
287 | b3a23197 | blueswir1 | s->intreg_pending[s->target_cpu] &= ~(1 << pil);
|
288 | b3a23197 | blueswir1 | } |
289 | b3a23197 | blueswir1 | slavio_check_interrupts(s); |
290 | e80cfcfc | bellard | } |
291 | e80cfcfc | bellard | } |
292 | e80cfcfc | bellard | |
293 | d7edfd27 | blueswir1 | static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) |
294 | ba3c64fb | bellard | { |
295 | ba3c64fb | bellard | SLAVIO_INTCTLState *s = opaque; |
296 | ba3c64fb | bellard | |
297 | b3a23197 | blueswir1 | DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
|
298 | d7edfd27 | blueswir1 | |
299 | b3a23197 | blueswir1 | if (level)
|
300 | d7edfd27 | blueswir1 | s->intreg_pending[cpu] |= s->cputimer_bit; |
301 | b3a23197 | blueswir1 | else
|
302 | d7edfd27 | blueswir1 | s->intreg_pending[cpu] &= ~s->cputimer_bit; |
303 | d7edfd27 | blueswir1 | |
304 | ba3c64fb | bellard | slavio_check_interrupts(s); |
305 | ba3c64fb | bellard | } |
306 | ba3c64fb | bellard | |
307 | e80cfcfc | bellard | static void slavio_intctl_save(QEMUFile *f, void *opaque) |
308 | e80cfcfc | bellard | { |
309 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
310 | e80cfcfc | bellard | int i;
|
311 | e80cfcfc | bellard | |
312 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
313 | e80cfcfc | bellard | qemu_put_be32s(f, &s->intreg_pending[i]); |
314 | e80cfcfc | bellard | } |
315 | e80cfcfc | bellard | qemu_put_be32s(f, &s->intregm_pending); |
316 | e80cfcfc | bellard | qemu_put_be32s(f, &s->intregm_disabled); |
317 | e80cfcfc | bellard | qemu_put_be32s(f, &s->target_cpu); |
318 | e80cfcfc | bellard | } |
319 | e80cfcfc | bellard | |
320 | e80cfcfc | bellard | static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id) |
321 | e80cfcfc | bellard | { |
322 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
323 | e80cfcfc | bellard | int i;
|
324 | e80cfcfc | bellard | |
325 | e80cfcfc | bellard | if (version_id != 1) |
326 | e80cfcfc | bellard | return -EINVAL;
|
327 | e80cfcfc | bellard | |
328 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
329 | e80cfcfc | bellard | qemu_get_be32s(f, &s->intreg_pending[i]); |
330 | e80cfcfc | bellard | } |
331 | e80cfcfc | bellard | qemu_get_be32s(f, &s->intregm_pending); |
332 | e80cfcfc | bellard | qemu_get_be32s(f, &s->intregm_disabled); |
333 | e80cfcfc | bellard | qemu_get_be32s(f, &s->target_cpu); |
334 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
335 | e80cfcfc | bellard | return 0; |
336 | e80cfcfc | bellard | } |
337 | e80cfcfc | bellard | |
338 | e80cfcfc | bellard | static void slavio_intctl_reset(void *opaque) |
339 | e80cfcfc | bellard | { |
340 | e80cfcfc | bellard | SLAVIO_INTCTLState *s = opaque; |
341 | e80cfcfc | bellard | int i;
|
342 | e80cfcfc | bellard | |
343 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
344 | e80cfcfc | bellard | s->intreg_pending[i] = 0;
|
345 | e80cfcfc | bellard | } |
346 | 6bae7071 | bellard | s->intregm_disabled = ~0xffb2007f;
|
347 | e80cfcfc | bellard | s->intregm_pending = 0;
|
348 | e80cfcfc | bellard | s->target_cpu = 0;
|
349 | 327ac2e7 | blueswir1 | slavio_check_interrupts(s); |
350 | e80cfcfc | bellard | } |
351 | e80cfcfc | bellard | |
352 | 5dcb6b91 | blueswir1 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
353 | d537cf6c | pbrook | const uint32_t *intbit_to_level,
|
354 | d7edfd27 | blueswir1 | qemu_irq **irq, qemu_irq **cpu_irq, |
355 | b3a23197 | blueswir1 | qemu_irq **parent_irq, unsigned int cputimer) |
356 | e80cfcfc | bellard | { |
357 | e80cfcfc | bellard | int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
|
358 | e80cfcfc | bellard | SLAVIO_INTCTLState *s; |
359 | e80cfcfc | bellard | |
360 | e80cfcfc | bellard | s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
|
361 | e80cfcfc | bellard | if (!s)
|
362 | e80cfcfc | bellard | return NULL; |
363 | e80cfcfc | bellard | |
364 | e0353fe2 | blueswir1 | s->intbit_to_level = intbit_to_level; |
365 | e80cfcfc | bellard | for (i = 0; i < MAX_CPUS; i++) { |
366 | e80cfcfc | bellard | slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
|
367 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE, |
368 | 5aca8c3b | blueswir1 | slavio_intctl_io_memory); |
369 | b3a23197 | blueswir1 | s->cpu_irqs[i] = parent_irq[i]; |
370 | e80cfcfc | bellard | } |
371 | e80cfcfc | bellard | |
372 | e80cfcfc | bellard | slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
|
373 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory); |
374 | e80cfcfc | bellard | |
375 | e80cfcfc | bellard | register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s); |
376 | e80cfcfc | bellard | qemu_register_reset(slavio_intctl_reset, s); |
377 | d537cf6c | pbrook | *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
|
378 | d7edfd27 | blueswir1 | |
379 | d7edfd27 | blueswir1 | *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS); |
380 | d7edfd27 | blueswir1 | s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
|
381 | e80cfcfc | bellard | slavio_intctl_reset(s); |
382 | e80cfcfc | bellard | return s;
|
383 | e80cfcfc | bellard | } |