Statistics
| Branch: | Revision:

root / hw / ide.c @ bde7600c

History | View | Annotate | Download (111.1 kB)

1
/*
2
 * QEMU IDE disk and CD-ROM Emulator
3
 * 
4
 * Copyright (c) 2003 Fabrice Bellard
5
 * Copyright (c) 2006 Openedhand Ltd.
6
 * 
7
 * Permission is hereby granted, free of charge, to any person obtaining a copy
8
 * of this software and associated documentation files (the "Software"), to deal
9
 * in the Software without restriction, including without limitation the rights
10
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11
 * copies of the Software, and to permit persons to whom the Software is
12
 * furnished to do so, subject to the following conditions:
13
 *
14
 * The above copyright notice and this permission notice shall be included in
15
 * all copies or substantial portions of the Software.
16
 *
17
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23
 * THE SOFTWARE.
24
 */
25
#include "vl.h"
26

    
27
/* debug IDE devices */
28
//#define DEBUG_IDE
29
//#define DEBUG_IDE_ATAPI
30
//#define DEBUG_AIO
31
#define USE_DMA_CDROM
32

    
33
/* Bits of HD_STATUS */
34
#define ERR_STAT                0x01
35
#define INDEX_STAT                0x02
36
#define ECC_STAT                0x04        /* Corrected error */
37
#define DRQ_STAT                0x08
38
#define SEEK_STAT                0x10
39
#define SRV_STAT                0x10
40
#define WRERR_STAT                0x20
41
#define READY_STAT                0x40
42
#define BUSY_STAT                0x80
43

    
44
/* Bits for HD_ERROR */
45
#define MARK_ERR                0x01        /* Bad address mark */
46
#define TRK0_ERR                0x02        /* couldn't find track 0 */
47
#define ABRT_ERR                0x04        /* Command aborted */
48
#define MCR_ERR                        0x08        /* media change request */
49
#define ID_ERR                        0x10        /* ID field not found */
50
#define MC_ERR                        0x20        /* media changed */
51
#define ECC_ERR                        0x40        /* Uncorrectable ECC error */
52
#define BBD_ERR                        0x80        /* pre-EIDE meaning:  block marked bad */
53
#define ICRC_ERR                0x80        /* new meaning:  CRC error during transfer */
54

    
55
/* Bits of HD_NSECTOR */
56
#define CD                        0x01
57
#define IO                        0x02
58
#define REL                        0x04
59
#define TAG_MASK                0xf8
60

    
61
#define IDE_CMD_RESET           0x04
62
#define IDE_CMD_DISABLE_IRQ     0x02
63

    
64
/* ATA/ATAPI Commands pre T13 Spec */
65
#define WIN_NOP                                0x00
66
/*
67
 *        0x01->0x02 Reserved
68
 */
69
#define CFA_REQ_EXT_ERROR_CODE                0x03 /* CFA Request Extended Error Code */
70
/*
71
 *        0x04->0x07 Reserved
72
 */
73
#define WIN_SRST                        0x08 /* ATAPI soft reset command */
74
#define WIN_DEVICE_RESET                0x08
75
/*
76
 *        0x09->0x0F Reserved
77
 */
78
#define WIN_RECAL                        0x10
79
#define WIN_RESTORE                        WIN_RECAL
80
/*
81
 *        0x10->0x1F Reserved
82
 */
83
#define WIN_READ                        0x20 /* 28-Bit */
84
#define WIN_READ_ONCE                        0x21 /* 28-Bit without retries */
85
#define WIN_READ_LONG                        0x22 /* 28-Bit */
86
#define WIN_READ_LONG_ONCE                0x23 /* 28-Bit without retries */
87
#define WIN_READ_EXT                        0x24 /* 48-Bit */
88
#define WIN_READDMA_EXT                        0x25 /* 48-Bit */
89
#define WIN_READDMA_QUEUED_EXT                0x26 /* 48-Bit */
90
#define WIN_READ_NATIVE_MAX_EXT                0x27 /* 48-Bit */
91
/*
92
 *        0x28
93
 */
94
#define WIN_MULTREAD_EXT                0x29 /* 48-Bit */
95
/*
96
 *        0x2A->0x2F Reserved
97
 */
98
#define WIN_WRITE                        0x30 /* 28-Bit */
99
#define WIN_WRITE_ONCE                        0x31 /* 28-Bit without retries */
100
#define WIN_WRITE_LONG                        0x32 /* 28-Bit */
101
#define WIN_WRITE_LONG_ONCE                0x33 /* 28-Bit without retries */
102
#define WIN_WRITE_EXT                        0x34 /* 48-Bit */
103
#define WIN_WRITEDMA_EXT                0x35 /* 48-Bit */
104
#define WIN_WRITEDMA_QUEUED_EXT                0x36 /* 48-Bit */
105
#define WIN_SET_MAX_EXT                        0x37 /* 48-Bit */
106
#define CFA_WRITE_SECT_WO_ERASE                0x38 /* CFA Write Sectors without erase */
107
#define WIN_MULTWRITE_EXT                0x39 /* 48-Bit */
108
/*
109
 *        0x3A->0x3B Reserved
110
 */
111
#define WIN_WRITE_VERIFY                0x3C /* 28-Bit */
112
/*
113
 *        0x3D->0x3F Reserved
114
 */
115
#define WIN_VERIFY                        0x40 /* 28-Bit - Read Verify Sectors */
116
#define WIN_VERIFY_ONCE                        0x41 /* 28-Bit - without retries */
117
#define WIN_VERIFY_EXT                        0x42 /* 48-Bit */
118
/*
119
 *        0x43->0x4F Reserved
120
 */
121
#define WIN_FORMAT                        0x50
122
/*
123
 *        0x51->0x5F Reserved
124
 */
125
#define WIN_INIT                        0x60
126
/*
127
 *        0x61->0x5F Reserved
128
 */
129
#define WIN_SEEK                        0x70 /* 0x70-0x7F Reserved */
130
#define CFA_TRANSLATE_SECTOR                0x87 /* CFA Translate Sector */
131
#define WIN_DIAGNOSE                        0x90
132
#define WIN_SPECIFY                        0x91 /* set drive geometry translation */
133
#define WIN_DOWNLOAD_MICROCODE                0x92
134
#define WIN_STANDBYNOW2                        0x94
135
#define CFA_IDLEIMMEDIATE                0x95 /* force drive to become "ready" */
136
#define WIN_STANDBY2                        0x96
137
#define WIN_SETIDLE2                        0x97
138
#define WIN_CHECKPOWERMODE2                0x98
139
#define WIN_SLEEPNOW2                        0x99
140
/*
141
 *        0x9A VENDOR
142
 */
143
#define WIN_PACKETCMD                        0xA0 /* Send a packet command. */
144
#define WIN_PIDENTIFY                        0xA1 /* identify ATAPI device        */
145
#define WIN_QUEUED_SERVICE                0xA2
146
#define WIN_SMART                        0xB0 /* self-monitoring and reporting */
147
#define CFA_ACCESS_METADATA_STORAGE        0xB8
148
#define CFA_ERASE_SECTORS               0xC0 /* microdrives implement as NOP */
149
#define WIN_MULTREAD                        0xC4 /* read sectors using multiple mode*/
150
#define WIN_MULTWRITE                        0xC5 /* write sectors using multiple mode */
151
#define WIN_SETMULT                        0xC6 /* enable/disable multiple mode */
152
#define WIN_READDMA_QUEUED                0xC7 /* read sectors using Queued DMA transfers */
153
#define WIN_READDMA                        0xC8 /* read sectors using DMA transfers */
154
#define WIN_READDMA_ONCE                0xC9 /* 28-Bit - without retries */
155
#define WIN_WRITEDMA                        0xCA /* write sectors using DMA transfers */
156
#define WIN_WRITEDMA_ONCE                0xCB /* 28-Bit - without retries */
157
#define WIN_WRITEDMA_QUEUED                0xCC /* write sectors using Queued DMA transfers */
158
#define CFA_WRITE_MULTI_WO_ERASE        0xCD /* CFA Write multiple without erase */
159
#define WIN_GETMEDIASTATUS                0xDA        
160
#define WIN_ACKMEDIACHANGE                0xDB /* ATA-1, ATA-2 vendor */
161
#define WIN_POSTBOOT                        0xDC
162
#define WIN_PREBOOT                        0xDD
163
#define WIN_DOORLOCK                        0xDE /* lock door on removable drives */
164
#define WIN_DOORUNLOCK                        0xDF /* unlock door on removable drives */
165
#define WIN_STANDBYNOW1                        0xE0
166
#define WIN_IDLEIMMEDIATE                0xE1 /* force drive to become "ready" */
167
#define WIN_STANDBY                     0xE2 /* Set device in Standby Mode */
168
#define WIN_SETIDLE1                        0xE3
169
#define WIN_READ_BUFFER                        0xE4 /* force read only 1 sector */
170
#define WIN_CHECKPOWERMODE1                0xE5
171
#define WIN_SLEEPNOW1                        0xE6
172
#define WIN_FLUSH_CACHE                        0xE7
173
#define WIN_WRITE_BUFFER                0xE8 /* force write only 1 sector */
174
#define WIN_WRITE_SAME                        0xE9 /* read ata-2 to use */
175
        /* SET_FEATURES 0x22 or 0xDD */
176
#define WIN_FLUSH_CACHE_EXT                0xEA /* 48-Bit */
177
#define WIN_IDENTIFY                        0xEC /* ask drive to identify itself        */
178
#define WIN_MEDIAEJECT                        0xED
179
#define WIN_IDENTIFY_DMA                0xEE /* same as WIN_IDENTIFY, but DMA */
180
#define WIN_SETFEATURES                        0xEF /* set special drive features */
181
#define EXABYTE_ENABLE_NEST                0xF0
182
#define IBM_SENSE_CONDITION                0xF0 /* measure disk temperature */
183
#define WIN_SECURITY_SET_PASS                0xF1
184
#define WIN_SECURITY_UNLOCK                0xF2
185
#define WIN_SECURITY_ERASE_PREPARE        0xF3
186
#define WIN_SECURITY_ERASE_UNIT                0xF4
187
#define WIN_SECURITY_FREEZE_LOCK        0xF5
188
#define CFA_WEAR_LEVEL                        0xF5 /* microdrives implement as NOP */
189
#define WIN_SECURITY_DISABLE                0xF6
190
#define WIN_READ_NATIVE_MAX                0xF8 /* return the native maximum address */
191
#define WIN_SET_MAX                        0xF9
192
#define DISABLE_SEAGATE                        0xFB
193

    
194
/* set to 1 set disable mult support */
195
#define MAX_MULT_SECTORS 16
196

    
197
/* ATAPI defines */
198

    
199
#define ATAPI_PACKET_SIZE 12
200

    
201
/* The generic packet command opcodes for CD/DVD Logical Units,
202
 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
203
#define GPCMD_BLANK                            0xa1
204
#define GPCMD_CLOSE_TRACK                    0x5b
205
#define GPCMD_FLUSH_CACHE                    0x35
206
#define GPCMD_FORMAT_UNIT                    0x04
207
#define GPCMD_GET_CONFIGURATION                    0x46
208
#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
209
#define GPCMD_GET_PERFORMANCE                    0xac
210
#define GPCMD_INQUIRY                            0x12
211
#define GPCMD_LOAD_UNLOAD                    0xa6
212
#define GPCMD_MECHANISM_STATUS                    0xbd
213
#define GPCMD_MODE_SELECT_10                    0x55
214
#define GPCMD_MODE_SENSE_10                    0x5a
215
#define GPCMD_PAUSE_RESUME                    0x4b
216
#define GPCMD_PLAY_AUDIO_10                    0x45
217
#define GPCMD_PLAY_AUDIO_MSF                    0x47
218
#define GPCMD_PLAY_AUDIO_TI                    0x48
219
#define GPCMD_PLAY_CD                            0xbc
220
#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL  0x1e
221
#define GPCMD_READ_10                            0x28
222
#define GPCMD_READ_12                            0xa8
223
#define GPCMD_READ_CDVD_CAPACITY            0x25
224
#define GPCMD_READ_CD                            0xbe
225
#define GPCMD_READ_CD_MSF                    0xb9
226
#define GPCMD_READ_DISC_INFO                    0x51
227
#define GPCMD_READ_DVD_STRUCTURE            0xad
228
#define GPCMD_READ_FORMAT_CAPACITIES            0x23
229
#define GPCMD_READ_HEADER                    0x44
230
#define GPCMD_READ_TRACK_RZONE_INFO            0x52
231
#define GPCMD_READ_SUBCHANNEL                    0x42
232
#define GPCMD_READ_TOC_PMA_ATIP                    0x43
233
#define GPCMD_REPAIR_RZONE_TRACK            0x58
234
#define GPCMD_REPORT_KEY                    0xa4
235
#define GPCMD_REQUEST_SENSE                    0x03
236
#define GPCMD_RESERVE_RZONE_TRACK            0x53
237
#define GPCMD_SCAN                            0xba
238
#define GPCMD_SEEK                            0x2b
239
#define GPCMD_SEND_DVD_STRUCTURE            0xad
240
#define GPCMD_SEND_EVENT                    0xa2
241
#define GPCMD_SEND_KEY                            0xa3
242
#define GPCMD_SEND_OPC                            0x54
243
#define GPCMD_SET_READ_AHEAD                    0xa7
244
#define GPCMD_SET_STREAMING                    0xb6
245
#define GPCMD_START_STOP_UNIT                    0x1b
246
#define GPCMD_STOP_PLAY_SCAN                    0x4e
247
#define GPCMD_TEST_UNIT_READY                    0x00
248
#define GPCMD_VERIFY_10                            0x2f
249
#define GPCMD_WRITE_10                            0x2a
250
#define GPCMD_WRITE_AND_VERIFY_10            0x2e
251
/* This is listed as optional in ATAPI 2.6, but is (curiously) 
252
 * missing from Mt. Fuji, Table 57.  It _is_ mentioned in Mt. Fuji
253
 * Table 377 as an MMC command for SCSi devices though...  Most ATAPI
254
 * drives support it. */
255
#define GPCMD_SET_SPEED                            0xbb
256
/* This seems to be a SCSI specific CD-ROM opcode 
257
 * to play data at track/index */
258
#define GPCMD_PLAYAUDIO_TI                    0x48
259
/*
260
 * From MS Media Status Notification Support Specification. For
261
 * older drives only.
262
 */
263
#define GPCMD_GET_MEDIA_STATUS                    0xda
264
#define GPCMD_MODE_SENSE_6                    0x1a
265

    
266
/* Mode page codes for mode sense/set */
267
#define GPMODE_R_W_ERROR_PAGE                0x01
268
#define GPMODE_WRITE_PARMS_PAGE                0x05
269
#define GPMODE_AUDIO_CTL_PAGE                0x0e
270
#define GPMODE_POWER_PAGE                0x1a
271
#define GPMODE_FAULT_FAIL_PAGE                0x1c
272
#define GPMODE_TO_PROTECT_PAGE                0x1d
273
#define GPMODE_CAPABILITIES_PAGE        0x2a
274
#define GPMODE_ALL_PAGES                0x3f
275
/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
276
 * of MODE_SENSE_POWER_PAGE */
277
#define GPMODE_CDROM_PAGE                0x0d
278

    
279
#define ATAPI_INT_REASON_CD             0x01 /* 0 = data transfer */
280
#define ATAPI_INT_REASON_IO             0x02 /* 1 = transfer to the host */
281
#define ATAPI_INT_REASON_REL            0x04
282
#define ATAPI_INT_REASON_TAG            0xf8
283

    
284
/* same constants as bochs */
285
#define ASC_ILLEGAL_OPCODE                   0x20
286
#define ASC_LOGICAL_BLOCK_OOR                0x21
287
#define ASC_INV_FIELD_IN_CMD_PACKET          0x24
288
#define ASC_MEDIUM_NOT_PRESENT               0x3a
289
#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED  0x39
290

    
291
#define CFA_NO_ERROR            0x00
292
#define CFA_MISC_ERROR          0x09
293
#define CFA_INVALID_COMMAND     0x20
294
#define CFA_INVALID_ADDRESS     0x21
295
#define CFA_ADDRESS_OVERFLOW    0x2f
296

    
297
#define SENSE_NONE            0
298
#define SENSE_NOT_READY       2
299
#define SENSE_ILLEGAL_REQUEST 5
300
#define SENSE_UNIT_ATTENTION  6
301

    
302
struct IDEState;
303

    
304
typedef void EndTransferFunc(struct IDEState *);
305

    
306
/* NOTE: IDEState represents in fact one drive */
307
typedef struct IDEState {
308
    /* ide config */
309
    int is_cdrom;
310
    int is_cf;
311
    int cylinders, heads, sectors;
312
    int64_t nb_sectors;
313
    int mult_sectors;
314
    int identify_set;
315
    uint16_t identify_data[256];
316
    qemu_irq irq;
317
    PCIDevice *pci_dev;
318
    struct BMDMAState *bmdma;
319
    int drive_serial;
320
    /* ide regs */
321
    uint8_t feature;
322
    uint8_t error;
323
    uint32_t nsector;
324
    uint8_t sector;
325
    uint8_t lcyl;
326
    uint8_t hcyl;
327
    /* other part of tf for lba48 support */
328
    uint8_t hob_feature;
329
    uint8_t hob_nsector;
330
    uint8_t hob_sector;
331
    uint8_t hob_lcyl;
332
    uint8_t hob_hcyl;
333

    
334
    uint8_t select;
335
    uint8_t status;
336

    
337
    /* 0x3f6 command, only meaningful for drive 0 */
338
    uint8_t cmd;
339
    /* set for lba48 access */
340
    uint8_t lba48;
341
    /* depends on bit 4 in select, only meaningful for drive 0 */
342
    struct IDEState *cur_drive; 
343
    BlockDriverState *bs;
344
    /* ATAPI specific */
345
    uint8_t sense_key;
346
    uint8_t asc;
347
    int packet_transfer_size;
348
    int elementary_transfer_size;
349
    int io_buffer_index;
350
    int lba;
351
    int cd_sector_size;
352
    int atapi_dma; /* true if dma is requested for the packet cmd */
353
    /* ATA DMA state */
354
    int io_buffer_size;
355
    /* PIO transfer handling */
356
    int req_nb_sectors; /* number of sectors per interrupt */
357
    EndTransferFunc *end_transfer_func;
358
    uint8_t *data_ptr;
359
    uint8_t *data_end;
360
    uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
361
    QEMUTimer *sector_write_timer; /* only used for win2k instal hack */
362
    uint32_t irq_count; /* counts IRQs when using win2k install hack */
363
    /* CF-ATA extended error */
364
    uint8_t ext_error;
365
    /* CF-ATA metadata storage */
366
    uint32_t mdata_size;
367
    uint8_t *mdata_storage;
368
    int media_changed;
369
} IDEState;
370

    
371
#define BM_STATUS_DMAING 0x01
372
#define BM_STATUS_ERROR  0x02
373
#define BM_STATUS_INT    0x04
374

    
375
#define BM_CMD_START     0x01
376
#define BM_CMD_READ      0x08
377

    
378
#define IDE_TYPE_PIIX3   0
379
#define IDE_TYPE_CMD646  1
380
#define IDE_TYPE_PIIX4   2
381

    
382
/* CMD646 specific */
383
#define MRDMODE                0x71
384
#define   MRDMODE_INTR_CH0        0x04
385
#define   MRDMODE_INTR_CH1        0x08
386
#define   MRDMODE_BLK_CH0        0x10
387
#define   MRDMODE_BLK_CH1        0x20
388
#define UDIDETCR0        0x73
389
#define UDIDETCR1        0x7B
390

    
391
typedef struct BMDMAState {
392
    uint8_t cmd;
393
    uint8_t status;
394
    uint32_t addr;
395
    
396
    struct PCIIDEState *pci_dev;
397
    /* current transfer state */
398
    uint32_t cur_addr;
399
    uint32_t cur_prd_last;
400
    uint32_t cur_prd_addr;
401
    uint32_t cur_prd_len;
402
    IDEState *ide_if;
403
    BlockDriverCompletionFunc *dma_cb;
404
    BlockDriverAIOCB *aiocb;
405
} BMDMAState;
406

    
407
typedef struct PCIIDEState {
408
    PCIDevice dev;
409
    IDEState ide_if[4];
410
    BMDMAState bmdma[2];
411
    int type; /* see IDE_TYPE_xxx */
412
} PCIIDEState;
413

    
414
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
415
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
416

    
417
static void padstr(char *str, const char *src, int len)
418
{
419
    int i, v;
420
    for(i = 0; i < len; i++) {
421
        if (*src)
422
            v = *src++;
423
        else
424
            v = ' ';
425
        *(char *)((long)str ^ 1) = v;
426
        str++;
427
    }
428
}
429

    
430
static void padstr8(uint8_t *buf, int buf_size, const char *src)
431
{
432
    int i;
433
    for(i = 0; i < buf_size; i++) {
434
        if (*src)
435
            buf[i] = *src++;
436
        else
437
            buf[i] = ' ';
438
    }
439
}
440

    
441
static void put_le16(uint16_t *p, unsigned int v)
442
{
443
    *p = cpu_to_le16(v);
444
}
445

    
446
static void ide_identify(IDEState *s)
447
{
448
    uint16_t *p;
449
    unsigned int oldsize;
450
    char buf[20];
451

    
452
    if (s->identify_set) {
453
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
454
        return;
455
    }
456

    
457
    memset(s->io_buffer, 0, 512);
458
    p = (uint16_t *)s->io_buffer;
459
    put_le16(p + 0, 0x0040);
460
    put_le16(p + 1, s->cylinders); 
461
    put_le16(p + 3, s->heads);
462
    put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
463
    put_le16(p + 5, 512); /* XXX: retired, remove ? */
464
    put_le16(p + 6, s->sectors); 
465
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
466
    padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
467
    put_le16(p + 20, 3); /* XXX: retired, remove ? */
468
    put_le16(p + 21, 512); /* cache size in sectors */
469
    put_le16(p + 22, 4); /* ecc bytes */
470
    padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
471
    padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
472
#if MAX_MULT_SECTORS > 1    
473
    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
474
#endif
475
    put_le16(p + 48, 1); /* dword I/O */
476
    put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
477
    put_le16(p + 51, 0x200); /* PIO transfer cycle */
478
    put_le16(p + 52, 0x200); /* DMA transfer cycle */
479
    put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
480
    put_le16(p + 54, s->cylinders);
481
    put_le16(p + 55, s->heads);
482
    put_le16(p + 56, s->sectors);
483
    oldsize = s->cylinders * s->heads * s->sectors;
484
    put_le16(p + 57, oldsize);
485
    put_le16(p + 58, oldsize >> 16);
486
    if (s->mult_sectors)
487
        put_le16(p + 59, 0x100 | s->mult_sectors);
488
    put_le16(p + 60, s->nb_sectors);
489
    put_le16(p + 61, s->nb_sectors >> 16);
490
    put_le16(p + 63, 0x07); /* mdma0-2 supported */
491
    put_le16(p + 65, 120);
492
    put_le16(p + 66, 120);
493
    put_le16(p + 67, 120);
494
    put_le16(p + 68, 120);
495
    put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
496
    put_le16(p + 81, 0x16); /* conforms to ata5 */
497
    put_le16(p + 82, (1 << 14));
498
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
499
    put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
500
    put_le16(p + 84, (1 << 14));
501
    put_le16(p + 85, (1 << 14));
502
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
503
    put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
504
    put_le16(p + 87, (1 << 14));
505
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
506
    put_le16(p + 93, 1 | (1 << 14) | 0x2000);
507
    put_le16(p + 100, s->nb_sectors);
508
    put_le16(p + 101, s->nb_sectors >> 16);
509
    put_le16(p + 102, s->nb_sectors >> 32);
510
    put_le16(p + 103, s->nb_sectors >> 48);
511

    
512
    memcpy(s->identify_data, p, sizeof(s->identify_data));
513
    s->identify_set = 1;
514
}
515

    
516
static void ide_atapi_identify(IDEState *s)
517
{
518
    uint16_t *p;
519
    char buf[20];
520

    
521
    if (s->identify_set) {
522
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
523
        return;
524
    }
525

    
526
    memset(s->io_buffer, 0, 512);
527
    p = (uint16_t *)s->io_buffer;
528
    /* Removable CDROM, 50us response, 12 byte packets */
529
    put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
530
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
531
    padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
532
    put_le16(p + 20, 3); /* buffer type */
533
    put_le16(p + 21, 512); /* cache size in sectors */
534
    put_le16(p + 22, 4); /* ecc bytes */
535
    padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
536
    padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
537
    put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
538
#ifdef USE_DMA_CDROM
539
    put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
540
    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
541
    put_le16(p + 63, 7);  /* mdma0-2 supported */
542
    put_le16(p + 64, 0x3f); /* PIO modes supported */
543
#else
544
    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
545
    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
546
    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
547
    put_le16(p + 64, 1); /* PIO modes */
548
#endif
549
    put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
550
    put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
551
    put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
552
    put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
553

    
554
    put_le16(p + 71, 30); /* in ns */
555
    put_le16(p + 72, 30); /* in ns */
556

    
557
    put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
558
#ifdef USE_DMA_CDROM
559
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
560
#endif
561
    memcpy(s->identify_data, p, sizeof(s->identify_data));
562
    s->identify_set = 1;
563
}
564

    
565
static void ide_cfata_identify(IDEState *s)
566
{
567
    uint16_t *p;
568
    uint32_t cur_sec;
569
    char buf[20];
570

    
571
    p = (uint16_t *) s->identify_data;
572
    if (s->identify_set)
573
        goto fill_buffer;
574

    
575
    memset(p, 0, sizeof(s->identify_data));
576

    
577
    cur_sec = s->cylinders * s->heads * s->sectors;
578

    
579
    put_le16(p + 0, 0x848a);                        /* CF Storage Card signature */
580
    put_le16(p + 1, s->cylinders);                /* Default cylinders */
581
    put_le16(p + 3, s->heads);                        /* Default heads */
582
    put_le16(p + 6, s->sectors);                /* Default sectors per track */
583
    put_le16(p + 7, s->nb_sectors >> 16);        /* Sectors per card */
584
    put_le16(p + 8, s->nb_sectors);                /* Sectors per card */
585
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
586
    padstr((uint8_t *)(p + 10), buf, 20);        /* Serial number in ASCII */
587
    put_le16(p + 22, 0x0004);                        /* ECC bytes */
588
    padstr((uint8_t *) (p + 23), QEMU_VERSION, 8);        /* Firmware Revision */
589
    padstr((uint8_t *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
590
#if MAX_MULT_SECTORS > 1
591
    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
592
#else
593
    put_le16(p + 47, 0x0000);
594
#endif
595
    put_le16(p + 49, 0x0f00);                        /* Capabilities */
596
    put_le16(p + 51, 0x0002);                        /* PIO cycle timing mode */
597
    put_le16(p + 52, 0x0001);                        /* DMA cycle timing mode */
598
    put_le16(p + 53, 0x0003);                        /* Translation params valid */
599
    put_le16(p + 54, s->cylinders);                /* Current cylinders */
600
    put_le16(p + 55, s->heads);                        /* Current heads */
601
    put_le16(p + 56, s->sectors);                /* Current sectors */
602
    put_le16(p + 57, cur_sec);                        /* Current capacity */
603
    put_le16(p + 58, cur_sec >> 16);                /* Current capacity */
604
    if (s->mult_sectors)                        /* Multiple sector setting */
605
        put_le16(p + 59, 0x100 | s->mult_sectors);
606
    put_le16(p + 60, s->nb_sectors);                /* Total LBA sectors */
607
    put_le16(p + 61, s->nb_sectors >> 16);        /* Total LBA sectors */
608
    put_le16(p + 63, 0x0203);                        /* Multiword DMA capability */
609
    put_le16(p + 64, 0x0001);                        /* Flow Control PIO support */
610
    put_le16(p + 65, 0x0096);                        /* Min. Multiword DMA cycle */
611
    put_le16(p + 66, 0x0096);                        /* Rec. Multiword DMA cycle */
612
    put_le16(p + 68, 0x00b4);                        /* Min. PIO cycle time */
613
    put_le16(p + 82, 0x400c);                        /* Command Set supported */
614
    put_le16(p + 83, 0x7068);                        /* Command Set supported */
615
    put_le16(p + 84, 0x4000);                        /* Features supported */
616
    put_le16(p + 85, 0x000c);                        /* Command Set enabled */
617
    put_le16(p + 86, 0x7044);                        /* Command Set enabled */
618
    put_le16(p + 87, 0x4000);                        /* Features enabled */
619
    put_le16(p + 91, 0x4060);                        /* Current APM level */
620
    put_le16(p + 129, 0x0002);                        /* Current features option */
621
    put_le16(p + 130, 0x0005);                        /* Reassigned sectors */
622
    put_le16(p + 131, 0x0001);                        /* Initial power mode */
623
    put_le16(p + 132, 0x0000);                        /* User signature */
624
    put_le16(p + 160, 0x8100);                        /* Power requirement */
625
    put_le16(p + 161, 0x8001);                        /* CF command set */
626

    
627
    s->identify_set = 1;
628

    
629
fill_buffer:
630
    memcpy(s->io_buffer, p, sizeof(s->identify_data));
631
}
632

    
633
static void ide_set_signature(IDEState *s)
634
{
635
    s->select &= 0xf0; /* clear head */
636
    /* put signature */
637
    s->nsector = 1;
638
    s->sector = 1;
639
    if (s->is_cdrom) {
640
        s->lcyl = 0x14;
641
        s->hcyl = 0xeb;
642
    } else if (s->bs) {
643
        s->lcyl = 0;
644
        s->hcyl = 0;
645
    } else {
646
        s->lcyl = 0xff;
647
        s->hcyl = 0xff;
648
    }
649
}
650

    
651
static inline void ide_abort_command(IDEState *s)
652
{
653
    s->status = READY_STAT | ERR_STAT;
654
    s->error = ABRT_ERR;
655
}
656

    
657
static inline void ide_set_irq(IDEState *s)
658
{
659
    BMDMAState *bm = s->bmdma;
660
    if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
661
        if (bm) {
662
            bm->status |= BM_STATUS_INT;
663
        }
664
        qemu_irq_raise(s->irq);
665
    }
666
}
667

    
668
/* prepare data transfer and tell what to do after */
669
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size, 
670
                               EndTransferFunc *end_transfer_func)
671
{
672
    s->end_transfer_func = end_transfer_func;
673
    s->data_ptr = buf;
674
    s->data_end = buf + size;
675
    if (!(s->status & ERR_STAT))
676
        s->status |= DRQ_STAT;
677
}
678

    
679
static void ide_transfer_stop(IDEState *s)
680
{
681
    s->end_transfer_func = ide_transfer_stop;
682
    s->data_ptr = s->io_buffer;
683
    s->data_end = s->io_buffer;
684
    s->status &= ~DRQ_STAT;
685
}
686

    
687
static int64_t ide_get_sector(IDEState *s)
688
{
689
    int64_t sector_num;
690
    if (s->select & 0x40) {
691
        /* lba */
692
        if (!s->lba48) {
693
            sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
694
                (s->lcyl << 8) | s->sector;
695
        } else {
696
            sector_num = ((int64_t)s->hob_hcyl << 40) |
697
                ((int64_t) s->hob_lcyl << 32) |
698
                ((int64_t) s->hob_sector << 24) |
699
                ((int64_t) s->hcyl << 16) |
700
                ((int64_t) s->lcyl << 8) | s->sector;
701
        }
702
    } else {
703
        sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
704
            (s->select & 0x0f) * s->sectors + (s->sector - 1);
705
    }
706
    return sector_num;
707
}
708

    
709
static void ide_set_sector(IDEState *s, int64_t sector_num)
710
{
711
    unsigned int cyl, r;
712
    if (s->select & 0x40) {
713
        if (!s->lba48) {
714
            s->select = (s->select & 0xf0) | (sector_num >> 24);
715
            s->hcyl = (sector_num >> 16);
716
            s->lcyl = (sector_num >> 8);
717
            s->sector = (sector_num);
718
        } else {
719
            s->sector = sector_num;
720
            s->lcyl = sector_num >> 8;
721
            s->hcyl = sector_num >> 16;
722
            s->hob_sector = sector_num >> 24;
723
            s->hob_lcyl = sector_num >> 32;
724
            s->hob_hcyl = sector_num >> 40;
725
        }
726
    } else {
727
        cyl = sector_num / (s->heads * s->sectors);
728
        r = sector_num % (s->heads * s->sectors);
729
        s->hcyl = cyl >> 8;
730
        s->lcyl = cyl;
731
        s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
732
        s->sector = (r % s->sectors) + 1;
733
    }
734
}
735

    
736
static void ide_sector_read(IDEState *s)
737
{
738
    int64_t sector_num;
739
    int ret, n;
740

    
741
    s->status = READY_STAT | SEEK_STAT;
742
    s->error = 0; /* not needed by IDE spec, but needed by Windows */
743
    sector_num = ide_get_sector(s);
744
    n = s->nsector;
745
    if (n == 0) {
746
        /* no more sector to read from disk */
747
        ide_transfer_stop(s);
748
    } else {
749
#if defined(DEBUG_IDE)
750
        printf("read sector=%Ld\n", sector_num);
751
#endif
752
        if (n > s->req_nb_sectors)
753
            n = s->req_nb_sectors;
754
        ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
755
        ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
756
        ide_set_irq(s);
757
        ide_set_sector(s, sector_num + n);
758
        s->nsector -= n;
759
    }
760
}
761

    
762
/* return 0 if buffer completed */
763
static int dma_buf_rw(BMDMAState *bm, int is_write)
764
{
765
    IDEState *s = bm->ide_if;
766
    struct {
767
        uint32_t addr;
768
        uint32_t size;
769
    } prd;
770
    int l, len;
771

    
772
    for(;;) {
773
        l = s->io_buffer_size - s->io_buffer_index;
774
        if (l <= 0) 
775
            break;
776
        if (bm->cur_prd_len == 0) {
777
            /* end of table (with a fail safe of one page) */
778
            if (bm->cur_prd_last ||
779
                (bm->cur_addr - bm->addr) >= 4096)
780
                return 0;
781
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
782
            bm->cur_addr += 8;
783
            prd.addr = le32_to_cpu(prd.addr);
784
            prd.size = le32_to_cpu(prd.size);
785
            len = prd.size & 0xfffe;
786
            if (len == 0)
787
                len = 0x10000;
788
            bm->cur_prd_len = len;
789
            bm->cur_prd_addr = prd.addr;
790
            bm->cur_prd_last = (prd.size & 0x80000000);
791
        }
792
        if (l > bm->cur_prd_len)
793
            l = bm->cur_prd_len;
794
        if (l > 0) {
795
            if (is_write) {
796
                cpu_physical_memory_write(bm->cur_prd_addr, 
797
                                          s->io_buffer + s->io_buffer_index, l);
798
            } else {
799
                cpu_physical_memory_read(bm->cur_prd_addr, 
800
                                          s->io_buffer + s->io_buffer_index, l);
801
            }
802
            bm->cur_prd_addr += l;
803
            bm->cur_prd_len -= l;
804
            s->io_buffer_index += l;
805
        }
806
    }
807
    return 1;
808
}
809

    
810
/* XXX: handle errors */
811
static void ide_read_dma_cb(void *opaque, int ret)
812
{
813
    BMDMAState *bm = opaque;
814
    IDEState *s = bm->ide_if;
815
    int n;
816
    int64_t sector_num;
817

    
818
    n = s->io_buffer_size >> 9;
819
    sector_num = ide_get_sector(s);
820
    if (n > 0) {
821
        sector_num += n;
822
        ide_set_sector(s, sector_num);
823
        s->nsector -= n;
824
        if (dma_buf_rw(bm, 1) == 0)
825
            goto eot;
826
    }
827

    
828
    /* end of transfer ? */
829
    if (s->nsector == 0) {
830
        s->status = READY_STAT | SEEK_STAT;
831
        ide_set_irq(s);
832
    eot:
833
        bm->status &= ~BM_STATUS_DMAING;
834
        bm->status |= BM_STATUS_INT;
835
        bm->dma_cb = NULL;
836
        bm->ide_if = NULL;
837
        bm->aiocb = NULL;
838
        return;
839
    }
840

    
841
    /* launch next transfer */
842
    n = s->nsector;
843
    if (n > MAX_MULT_SECTORS)
844
        n = MAX_MULT_SECTORS;
845
    s->io_buffer_index = 0;
846
    s->io_buffer_size = n * 512;
847
#ifdef DEBUG_AIO
848
    printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
849
#endif
850
    bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n, 
851
                              ide_read_dma_cb, bm);
852
}
853

    
854
static void ide_sector_read_dma(IDEState *s)
855
{
856
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
857
    s->io_buffer_index = 0;
858
    s->io_buffer_size = 0;
859
    ide_dma_start(s, ide_read_dma_cb);
860
}
861

    
862
static void ide_sector_write_timer_cb(void *opaque)
863
{
864
    IDEState *s = opaque;
865
    ide_set_irq(s);
866
}
867

    
868
static void ide_sector_write_aio_cb(void *opaque, int ret)
869
{
870
    BMDMAState *bm = opaque;
871
    IDEState *s = bm->ide_if;
872

    
873
#ifdef TARGET_I386
874
    if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
875
        /* It seems there is a bug in the Windows 2000 installer HDD
876
           IDE driver which fills the disk with empty logs when the
877
           IDE write IRQ comes too early. This hack tries to correct
878
           that at the expense of slower write performances. Use this
879
           option _only_ to install Windows 2000. You must disable it
880
           for normal use. */
881
        qemu_mod_timer(s->sector_write_timer,
882
                       qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
883
    } else
884
#endif
885
    {
886
        ide_set_irq(s);
887
    }
888
    bm->aiocb = NULL;
889
}
890

    
891
static void ide_sector_write(IDEState *s)
892
{
893
    BMDMAState *bm;
894
    int64_t sector_num;
895
    int n, n1;
896

    
897
    s->io_buffer_index = 0;
898
    s->io_buffer_size = 0;
899
    bm = s->bmdma;
900
    if(bm == NULL) {
901
        bm = qemu_mallocz(sizeof(BMDMAState));
902
        s->bmdma = bm;
903
    }
904
    bm->ide_if = s;
905
    bm->dma_cb = ide_sector_write_aio_cb;
906

    
907
    s->status = READY_STAT | SEEK_STAT;
908
    sector_num = ide_get_sector(s);
909
#if defined(DEBUG_IDE)
910
    printf("write sector=%Ld\n", sector_num);
911
#endif
912
    n = s->nsector;
913
    if (n > s->req_nb_sectors)
914
        n = s->req_nb_sectors;
915
    s->nsector -= n;
916
    if (s->nsector == 0) {
917
        /* no more sectors to write */
918
        ide_transfer_stop(s);
919
    } else {
920
        n1 = s->nsector;
921
        if (n1 > s->req_nb_sectors)
922
            n1 = s->req_nb_sectors;
923
        ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
924
    }
925
    ide_set_sector(s, sector_num + n);
926
    
927
    bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
928
                               ide_sector_write_aio_cb, bm);
929
}
930

    
931
/* XXX: handle errors */
932
static void ide_write_dma_cb(void *opaque, int ret)
933
{
934
    BMDMAState *bm = opaque;
935
    IDEState *s = bm->ide_if;
936
    int n;
937
    int64_t sector_num;
938

    
939
    n = s->io_buffer_size >> 9;
940
    sector_num = ide_get_sector(s);
941
    if (n > 0) {
942
        sector_num += n;
943
        ide_set_sector(s, sector_num);
944
        s->nsector -= n;
945
    }
946

    
947
    /* end of transfer ? */
948
    if (s->nsector == 0) {
949
        s->status = READY_STAT | SEEK_STAT;
950
        ide_set_irq(s);
951
    eot:
952
        bm->status &= ~BM_STATUS_DMAING;
953
        bm->status |= BM_STATUS_INT;
954
        bm->dma_cb = NULL;
955
        bm->ide_if = NULL;
956
        bm->aiocb = NULL;
957
        return;
958
    }
959

    
960
    /* launch next transfer */
961
    n = s->nsector;
962
    if (n > MAX_MULT_SECTORS)
963
        n = MAX_MULT_SECTORS;
964
    s->io_buffer_index = 0;
965
    s->io_buffer_size = n * 512;
966

    
967
    if (dma_buf_rw(bm, 0) == 0)
968
        goto eot;
969
#ifdef DEBUG_AIO
970
    printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
971
#endif
972
    bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n, 
973
                               ide_write_dma_cb, bm);
974
}
975

    
976
static void ide_sector_write_dma(IDEState *s)
977
{
978
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
979
    s->io_buffer_index = 0;
980
    s->io_buffer_size = 0;
981
    ide_dma_start(s, ide_write_dma_cb);
982
}
983

    
984
static void ide_atapi_cmd_ok(IDEState *s)
985
{
986
    s->error = 0;
987
    s->status = READY_STAT;
988
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
989
    ide_set_irq(s);
990
}
991

    
992
static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
993
{
994
#ifdef DEBUG_IDE_ATAPI
995
    printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
996
#endif
997
    s->error = sense_key << 4;
998
    s->status = READY_STAT | ERR_STAT;
999
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1000
    s->sense_key = sense_key;
1001
    s->asc = asc;
1002
    ide_set_irq(s);
1003
}
1004

    
1005
static inline void cpu_to_ube16(uint8_t *buf, int val)
1006
{
1007
    buf[0] = val >> 8;
1008
    buf[1] = val;
1009
}
1010

    
1011
static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
1012
{
1013
    buf[0] = val >> 24;
1014
    buf[1] = val >> 16;
1015
    buf[2] = val >> 8;
1016
    buf[3] = val;
1017
}
1018

    
1019
static inline int ube16_to_cpu(const uint8_t *buf)
1020
{
1021
    return (buf[0] << 8) | buf[1];
1022
}
1023

    
1024
static inline int ube32_to_cpu(const uint8_t *buf)
1025
{
1026
    return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
1027
}
1028

    
1029
static void lba_to_msf(uint8_t *buf, int lba)
1030
{
1031
    lba += 150;
1032
    buf[0] = (lba / 75) / 60;
1033
    buf[1] = (lba / 75) % 60;
1034
    buf[2] = lba % 75;
1035
}
1036

    
1037
static void cd_data_to_raw(uint8_t *buf, int lba)
1038
{
1039
    /* sync bytes */
1040
    buf[0] = 0x00;
1041
    memset(buf + 1, 0xff, 10);
1042
    buf[11] = 0x00;
1043
    buf += 12;
1044
    /* MSF */
1045
    lba_to_msf(buf, lba);
1046
    buf[3] = 0x01; /* mode 1 data */
1047
    buf += 4;
1048
    /* data */
1049
    buf += 2048;
1050
    /* XXX: ECC not computed */
1051
    memset(buf, 0, 288);
1052
}
1053

    
1054
static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf, 
1055
                           int sector_size)
1056
{
1057
    int ret;
1058

    
1059
    switch(sector_size) {
1060
    case 2048:
1061
        ret = bdrv_read(bs, (int64_t)lba << 2, buf, 4);
1062
        break;
1063
    case 2352:
1064
        ret = bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4);
1065
        if (ret < 0)
1066
            return ret;
1067
        cd_data_to_raw(buf, lba);
1068
        break;
1069
    default:
1070
        ret = -EIO;
1071
        break;
1072
    }
1073
    return ret;
1074
}
1075

    
1076
static void ide_atapi_io_error(IDEState *s, int ret)
1077
{
1078
    /* XXX: handle more errors */
1079
    if (ret == -ENOMEDIUM) {
1080
        ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1081
                            ASC_MEDIUM_NOT_PRESENT);
1082
    } else {
1083
        ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1084
                            ASC_LOGICAL_BLOCK_OOR);
1085
    }
1086
}
1087

    
1088
/* The whole ATAPI transfer logic is handled in this function */
1089
static void ide_atapi_cmd_reply_end(IDEState *s)
1090
{
1091
    int byte_count_limit, size, ret;
1092
#ifdef DEBUG_IDE_ATAPI
1093
    printf("reply: tx_size=%d elem_tx_size=%d index=%d\n", 
1094
           s->packet_transfer_size,
1095
           s->elementary_transfer_size,
1096
           s->io_buffer_index);
1097
#endif
1098
    if (s->packet_transfer_size <= 0) {
1099
        /* end of transfer */
1100
        ide_transfer_stop(s);
1101
        s->status = READY_STAT;
1102
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1103
        ide_set_irq(s);
1104
#ifdef DEBUG_IDE_ATAPI
1105
        printf("status=0x%x\n", s->status);
1106
#endif
1107
    } else {
1108
        /* see if a new sector must be read */
1109
        if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
1110
            ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
1111
            if (ret < 0) {
1112
                ide_transfer_stop(s);
1113
                ide_atapi_io_error(s, ret);
1114
                return;
1115
            }
1116
            s->lba++;
1117
            s->io_buffer_index = 0;
1118
        }
1119
        if (s->elementary_transfer_size > 0) {
1120
            /* there are some data left to transmit in this elementary
1121
               transfer */
1122
            size = s->cd_sector_size - s->io_buffer_index;
1123
            if (size > s->elementary_transfer_size)
1124
                size = s->elementary_transfer_size;
1125
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index, 
1126
                               size, ide_atapi_cmd_reply_end);
1127
            s->packet_transfer_size -= size;
1128
            s->elementary_transfer_size -= size;
1129
            s->io_buffer_index += size;
1130
        } else {
1131
            /* a new transfer is needed */
1132
            s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
1133
            byte_count_limit = s->lcyl | (s->hcyl << 8);
1134
#ifdef DEBUG_IDE_ATAPI
1135
            printf("byte_count_limit=%d\n", byte_count_limit);
1136
#endif
1137
            if (byte_count_limit == 0xffff)
1138
                byte_count_limit--;
1139
            size = s->packet_transfer_size;
1140
            if (size > byte_count_limit) {
1141
                /* byte count limit must be even if this case */
1142
                if (byte_count_limit & 1)
1143
                    byte_count_limit--;
1144
                size = byte_count_limit;
1145
            }
1146
            s->lcyl = size;
1147
            s->hcyl = size >> 8;
1148
            s->elementary_transfer_size = size;
1149
            /* we cannot transmit more than one sector at a time */
1150
            if (s->lba != -1) {
1151
                if (size > (s->cd_sector_size - s->io_buffer_index))
1152
                    size = (s->cd_sector_size - s->io_buffer_index);
1153
            }
1154
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index, 
1155
                               size, ide_atapi_cmd_reply_end);
1156
            s->packet_transfer_size -= size;
1157
            s->elementary_transfer_size -= size;
1158
            s->io_buffer_index += size;
1159
            ide_set_irq(s);
1160
#ifdef DEBUG_IDE_ATAPI
1161
            printf("status=0x%x\n", s->status);
1162
#endif
1163
        }
1164
    }
1165
}
1166

    
1167
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
1168
static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
1169
{
1170
    if (size > max_size)
1171
        size = max_size;
1172
    s->lba = -1; /* no sector read */
1173
    s->packet_transfer_size = size;
1174
    s->io_buffer_size = size;    /* dma: send the reply data as one chunk */
1175
    s->elementary_transfer_size = 0;
1176
    s->io_buffer_index = 0;
1177

    
1178
    if (s->atapi_dma) {
1179
            s->status = READY_STAT | DRQ_STAT;
1180
        ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1181
    } else {
1182
            s->status = READY_STAT;
1183
            ide_atapi_cmd_reply_end(s);
1184
    }
1185
}
1186

    
1187
/* start a CD-CDROM read command */
1188
static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
1189
                                   int sector_size)
1190
{
1191
    s->lba = lba;
1192
    s->packet_transfer_size = nb_sectors * sector_size;
1193
    s->elementary_transfer_size = 0;
1194
    s->io_buffer_index = sector_size;
1195
    s->cd_sector_size = sector_size;
1196

    
1197
    s->status = READY_STAT;
1198
    ide_atapi_cmd_reply_end(s);
1199
}
1200

    
1201
/* ATAPI DMA support */
1202

    
1203
/* XXX: handle read errors */
1204
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
1205
{
1206
    BMDMAState *bm = opaque;
1207
    IDEState *s = bm->ide_if;
1208
    int data_offset, n;
1209

    
1210
    if (ret < 0) {
1211
        ide_atapi_io_error(s, ret);
1212
        goto eot;
1213
    }
1214

    
1215
    if (s->io_buffer_size > 0) {
1216
        /*
1217
         * For a cdrom read sector command (s->lba != -1),
1218
         * adjust the lba for the next s->io_buffer_size chunk
1219
         * and dma the current chunk.
1220
         * For a command != read (s->lba == -1), just transfer
1221
         * the reply data.
1222
         */
1223
        if (s->lba != -1) {
1224
            if (s->cd_sector_size == 2352) {
1225
                n = 1;
1226
                cd_data_to_raw(s->io_buffer, s->lba);
1227
            } else {
1228
                n = s->io_buffer_size >> 11;
1229
            }
1230
            s->lba += n;
1231
        }
1232
        s->packet_transfer_size -= s->io_buffer_size;
1233
        if (dma_buf_rw(bm, 1) == 0)
1234
            goto eot;
1235
    }
1236

    
1237
    if (s->packet_transfer_size <= 0) {
1238
        s->status = READY_STAT;
1239
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1240
        ide_set_irq(s);
1241
    eot:
1242
        bm->status &= ~BM_STATUS_DMAING;
1243
        bm->status |= BM_STATUS_INT;
1244
        bm->dma_cb = NULL;
1245
        bm->ide_if = NULL;
1246
        bm->aiocb = NULL;
1247
        return;
1248
    }
1249
    
1250
    s->io_buffer_index = 0;
1251
    if (s->cd_sector_size == 2352) {
1252
        n = 1;
1253
        s->io_buffer_size = s->cd_sector_size;
1254
        data_offset = 16;
1255
    } else {
1256
        n = s->packet_transfer_size >> 11;
1257
        if (n > (MAX_MULT_SECTORS / 4))
1258
            n = (MAX_MULT_SECTORS / 4);
1259
        s->io_buffer_size = n * 2048;
1260
        data_offset = 0;
1261
    }
1262
#ifdef DEBUG_AIO
1263
    printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
1264
#endif
1265
    bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2, 
1266
                              s->io_buffer + data_offset, n * 4, 
1267
                              ide_atapi_cmd_read_dma_cb, bm);
1268
    if (!bm->aiocb) {
1269
        /* Note: media not present is the most likely case */
1270
        ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1271
                            ASC_MEDIUM_NOT_PRESENT);
1272
        goto eot;
1273
    }
1274
}
1275

    
1276
/* start a CD-CDROM read command with DMA */
1277
/* XXX: test if DMA is available */
1278
static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
1279
                                   int sector_size)
1280
{
1281
    s->lba = lba;
1282
    s->packet_transfer_size = nb_sectors * sector_size;
1283
    s->io_buffer_index = 0;
1284
    s->io_buffer_size = 0;
1285
    s->cd_sector_size = sector_size;
1286

    
1287
    /* XXX: check if BUSY_STAT should be set */
1288
    s->status = READY_STAT | DRQ_STAT | BUSY_STAT;
1289
    ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1290
}
1291

    
1292
static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors, 
1293
                               int sector_size)
1294
{
1295
#ifdef DEBUG_IDE_ATAPI
1296
    printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio",
1297
        lba, nb_sectors);
1298
#endif
1299
    if (s->atapi_dma) {
1300
        ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
1301
    } else {
1302
        ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
1303
    }
1304
}
1305

    
1306
static void ide_atapi_cmd(IDEState *s)
1307
{
1308
    const uint8_t *packet;
1309
    uint8_t *buf;
1310
    int max_len;
1311

    
1312
    packet = s->io_buffer;
1313
    buf = s->io_buffer;
1314
#ifdef DEBUG_IDE_ATAPI
1315
    {
1316
        int i;
1317
        printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1318
        for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1319
            printf(" %02x", packet[i]);
1320
        }
1321
        printf("\n");
1322
    }
1323
#endif
1324
    switch(s->io_buffer[0]) {
1325
    case GPCMD_TEST_UNIT_READY:
1326
        if (bdrv_is_inserted(s->bs)) {
1327
            ide_atapi_cmd_ok(s);
1328
        } else {
1329
            ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1330
                                ASC_MEDIUM_NOT_PRESENT);
1331
        }
1332
        break;
1333
    case GPCMD_MODE_SENSE_6:
1334
    case GPCMD_MODE_SENSE_10:
1335
        {
1336
            int action, code;
1337
            if (packet[0] == GPCMD_MODE_SENSE_10)
1338
                max_len = ube16_to_cpu(packet + 7);
1339
            else
1340
                max_len = packet[4];
1341
            action = packet[2] >> 6;
1342
            code = packet[2] & 0x3f;
1343
            switch(action) {
1344
            case 0: /* current values */
1345
                switch(code) {
1346
                case 0x01: /* error recovery */
1347
                    cpu_to_ube16(&buf[0], 16 + 6);
1348
                    buf[2] = 0x70;
1349
                    buf[3] = 0;
1350
                    buf[4] = 0;
1351
                    buf[5] = 0;
1352
                    buf[6] = 0;
1353
                    buf[7] = 0;
1354

    
1355
                    buf[8] = 0x01;
1356
                    buf[9] = 0x06;
1357
                    buf[10] = 0x00;
1358
                    buf[11] = 0x05;
1359
                    buf[12] = 0x00;
1360
                    buf[13] = 0x00;
1361
                    buf[14] = 0x00;
1362
                    buf[15] = 0x00;
1363
                    ide_atapi_cmd_reply(s, 16, max_len);
1364
                    break;
1365
                case 0x2a:
1366
                    cpu_to_ube16(&buf[0], 28 + 6);
1367
                    buf[2] = 0x70;
1368
                    buf[3] = 0;
1369
                    buf[4] = 0;
1370
                    buf[5] = 0;
1371
                    buf[6] = 0;
1372
                    buf[7] = 0;
1373

    
1374
                    buf[8] = 0x2a;
1375
                    buf[9] = 0x12;
1376
                    buf[10] = 0x08;
1377
                    buf[11] = 0x00;
1378
                    
1379
                    buf[12] = 0x70;
1380
                    buf[13] = 3 << 5;
1381
                    buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1382
                    if (bdrv_is_locked(s->bs))
1383
                        buf[6] |= 1 << 1;
1384
                    buf[15] = 0x00;
1385
                    cpu_to_ube16(&buf[16], 706);
1386
                    buf[18] = 0;
1387
                    buf[19] = 2;
1388
                    cpu_to_ube16(&buf[20], 512);
1389
                    cpu_to_ube16(&buf[22], 706);
1390
                    buf[24] = 0;
1391
                    buf[25] = 0;
1392
                    buf[26] = 0;
1393
                    buf[27] = 0;
1394
                    ide_atapi_cmd_reply(s, 28, max_len);
1395
                    break;
1396
                default:
1397
                    goto error_cmd;
1398
                }
1399
                break;
1400
            case 1: /* changeable values */
1401
                goto error_cmd;
1402
            case 2: /* default values */
1403
                goto error_cmd;
1404
            default:
1405
            case 3: /* saved values */
1406
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1407
                                    ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1408
                break;
1409
            }
1410
        }
1411
        break;
1412
    case GPCMD_REQUEST_SENSE:
1413
        max_len = packet[4];
1414
        memset(buf, 0, 18);
1415
        buf[0] = 0x70 | (1 << 7);
1416
        buf[2] = s->sense_key;
1417
        buf[7] = 10;
1418
        buf[12] = s->asc;
1419
        ide_atapi_cmd_reply(s, 18, max_len);
1420
        break;
1421
    case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1422
        if (bdrv_is_inserted(s->bs)) {
1423
            bdrv_set_locked(s->bs, packet[4] & 1);
1424
            ide_atapi_cmd_ok(s);
1425
        } else {
1426
            ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1427
                                ASC_MEDIUM_NOT_PRESENT);
1428
        }
1429
        break;
1430
    case GPCMD_READ_10:
1431
    case GPCMD_READ_12:
1432
        {
1433
            int nb_sectors, lba;
1434

    
1435
            if (packet[0] == GPCMD_READ_10)
1436
                nb_sectors = ube16_to_cpu(packet + 7);
1437
            else
1438
                nb_sectors = ube32_to_cpu(packet + 6);
1439
            lba = ube32_to_cpu(packet + 2);
1440
            if (nb_sectors == 0) {
1441
                ide_atapi_cmd_ok(s);
1442
                break;
1443
            }
1444
            ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1445
        }
1446
        break;
1447
    case GPCMD_READ_CD:
1448
        {
1449
            int nb_sectors, lba, transfer_request;
1450

    
1451
            nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1452
            lba = ube32_to_cpu(packet + 2);
1453
            if (nb_sectors == 0) {
1454
                ide_atapi_cmd_ok(s);
1455
                break;
1456
            }
1457
            transfer_request = packet[9];
1458
            switch(transfer_request & 0xf8) {
1459
            case 0x00:
1460
                /* nothing */
1461
                ide_atapi_cmd_ok(s);
1462
                break;
1463
            case 0x10:
1464
                /* normal read */
1465
                ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1466
                break;
1467
            case 0xf8:
1468
                /* read all data */
1469
                ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1470
                break;
1471
            default:
1472
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1473
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1474
                break;
1475
            }
1476
        }
1477
        break;
1478
    case GPCMD_SEEK:
1479
        {
1480
            int lba;
1481
            int64_t total_sectors;
1482

    
1483
            bdrv_get_geometry(s->bs, &total_sectors);
1484
            total_sectors >>= 2;
1485
            if (total_sectors <= 0) {
1486
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1487
                                    ASC_MEDIUM_NOT_PRESENT);
1488
                break;
1489
            }
1490
            lba = ube32_to_cpu(packet + 2);
1491
            if (lba >= total_sectors) {
1492
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1493
                                    ASC_LOGICAL_BLOCK_OOR);
1494
                break;
1495
            }
1496
            ide_atapi_cmd_ok(s);
1497
        }
1498
        break;
1499
    case GPCMD_START_STOP_UNIT:
1500
        {
1501
            int start, eject;
1502
            start = packet[4] & 1;
1503
            eject = (packet[4] >> 1) & 1;
1504
            
1505
            if (eject && !start) {
1506
                /* eject the disk */
1507
                bdrv_eject(s->bs, 1);
1508
            } else if (eject && start) {
1509
                /* close the tray */
1510
                bdrv_eject(s->bs, 0);
1511
            }
1512
            ide_atapi_cmd_ok(s);
1513
        }
1514
        break;
1515
    case GPCMD_MECHANISM_STATUS:
1516
        {
1517
            max_len = ube16_to_cpu(packet + 8);
1518
            cpu_to_ube16(buf, 0);
1519
            /* no current LBA */
1520
            buf[2] = 0;
1521
            buf[3] = 0;
1522
            buf[4] = 0;
1523
            buf[5] = 1;
1524
            cpu_to_ube16(buf + 6, 0);
1525
            ide_atapi_cmd_reply(s, 8, max_len);
1526
        }
1527
        break;
1528
    case GPCMD_READ_TOC_PMA_ATIP:
1529
        {
1530
            int format, msf, start_track, len;
1531
            int64_t total_sectors;
1532

    
1533
            bdrv_get_geometry(s->bs, &total_sectors);
1534
            total_sectors >>= 2;
1535
            if (total_sectors <= 0) {
1536
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1537
                                    ASC_MEDIUM_NOT_PRESENT);
1538
                break;
1539
            }
1540
            max_len = ube16_to_cpu(packet + 7);
1541
            format = packet[9] >> 6;
1542
            msf = (packet[1] >> 1) & 1;
1543
            start_track = packet[6];
1544
            switch(format) {
1545
            case 0:
1546
                len = cdrom_read_toc(total_sectors, buf, msf, start_track);
1547
                if (len < 0)
1548
                    goto error_cmd;
1549
                ide_atapi_cmd_reply(s, len, max_len);
1550
                break;
1551
            case 1:
1552
                /* multi session : only a single session defined */
1553
                memset(buf, 0, 12);
1554
                buf[1] = 0x0a;
1555
                buf[2] = 0x01;
1556
                buf[3] = 0x01;
1557
                ide_atapi_cmd_reply(s, 12, max_len);
1558
                break;
1559
            case 2:
1560
                len = cdrom_read_toc_raw(total_sectors, buf, msf, start_track);
1561
                if (len < 0)
1562
                    goto error_cmd;
1563
                ide_atapi_cmd_reply(s, len, max_len);
1564
                break;
1565
            default:
1566
            error_cmd:
1567
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1568
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1569
                break;
1570
            }
1571
        }
1572
        break;
1573
    case GPCMD_READ_CDVD_CAPACITY:
1574
        {
1575
            int64_t total_sectors;
1576

    
1577
            bdrv_get_geometry(s->bs, &total_sectors);
1578
            total_sectors >>= 2;
1579
            if (total_sectors <= 0) {
1580
                ide_atapi_cmd_error(s, SENSE_NOT_READY, 
1581
                                    ASC_MEDIUM_NOT_PRESENT);
1582
                break;
1583
            }
1584
            /* NOTE: it is really the number of sectors minus 1 */
1585
            cpu_to_ube32(buf, total_sectors - 1);
1586
            cpu_to_ube32(buf + 4, 2048);
1587
            ide_atapi_cmd_reply(s, 8, 8);
1588
        }
1589
        break;
1590
    case GPCMD_READ_DVD_STRUCTURE:
1591
        {
1592
            int media = packet[1];
1593
            int layer = packet[6];
1594
            int format = packet[2];
1595
            int64_t total_sectors;
1596

    
1597
            if (media != 0 || layer != 0)
1598
            {
1599
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1600
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1601
            }
1602

    
1603
            switch (format) {
1604
                case 0:
1605
                    bdrv_get_geometry(s->bs, &total_sectors);
1606
                    total_sectors >>= 2;
1607

    
1608
                    memset(buf, 0, 2052);
1609

    
1610
                    buf[4] = 1;   // DVD-ROM, part version 1
1611
                    buf[5] = 0xf; // 120mm disc, maximum rate unspecified
1612
                    buf[6] = 0;   // one layer, embossed data
1613
                    buf[7] = 0;
1614

    
1615
                    cpu_to_ube32(buf + 8, 0);
1616
                    cpu_to_ube32(buf + 12, total_sectors - 1);
1617
                    cpu_to_ube32(buf + 16, total_sectors - 1);
1618

    
1619
                    cpu_to_be16wu((uint16_t *)buf, 2048 + 4);
1620

    
1621
                    ide_atapi_cmd_reply(s, 2048 + 3, 2048 + 4);
1622
                    break;
1623

    
1624
                default:
1625
                    ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1626
                                        ASC_INV_FIELD_IN_CMD_PACKET);
1627
                    break;
1628
            }
1629
        }
1630
        break;
1631
    case GPCMD_SET_SPEED:
1632
        ide_atapi_cmd_ok(s);
1633
        break;
1634
    case GPCMD_INQUIRY:
1635
        max_len = packet[4];
1636
        buf[0] = 0x05; /* CD-ROM */
1637
        buf[1] = 0x80; /* removable */
1638
        buf[2] = 0x00; /* ISO */
1639
        buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1640
        buf[4] = 31; /* additional length */
1641
        buf[5] = 0; /* reserved */
1642
        buf[6] = 0; /* reserved */
1643
        buf[7] = 0; /* reserved */
1644
        padstr8(buf + 8, 8, "QEMU");
1645
        padstr8(buf + 16, 16, "QEMU CD-ROM");
1646
        padstr8(buf + 32, 4, QEMU_VERSION);
1647
        ide_atapi_cmd_reply(s, 36, max_len);
1648
        break;
1649
    case GPCMD_GET_CONFIGURATION:
1650
        {
1651
            int64_t total_sectors;
1652

    
1653
            /* only feature 0 is supported */
1654
            if (packet[2] != 0 || packet[3] != 0) {
1655
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1656
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1657
                break;
1658
            }
1659
            memset(buf, 0, 32);
1660
            bdrv_get_geometry(s->bs, &total_sectors);
1661
            buf[3] = 16;
1662
            buf[7] = total_sectors <= 1433600 ? 0x08 : 0x10; /* current profile */
1663
            buf[10] = 0x10 | 0x1;
1664
            buf[11] = 0x08; /* size of profile list */
1665
            buf[13] = 0x10; /* DVD-ROM profile */
1666
            buf[14] = buf[7] == 0x10; /* (in)active */
1667
            buf[17] = 0x08; /* CD-ROM profile */
1668
            buf[18] = buf[7] == 0x08; /* (in)active */
1669
            ide_atapi_cmd_reply(s, 32, 32);
1670
            break;
1671
        }
1672
    default:
1673
        ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST, 
1674
                            ASC_ILLEGAL_OPCODE);
1675
        break;
1676
    }
1677
}
1678

    
1679
static void ide_cfata_metadata_inquiry(IDEState *s)
1680
{
1681
    uint16_t *p;
1682
    uint32_t spd;
1683

    
1684
    p = (uint16_t *) s->io_buffer;
1685
    memset(p, 0, 0x200);
1686
    spd = ((s->mdata_size - 1) >> 9) + 1;
1687

    
1688
    put_le16(p + 0, 0x0001);                        /* Data format revision */
1689
    put_le16(p + 1, 0x0000);                        /* Media property: silicon */
1690
    put_le16(p + 2, s->media_changed);                /* Media status */
1691
    put_le16(p + 3, s->mdata_size & 0xffff);        /* Capacity in bytes (low) */
1692
    put_le16(p + 4, s->mdata_size >> 16);        /* Capacity in bytes (high) */
1693
    put_le16(p + 5, spd & 0xffff);                /* Sectors per device (low) */
1694
    put_le16(p + 6, spd >> 16);                        /* Sectors per device (high) */
1695
}
1696

    
1697
static void ide_cfata_metadata_read(IDEState *s)
1698
{
1699
    uint16_t *p;
1700

    
1701
    if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1702
        s->status = ERR_STAT;
1703
        s->error = ABRT_ERR;
1704
        return;
1705
    }
1706

    
1707
    p = (uint16_t *) s->io_buffer;
1708
    memset(p, 0, 0x200);
1709

    
1710
    put_le16(p + 0, s->media_changed);                /* Media status */
1711
    memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1712
                    MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1713
                                    s->nsector << 9), 0x200 - 2));
1714
}
1715

    
1716
static void ide_cfata_metadata_write(IDEState *s)
1717
{
1718
    if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1719
        s->status = ERR_STAT;
1720
        s->error = ABRT_ERR;
1721
        return;
1722
    }
1723

    
1724
    s->media_changed = 0;
1725

    
1726
    memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1727
                    s->io_buffer + 2,
1728
                    MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1729
                                    s->nsector << 9), 0x200 - 2));
1730
}
1731

    
1732
/* called when the inserted state of the media has changed */
1733
static void cdrom_change_cb(void *opaque)
1734
{
1735
    IDEState *s = opaque;
1736
    int64_t nb_sectors;
1737

    
1738
    /* XXX: send interrupt too */
1739
    bdrv_get_geometry(s->bs, &nb_sectors);
1740
    s->nb_sectors = nb_sectors;
1741
}
1742

    
1743
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1744
{
1745
    s->lba48 = lba48;
1746

    
1747
    /* handle the 'magic' 0 nsector count conversion here. to avoid
1748
     * fiddling with the rest of the read logic, we just store the
1749
     * full sector count in ->nsector and ignore ->hob_nsector from now
1750
     */
1751
    if (!s->lba48) {
1752
        if (!s->nsector)
1753
            s->nsector = 256;
1754
    } else {
1755
        if (!s->nsector && !s->hob_nsector)
1756
            s->nsector = 65536;
1757
        else {
1758
            int lo = s->nsector;
1759
            int hi = s->hob_nsector;
1760

    
1761
            s->nsector = (hi << 8) | lo;
1762
        }
1763
    }
1764
}
1765

    
1766
static void ide_clear_hob(IDEState *ide_if)
1767
{
1768
    /* any write clears HOB high bit of device control register */
1769
    ide_if[0].select &= ~(1 << 7);
1770
    ide_if[1].select &= ~(1 << 7);
1771
}
1772

    
1773
static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1774
{
1775
    IDEState *ide_if = opaque;
1776
    IDEState *s;
1777
    int unit, n;
1778
    int lba48 = 0;
1779

    
1780
#ifdef DEBUG_IDE
1781
    printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1782
#endif
1783

    
1784
    addr &= 7;
1785
    switch(addr) {
1786
    case 0:
1787
        break;
1788
    case 1:
1789
        ide_clear_hob(ide_if);
1790
        /* NOTE: data is written to the two drives */
1791
        ide_if[0].hob_feature = ide_if[0].feature;
1792
        ide_if[1].hob_feature = ide_if[1].feature;
1793
        ide_if[0].feature = val;
1794
        ide_if[1].feature = val;
1795
        break;
1796
    case 2:
1797
        ide_clear_hob(ide_if);
1798
        ide_if[0].hob_nsector = ide_if[0].nsector;
1799
        ide_if[1].hob_nsector = ide_if[1].nsector;
1800
        ide_if[0].nsector = val;
1801
        ide_if[1].nsector = val;
1802
        break;
1803
    case 3:
1804
        ide_clear_hob(ide_if);
1805
        ide_if[0].hob_sector = ide_if[0].sector;
1806
        ide_if[1].hob_sector = ide_if[1].sector;
1807
        ide_if[0].sector = val;
1808
        ide_if[1].sector = val;
1809
        break;
1810
    case 4:
1811
        ide_clear_hob(ide_if);
1812
        ide_if[0].hob_lcyl = ide_if[0].lcyl;
1813
        ide_if[1].hob_lcyl = ide_if[1].lcyl;
1814
        ide_if[0].lcyl = val;
1815
        ide_if[1].lcyl = val;
1816
        break;
1817
    case 5:
1818
        ide_clear_hob(ide_if);
1819
        ide_if[0].hob_hcyl = ide_if[0].hcyl;
1820
        ide_if[1].hob_hcyl = ide_if[1].hcyl;
1821
        ide_if[0].hcyl = val;
1822
        ide_if[1].hcyl = val;
1823
        break;
1824
    case 6:
1825
        /* FIXME: HOB readback uses bit 7 */
1826
        ide_if[0].select = (val & ~0x10) | 0xa0;
1827
        ide_if[1].select = (val | 0x10) | 0xa0;
1828
        /* select drive */
1829
        unit = (val >> 4) & 1;
1830
        s = ide_if + unit;
1831
        ide_if->cur_drive = s;
1832
        break;
1833
    default:
1834
    case 7:
1835
        /* command */
1836
#if defined(DEBUG_IDE)
1837
        printf("ide: CMD=%02x\n", val);
1838
#endif
1839
        s = ide_if->cur_drive;
1840
        /* ignore commands to non existant slave */
1841
        if (s != ide_if && !s->bs) 
1842
            break;
1843

    
1844
        switch(val) {
1845
        case WIN_IDENTIFY:
1846
            if (s->bs && !s->is_cdrom) {
1847
                if (!s->is_cf)
1848
                    ide_identify(s);
1849
                else
1850
                    ide_cfata_identify(s);
1851
                s->status = READY_STAT | SEEK_STAT;
1852
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1853
            } else {
1854
                if (s->is_cdrom) {
1855
                    ide_set_signature(s);
1856
                }
1857
                ide_abort_command(s);
1858
            }
1859
            ide_set_irq(s);
1860
            break;
1861
        case WIN_SPECIFY:
1862
        case WIN_RECAL:
1863
            s->error = 0;
1864
            s->status = READY_STAT | SEEK_STAT;
1865
            ide_set_irq(s);
1866
            break;
1867
        case WIN_SETMULT:
1868
            if (s->is_cf && s->nsector == 0) {
1869
                /* Disable Read and Write Multiple */
1870
                s->mult_sectors = 0;
1871
                s->status = READY_STAT;
1872
            } else if ((s->nsector & 0xff) != 0 &&
1873
                ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1874
                 (s->nsector & (s->nsector - 1)) != 0)) {
1875
                ide_abort_command(s);
1876
            } else {
1877
                s->mult_sectors = s->nsector & 0xff;
1878
                s->status = READY_STAT;
1879
            }
1880
            ide_set_irq(s);
1881
            break;
1882
        case WIN_VERIFY_EXT:
1883
            lba48 = 1;
1884
        case WIN_VERIFY:
1885
        case WIN_VERIFY_ONCE:
1886
            /* do sector number check ? */
1887
            ide_cmd_lba48_transform(s, lba48);
1888
            s->status = READY_STAT;
1889
            ide_set_irq(s);
1890
            break;
1891
        case WIN_READ_EXT:
1892
            lba48 = 1;
1893
        case WIN_READ:
1894
        case WIN_READ_ONCE:
1895
            if (!s->bs) 
1896
                goto abort_cmd;
1897
            ide_cmd_lba48_transform(s, lba48);
1898
            s->req_nb_sectors = 1;
1899
            ide_sector_read(s);
1900
            break;
1901
        case WIN_WRITE_EXT:
1902
            lba48 = 1;
1903
        case WIN_WRITE:
1904
        case WIN_WRITE_ONCE:
1905
        case CFA_WRITE_SECT_WO_ERASE:
1906
        case WIN_WRITE_VERIFY:
1907
            ide_cmd_lba48_transform(s, lba48);
1908
            s->error = 0;
1909
            s->status = SEEK_STAT | READY_STAT;
1910
            s->req_nb_sectors = 1;
1911
            ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1912
            s->media_changed = 1;
1913
            break;
1914
        case WIN_MULTREAD_EXT:
1915
            lba48 = 1;
1916
        case WIN_MULTREAD:
1917
            if (!s->mult_sectors)
1918
                goto abort_cmd;
1919
            ide_cmd_lba48_transform(s, lba48);
1920
            s->req_nb_sectors = s->mult_sectors;
1921
            ide_sector_read(s);
1922
            break;
1923
        case WIN_MULTWRITE_EXT:
1924
            lba48 = 1;
1925
        case WIN_MULTWRITE:
1926
        case CFA_WRITE_MULTI_WO_ERASE:
1927
            if (!s->mult_sectors)
1928
                goto abort_cmd;
1929
            ide_cmd_lba48_transform(s, lba48);
1930
            s->error = 0;
1931
            s->status = SEEK_STAT | READY_STAT;
1932
            s->req_nb_sectors = s->mult_sectors;
1933
            n = s->nsector;
1934
            if (n > s->req_nb_sectors)
1935
                n = s->req_nb_sectors;
1936
            ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1937
            s->media_changed = 1;
1938
            break;
1939
        case WIN_READDMA_EXT:
1940
            lba48 = 1;
1941
        case WIN_READDMA:
1942
        case WIN_READDMA_ONCE:
1943
            if (!s->bs) 
1944
                goto abort_cmd;
1945
            ide_cmd_lba48_transform(s, lba48);
1946
            ide_sector_read_dma(s);
1947
            break;
1948
        case WIN_WRITEDMA_EXT:
1949
            lba48 = 1;
1950
        case WIN_WRITEDMA:
1951
        case WIN_WRITEDMA_ONCE:
1952
            if (!s->bs) 
1953
                goto abort_cmd;
1954
            ide_cmd_lba48_transform(s, lba48);
1955
            ide_sector_write_dma(s);
1956
            s->media_changed = 1;
1957
            break;
1958
        case WIN_READ_NATIVE_MAX_EXT:
1959
            lba48 = 1;
1960
        case WIN_READ_NATIVE_MAX:
1961
            ide_cmd_lba48_transform(s, lba48);
1962
            ide_set_sector(s, s->nb_sectors - 1);
1963
            s->status = READY_STAT;
1964
            ide_set_irq(s);
1965
            break;
1966
        case WIN_CHECKPOWERMODE1:
1967
        case WIN_CHECKPOWERMODE2:
1968
            s->nsector = 0xff; /* device active or idle */
1969
            s->status = READY_STAT;
1970
            ide_set_irq(s);
1971
            break;
1972
        case WIN_SETFEATURES:
1973
            if (!s->bs)
1974
                goto abort_cmd;
1975
            /* XXX: valid for CDROM ? */
1976
            switch(s->feature) {
1977
            case 0xcc: /* reverting to power-on defaults enable */
1978
            case 0x66: /* reverting to power-on defaults disable */
1979
            case 0x02: /* write cache enable */
1980
            case 0x82: /* write cache disable */
1981
            case 0xaa: /* read look-ahead enable */
1982
            case 0x55: /* read look-ahead disable */
1983
            case 0x05: /* set advanced power management mode */
1984
            case 0x85: /* disable advanced power management mode */
1985
            case 0x69: /* NOP */
1986
            case 0x67: /* NOP */
1987
            case 0x96: /* NOP */
1988
            case 0x9a: /* NOP */
1989
                s->status = READY_STAT | SEEK_STAT;
1990
                ide_set_irq(s);
1991
                break;
1992
            case 0x03: { /* set transfer mode */
1993
                uint8_t val = s->nsector & 0x07;
1994

    
1995
                switch (s->nsector >> 3) {
1996
                    case 0x00: /* pio default */
1997
                    case 0x01: /* pio mode */
1998
                        put_le16(s->identify_data + 63,0x07);
1999
                        put_le16(s->identify_data + 88,0x3f);
2000
                        break;
2001
                    case 0x04: /* mdma mode */
2002
                        put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
2003
                        put_le16(s->identify_data + 88,0x3f);
2004
                        break;
2005
                    case 0x08: /* udma mode */
2006
                        put_le16(s->identify_data + 63,0x07);
2007
                        put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
2008
                        break;
2009
                    default:
2010
                        goto abort_cmd;
2011
                }
2012
                s->status = READY_STAT | SEEK_STAT;
2013
                ide_set_irq(s);
2014
                break;
2015
            }
2016
            default:
2017
                goto abort_cmd;
2018
            }
2019
            break;
2020
        case WIN_FLUSH_CACHE:
2021
        case WIN_FLUSH_CACHE_EXT:
2022
            if (s->bs)
2023
                bdrv_flush(s->bs);
2024
            s->status = READY_STAT;
2025
            ide_set_irq(s);
2026
            break;
2027
        case WIN_STANDBYNOW1:
2028
        case WIN_STANDBYNOW2:
2029
        case WIN_IDLEIMMEDIATE:
2030
        case CFA_IDLEIMMEDIATE:
2031
        case WIN_SETIDLE1:
2032
        case WIN_SETIDLE2:
2033
            s->status = READY_STAT;
2034
            ide_set_irq(s);
2035
            break;
2036
            /* ATAPI commands */
2037
        case WIN_PIDENTIFY:
2038
            if (s->is_cdrom) {
2039
                ide_atapi_identify(s);
2040
                s->status = READY_STAT | SEEK_STAT;
2041
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
2042
            } else {
2043
                ide_abort_command(s);
2044
            }
2045
            ide_set_irq(s);
2046
            break;
2047
        case WIN_DIAGNOSE:
2048
            ide_set_signature(s);
2049
            s->status = 0x00; /* NOTE: READY is _not_ set */
2050
            s->error = 0x01;
2051
            break;
2052
        case WIN_SRST:
2053
            if (!s->is_cdrom)
2054
                goto abort_cmd;
2055
            ide_set_signature(s);
2056
            s->status = 0x00; /* NOTE: READY is _not_ set */
2057
            s->error = 0x01;
2058
            break;
2059
        case WIN_PACKETCMD:
2060
            if (!s->is_cdrom)
2061
                goto abort_cmd;
2062
            /* overlapping commands not supported */
2063
            if (s->feature & 0x02)
2064
                goto abort_cmd;
2065
            s->status = READY_STAT;
2066
            s->atapi_dma = s->feature & 1;
2067
            s->nsector = 1;
2068
            ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE, 
2069
                               ide_atapi_cmd);
2070
            break;
2071
        /* CF-ATA commands */
2072
        case CFA_REQ_EXT_ERROR_CODE:
2073
            if (!s->is_cf)
2074
                goto abort_cmd;
2075
            s->error = 0x09;    /* miscellaneous error */
2076
            s->status = READY_STAT;
2077
            ide_set_irq(s);
2078
            break;
2079
        case CFA_ERASE_SECTORS:
2080
        case CFA_WEAR_LEVEL:
2081
            if (!s->is_cf)
2082
                goto abort_cmd;
2083
            if (val == CFA_WEAR_LEVEL)
2084
                s->nsector = 0;
2085
            if (val == CFA_ERASE_SECTORS)
2086
                s->media_changed = 1;
2087
            s->error = 0x00;
2088
            s->status = READY_STAT;
2089
            ide_set_irq(s);
2090
            break;
2091
        case CFA_TRANSLATE_SECTOR:
2092
            if (!s->is_cf)
2093
                goto abort_cmd;
2094
            s->error = 0x00;
2095
            s->status = READY_STAT;
2096
            memset(s->io_buffer, 0, 0x200);
2097
            s->io_buffer[0x00] = s->hcyl;                        /* Cyl MSB */
2098
            s->io_buffer[0x01] = s->lcyl;                        /* Cyl LSB */
2099
            s->io_buffer[0x02] = s->select;                        /* Head */
2100
            s->io_buffer[0x03] = s->sector;                        /* Sector */
2101
            s->io_buffer[0x04] = ide_get_sector(s) >> 16;        /* LBA MSB */
2102
            s->io_buffer[0x05] = ide_get_sector(s) >> 8;        /* LBA */
2103
            s->io_buffer[0x06] = ide_get_sector(s) >> 0;        /* LBA LSB */
2104
            s->io_buffer[0x13] = 0x00;                                /* Erase flag */
2105
            s->io_buffer[0x18] = 0x00;                                /* Hot count */
2106
            s->io_buffer[0x19] = 0x00;                                /* Hot count */
2107
            s->io_buffer[0x1a] = 0x01;                                /* Hot count */
2108
            ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2109
            ide_set_irq(s);
2110
            break;
2111
        case CFA_ACCESS_METADATA_STORAGE:
2112
            if (!s->is_cf)
2113
                goto abort_cmd;
2114
            switch (s->feature) {
2115
            case 0x02:        /* Inquiry Metadata Storage */
2116
                ide_cfata_metadata_inquiry(s);
2117
                break;
2118
            case 0x03:        /* Read Metadata Storage */
2119
                ide_cfata_metadata_read(s);
2120
                break;
2121
            case 0x04:        /* Write Metadata Storage */
2122
                ide_cfata_metadata_write(s);
2123
                break;
2124
            default:
2125
                goto abort_cmd;
2126
            }
2127
            ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2128
            s->status = 0x00; /* NOTE: READY is _not_ set */
2129
            ide_set_irq(s);
2130
            break;
2131
        case IBM_SENSE_CONDITION:
2132
            if (!s->is_cf)
2133
                goto abort_cmd;
2134
            switch (s->feature) {
2135
            case 0x01:  /* sense temperature in device */
2136
                s->nsector = 0x50;      /* +20 C */
2137
                break;
2138
            default:
2139
                goto abort_cmd;
2140
            }
2141
            s->status = READY_STAT;
2142
            ide_set_irq(s);
2143
            break;
2144
        default:
2145
        abort_cmd:
2146
            ide_abort_command(s);
2147
            ide_set_irq(s);
2148
            break;
2149
        }
2150
    }
2151
}
2152

    
2153
static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2154
{
2155
    IDEState *ide_if = opaque;
2156
    IDEState *s = ide_if->cur_drive;
2157
    uint32_t addr;
2158
    int ret, hob;
2159

    
2160
    addr = addr1 & 7;
2161
    /* FIXME: HOB readback uses bit 7, but it's always set right now */
2162
    //hob = s->select & (1 << 7);
2163
    hob = 0;
2164
    switch(addr) {
2165
    case 0:
2166
        ret = 0xff;
2167
        break;
2168
    case 1:
2169
        if (!ide_if[0].bs && !ide_if[1].bs)
2170
            ret = 0;
2171
        else if (!hob)
2172
            ret = s->error;
2173
        else
2174
            ret = s->hob_feature;
2175
        break;
2176
    case 2:
2177
        if (!ide_if[0].bs && !ide_if[1].bs)
2178
            ret = 0;
2179
        else if (!hob)
2180
            ret = s->nsector & 0xff;
2181
        else
2182
            ret = s->hob_nsector;
2183
        break;
2184
    case 3:
2185
        if (!ide_if[0].bs && !ide_if[1].bs)
2186
            ret = 0;
2187
        else if (!hob)
2188
            ret = s->sector;
2189
        else
2190
            ret = s->hob_sector;
2191
        break;
2192
    case 4:
2193
        if (!ide_if[0].bs && !ide_if[1].bs)
2194
            ret = 0;
2195
        else if (!hob)
2196
            ret = s->lcyl;
2197
        else
2198
            ret = s->hob_lcyl;
2199
        break;
2200
    case 5:
2201
        if (!ide_if[0].bs && !ide_if[1].bs)
2202
            ret = 0;
2203
        else if (!hob)
2204
            ret = s->hcyl;
2205
        else
2206
            ret = s->hob_hcyl;
2207
        break;
2208
    case 6:
2209
        if (!ide_if[0].bs && !ide_if[1].bs)
2210
            ret = 0;
2211
        else
2212
            ret = s->select;
2213
        break;
2214
    default:
2215
    case 7:
2216
        if ((!ide_if[0].bs && !ide_if[1].bs) ||
2217
            (s != ide_if && !s->bs))
2218
            ret = 0;
2219
        else
2220
            ret = s->status;
2221
        qemu_irq_lower(s->irq);
2222
        break;
2223
    }
2224
#ifdef DEBUG_IDE
2225
    printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2226
#endif
2227
    return ret;
2228
}
2229

    
2230
static uint32_t ide_status_read(void *opaque, uint32_t addr)
2231
{
2232
    IDEState *ide_if = opaque;
2233
    IDEState *s = ide_if->cur_drive;
2234
    int ret;
2235

    
2236
    if ((!ide_if[0].bs && !ide_if[1].bs) ||
2237
        (s != ide_if && !s->bs))
2238
        ret = 0;
2239
    else
2240
        ret = s->status;
2241
#ifdef DEBUG_IDE
2242
    printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2243
#endif
2244
    return ret;
2245
}
2246

    
2247
static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2248
{
2249
    IDEState *ide_if = opaque;
2250
    IDEState *s;
2251
    int i;
2252

    
2253
#ifdef DEBUG_IDE
2254
    printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2255
#endif
2256
    /* common for both drives */
2257
    if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
2258
        (val & IDE_CMD_RESET)) {
2259
        /* reset low to high */
2260
        for(i = 0;i < 2; i++) {
2261
            s = &ide_if[i];
2262
            s->status = BUSY_STAT | SEEK_STAT;
2263
            s->error = 0x01;
2264
        }
2265
    } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
2266
               !(val & IDE_CMD_RESET)) {
2267
        /* high to low */
2268
        for(i = 0;i < 2; i++) {
2269
            s = &ide_if[i];
2270
            if (s->is_cdrom)
2271
                s->status = 0x00; /* NOTE: READY is _not_ set */
2272
            else
2273
                s->status = READY_STAT | SEEK_STAT;
2274
            ide_set_signature(s);
2275
        }
2276
    }
2277

    
2278
    ide_if[0].cmd = val;
2279
    ide_if[1].cmd = val;
2280
}
2281

    
2282
static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2283
{
2284
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2285
    uint8_t *p;
2286

    
2287
    p = s->data_ptr;
2288
    *(uint16_t *)p = le16_to_cpu(val);
2289
    p += 2;
2290
    s->data_ptr = p;
2291
    if (p >= s->data_end)
2292
        s->end_transfer_func(s);
2293
}
2294

    
2295
static uint32_t ide_data_readw(void *opaque, uint32_t addr)
2296
{
2297
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2298
    uint8_t *p;
2299
    int ret;
2300
    p = s->data_ptr;
2301
    ret = cpu_to_le16(*(uint16_t *)p);
2302
    p += 2;
2303
    s->data_ptr = p;
2304
    if (p >= s->data_end)
2305
        s->end_transfer_func(s);
2306
    return ret;
2307
}
2308

    
2309
static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2310
{
2311
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2312
    uint8_t *p;
2313

    
2314
    p = s->data_ptr;
2315
    *(uint32_t *)p = le32_to_cpu(val);
2316
    p += 4;
2317
    s->data_ptr = p;
2318
    if (p >= s->data_end)
2319
        s->end_transfer_func(s);
2320
}
2321

    
2322
static uint32_t ide_data_readl(void *opaque, uint32_t addr)
2323
{
2324
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2325
    uint8_t *p;
2326
    int ret;
2327
    
2328
    p = s->data_ptr;
2329
    ret = cpu_to_le32(*(uint32_t *)p);
2330
    p += 4;
2331
    s->data_ptr = p;
2332
    if (p >= s->data_end)
2333
        s->end_transfer_func(s);
2334
    return ret;
2335
}
2336

    
2337
static void ide_dummy_transfer_stop(IDEState *s)
2338
{
2339
    s->data_ptr = s->io_buffer;
2340
    s->data_end = s->io_buffer;
2341
    s->io_buffer[0] = 0xff;
2342
    s->io_buffer[1] = 0xff;
2343
    s->io_buffer[2] = 0xff;
2344
    s->io_buffer[3] = 0xff;
2345
}
2346

    
2347
static void ide_reset(IDEState *s)
2348
{
2349
    if (s->is_cf)
2350
        s->mult_sectors = 0;
2351
    else
2352
        s->mult_sectors = MAX_MULT_SECTORS;
2353
    s->cur_drive = s;
2354
    s->select = 0xa0;
2355
    s->status = READY_STAT;
2356
    ide_set_signature(s);
2357
    /* init the transfer handler so that 0xffff is returned on data
2358
       accesses */
2359
    s->end_transfer_func = ide_dummy_transfer_stop;
2360
    ide_dummy_transfer_stop(s);
2361
    s->media_changed = 0;
2362
}
2363

    
2364
struct partition {
2365
        uint8_t boot_ind;                /* 0x80 - active */
2366
        uint8_t head;                /* starting head */
2367
        uint8_t sector;                /* starting sector */
2368
        uint8_t cyl;                /* starting cylinder */
2369
        uint8_t sys_ind;                /* What partition type */
2370
        uint8_t end_head;                /* end head */
2371
        uint8_t end_sector;        /* end sector */
2372
        uint8_t end_cyl;                /* end cylinder */
2373
        uint32_t start_sect;        /* starting sector counting from 0 */
2374
        uint32_t nr_sects;                /* nr of sectors in partition */
2375
} __attribute__((packed));
2376

    
2377
/* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
2378
static int guess_disk_lchs(IDEState *s, 
2379
                           int *pcylinders, int *pheads, int *psectors)
2380
{
2381
    uint8_t buf[512];
2382
    int ret, i, heads, sectors, cylinders;
2383
    struct partition *p;
2384
    uint32_t nr_sects;
2385

    
2386
    ret = bdrv_read(s->bs, 0, buf, 1);
2387
    if (ret < 0)
2388
        return -1;
2389
    /* test msdos magic */
2390
    if (buf[510] != 0x55 || buf[511] != 0xaa)
2391
        return -1;
2392
    for(i = 0; i < 4; i++) {
2393
        p = ((struct partition *)(buf + 0x1be)) + i;
2394
        nr_sects = le32_to_cpu(p->nr_sects);
2395
        if (nr_sects && p->end_head) {
2396
            /* We make the assumption that the partition terminates on
2397
               a cylinder boundary */
2398
            heads = p->end_head + 1;
2399
            sectors = p->end_sector & 63;
2400
            if (sectors == 0)
2401
                continue;
2402
            cylinders = s->nb_sectors / (heads * sectors);
2403
            if (cylinders < 1 || cylinders > 16383)
2404
                continue;
2405
            *pheads = heads;
2406
            *psectors = sectors;
2407
            *pcylinders = cylinders;
2408
#if 0
2409
            printf("guessed geometry: LCHS=%d %d %d\n", 
2410
                   cylinders, heads, sectors);
2411
#endif
2412
            return 0;
2413
        }
2414
    }
2415
    return -1;
2416
}
2417

    
2418
static void ide_init2(IDEState *ide_state,
2419
                      BlockDriverState *hd0, BlockDriverState *hd1,
2420
                      qemu_irq irq)
2421
{
2422
    IDEState *s;
2423
    static int drive_serial = 1;
2424
    int i, cylinders, heads, secs, translation, lba_detected = 0;
2425
    int64_t nb_sectors;
2426

    
2427
    for(i = 0; i < 2; i++) {
2428
        s = ide_state + i;
2429
        if (i == 0)
2430
            s->bs = hd0;
2431
        else
2432
            s->bs = hd1;
2433
        if (s->bs) {
2434
            bdrv_get_geometry(s->bs, &nb_sectors);
2435
            s->nb_sectors = nb_sectors;
2436
            /* if a geometry hint is available, use it */
2437
            bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
2438
            translation = bdrv_get_translation_hint(s->bs);
2439
            if (cylinders != 0) {
2440
                s->cylinders = cylinders;
2441
                s->heads = heads;
2442
                s->sectors = secs;
2443
            } else {
2444
                if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
2445
                    if (heads > 16) {
2446
                        /* if heads > 16, it means that a BIOS LBA
2447
                           translation was active, so the default
2448
                           hardware geometry is OK */
2449
                        lba_detected = 1;
2450
                        goto default_geometry;
2451
                    } else {
2452
                        s->cylinders = cylinders;
2453
                        s->heads = heads;
2454
                        s->sectors = secs;
2455
                        /* disable any translation to be in sync with
2456
                           the logical geometry */
2457
                        if (translation == BIOS_ATA_TRANSLATION_AUTO) {
2458
                            bdrv_set_translation_hint(s->bs,
2459
                                                      BIOS_ATA_TRANSLATION_NONE);
2460
                        }
2461
                    }
2462
                } else {
2463
                default_geometry:
2464
                    /* if no geometry, use a standard physical disk geometry */
2465
                    cylinders = nb_sectors / (16 * 63);
2466
                    if (cylinders > 16383)
2467
                        cylinders = 16383;
2468
                    else if (cylinders < 2)
2469
                        cylinders = 2;
2470
                    s->cylinders = cylinders;
2471
                    s->heads = 16;
2472
                    s->sectors = 63;
2473
                    if ((lba_detected == 1) && (translation == BIOS_ATA_TRANSLATION_AUTO)) {
2474
                      if ((s->cylinders * s->heads) <= 131072) {
2475
                        bdrv_set_translation_hint(s->bs,
2476
                                                  BIOS_ATA_TRANSLATION_LARGE);
2477
                      } else {
2478
                        bdrv_set_translation_hint(s->bs,
2479
                                                  BIOS_ATA_TRANSLATION_LBA);
2480
                      }
2481
                    }
2482
                }
2483
                bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
2484
            }
2485
            if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
2486
                s->is_cdrom = 1;
2487
                bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
2488
            }
2489
        }
2490
        s->drive_serial = drive_serial++;
2491
        s->irq = irq;
2492
        s->sector_write_timer = qemu_new_timer(vm_clock, 
2493
                                               ide_sector_write_timer_cb, s);
2494
        ide_reset(s);
2495
    }
2496
}
2497

    
2498
static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
2499
{
2500
    register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
2501
    register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
2502
    if (iobase2) {
2503
        register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
2504
        register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
2505
    }
2506
    
2507
    /* data ports */
2508
    register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
2509
    register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
2510
    register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
2511
    register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
2512
}
2513

    
2514
/* save per IDE drive data */
2515
static void ide_save(QEMUFile* f, IDEState *s)
2516
{
2517
    qemu_put_be32s(f, &s->mult_sectors);
2518
    qemu_put_be32s(f, &s->identify_set);
2519
    if (s->identify_set) {
2520
        qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2521
    }
2522
    qemu_put_8s(f, &s->feature);
2523
    qemu_put_8s(f, &s->error);
2524
    qemu_put_be32s(f, &s->nsector);
2525
    qemu_put_8s(f, &s->sector);
2526
    qemu_put_8s(f, &s->lcyl);
2527
    qemu_put_8s(f, &s->hcyl);
2528
    qemu_put_8s(f, &s->hob_feature);
2529
    qemu_put_8s(f, &s->hob_nsector);
2530
    qemu_put_8s(f, &s->hob_sector);
2531
    qemu_put_8s(f, &s->hob_lcyl);
2532
    qemu_put_8s(f, &s->hob_hcyl);
2533
    qemu_put_8s(f, &s->select);
2534
    qemu_put_8s(f, &s->status);
2535
    qemu_put_8s(f, &s->lba48);
2536

    
2537
    qemu_put_8s(f, &s->sense_key);
2538
    qemu_put_8s(f, &s->asc);
2539
    /* XXX: if a transfer is pending, we do not save it yet */
2540
}
2541

    
2542
/* load per IDE drive data */
2543
static void ide_load(QEMUFile* f, IDEState *s)
2544
{
2545
    qemu_get_be32s(f, &s->mult_sectors);
2546
    qemu_get_be32s(f, &s->identify_set);
2547
    if (s->identify_set) {
2548
        qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2549
    }
2550
    qemu_get_8s(f, &s->feature);
2551
    qemu_get_8s(f, &s->error);
2552
    qemu_get_be32s(f, &s->nsector);
2553
    qemu_get_8s(f, &s->sector);
2554
    qemu_get_8s(f, &s->lcyl);
2555
    qemu_get_8s(f, &s->hcyl);
2556
    qemu_get_8s(f, &s->hob_feature);
2557
    qemu_get_8s(f, &s->hob_nsector);
2558
    qemu_get_8s(f, &s->hob_sector);
2559
    qemu_get_8s(f, &s->hob_lcyl);
2560
    qemu_get_8s(f, &s->hob_hcyl);
2561
    qemu_get_8s(f, &s->select);
2562
    qemu_get_8s(f, &s->status);
2563
    qemu_get_8s(f, &s->lba48);
2564

    
2565
    qemu_get_8s(f, &s->sense_key);
2566
    qemu_get_8s(f, &s->asc);
2567
    /* XXX: if a transfer is pending, we do not save it yet */
2568
}
2569

    
2570
/***********************************************************/
2571
/* ISA IDE definitions */
2572

    
2573
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
2574
                  BlockDriverState *hd0, BlockDriverState *hd1)
2575
{
2576
    IDEState *ide_state;
2577

    
2578
    ide_state = qemu_mallocz(sizeof(IDEState) * 2);
2579
    if (!ide_state)
2580
        return;
2581
    
2582
    ide_init2(ide_state, hd0, hd1, irq);
2583
    ide_init_ioport(ide_state, iobase, iobase2);
2584
}
2585

    
2586
/***********************************************************/
2587
/* PCI IDE definitions */
2588

    
2589
static void cmd646_update_irq(PCIIDEState *d);
2590

    
2591
static void ide_map(PCIDevice *pci_dev, int region_num, 
2592
                    uint32_t addr, uint32_t size, int type)
2593
{
2594
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2595
    IDEState *ide_state;
2596

    
2597
    if (region_num <= 3) {
2598
        ide_state = &d->ide_if[(region_num >> 1) * 2];
2599
        if (region_num & 1) {
2600
            register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
2601
            register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
2602
        } else {
2603
            register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
2604
            register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
2605

    
2606
            /* data ports */
2607
            register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
2608
            register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
2609
            register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
2610
            register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
2611
        }
2612
    }
2613
}
2614

    
2615
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
2616
{
2617
    BMDMAState *bm = s->bmdma;
2618
    if(!bm)
2619
        return;
2620
    bm->ide_if = s;
2621
    bm->dma_cb = dma_cb;
2622
    bm->cur_prd_last = 0;
2623
    bm->cur_prd_addr = 0;
2624
    bm->cur_prd_len = 0;
2625
    if (bm->status & BM_STATUS_DMAING) {
2626
        bm->dma_cb(bm, 0);
2627
    }
2628
}
2629

    
2630
static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2631
{
2632
    BMDMAState *bm = opaque;
2633
#ifdef DEBUG_IDE
2634
    printf("%s: 0x%08x\n", __func__, val);
2635
#endif
2636
    if (!(val & BM_CMD_START)) {
2637
        /* XXX: do it better */
2638
        if (bm->status & BM_STATUS_DMAING) {
2639
            bm->status &= ~BM_STATUS_DMAING;
2640
            /* cancel DMA request */
2641
            bm->ide_if = NULL;
2642
            bm->dma_cb = NULL;
2643
            if (bm->aiocb) {
2644
#ifdef DEBUG_AIO
2645
                printf("aio_cancel\n");
2646
#endif
2647
                bdrv_aio_cancel(bm->aiocb);
2648
                bm->aiocb = NULL;
2649
            }
2650
        }
2651
        bm->cmd = val & 0x09;
2652
    } else {
2653
        if (!(bm->status & BM_STATUS_DMAING)) {
2654
            bm->status |= BM_STATUS_DMAING;
2655
            /* start dma transfer if possible */
2656
            if (bm->dma_cb)
2657
                bm->dma_cb(bm, 0);
2658
        }
2659
        bm->cmd = val & 0x09;
2660
    }
2661
}
2662

    
2663
static uint32_t bmdma_readb(void *opaque, uint32_t addr)
2664
{
2665
    BMDMAState *bm = opaque;
2666
    PCIIDEState *pci_dev;
2667
    uint32_t val;
2668
    
2669
    switch(addr & 3) {
2670
    case 0: 
2671
        val = bm->cmd;
2672
        break;
2673
    case 1:
2674
        pci_dev = bm->pci_dev;
2675
        if (pci_dev->type == IDE_TYPE_CMD646) {
2676
            val = pci_dev->dev.config[MRDMODE];
2677
        } else {
2678
            val = 0xff;
2679
        }
2680
        break;
2681
    case 2:
2682
        val = bm->status;
2683
        break;
2684
    case 3:
2685
        pci_dev = bm->pci_dev;
2686
        if (pci_dev->type == IDE_TYPE_CMD646) {
2687
            if (bm == &pci_dev->bmdma[0])
2688
                val = pci_dev->dev.config[UDIDETCR0];
2689
            else
2690
                val = pci_dev->dev.config[UDIDETCR1];
2691
        } else {
2692
            val = 0xff;
2693
        }
2694
        break;
2695
    default:
2696
        val = 0xff;
2697
        break;
2698
    }
2699
#ifdef DEBUG_IDE
2700
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
2701
#endif
2702
    return val;
2703
}
2704

    
2705
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
2706
{
2707
    BMDMAState *bm = opaque;
2708
    PCIIDEState *pci_dev;
2709
#ifdef DEBUG_IDE
2710
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
2711
#endif
2712
    switch(addr & 3) {
2713
    case 1:
2714
        pci_dev = bm->pci_dev;
2715
        if (pci_dev->type == IDE_TYPE_CMD646) {
2716
            pci_dev->dev.config[MRDMODE] = 
2717
                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
2718
            cmd646_update_irq(pci_dev);
2719
        }
2720
        break;
2721
    case 2:
2722
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2723
        break;
2724
    case 3:
2725
        pci_dev = bm->pci_dev;
2726
        if (pci_dev->type == IDE_TYPE_CMD646) {
2727
            if (bm == &pci_dev->bmdma[0])
2728
                pci_dev->dev.config[UDIDETCR0] = val;
2729
            else
2730
                pci_dev->dev.config[UDIDETCR1] = val;
2731
        }
2732
        break;
2733
    }
2734
}
2735

    
2736
static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2737
{
2738
    BMDMAState *bm = opaque;
2739
    uint32_t val;
2740
    val = bm->addr;
2741
#ifdef DEBUG_IDE
2742
    printf("%s: 0x%08x\n", __func__, val);
2743
#endif
2744
    return val;
2745
}
2746

    
2747
static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2748
{
2749
    BMDMAState *bm = opaque;
2750
#ifdef DEBUG_IDE
2751
    printf("%s: 0x%08x\n", __func__, val);
2752
#endif
2753
    bm->addr = val & ~3;
2754
    bm->cur_addr = bm->addr;
2755
}
2756

    
2757
static void bmdma_map(PCIDevice *pci_dev, int region_num, 
2758
                    uint32_t addr, uint32_t size, int type)
2759
{
2760
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2761
    int i;
2762

    
2763
    for(i = 0;i < 2; i++) {
2764
        BMDMAState *bm = &d->bmdma[i];
2765
        d->ide_if[2 * i].bmdma = bm;
2766
        d->ide_if[2 * i + 1].bmdma = bm;
2767
        bm->pci_dev = (PCIIDEState *)pci_dev;
2768

    
2769
        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2770

    
2771
        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
2772
        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
2773

    
2774
        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2775
        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2776
        addr += 8;
2777
    }
2778
}
2779

    
2780
/* XXX: call it also when the MRDMODE is changed from the PCI config
2781
   registers */
2782
static void cmd646_update_irq(PCIIDEState *d)
2783
{
2784
    int pci_level;
2785
    pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
2786
                 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
2787
        ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
2788
         !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
2789
    qemu_set_irq(d->dev.irq[0], pci_level);
2790
}
2791

    
2792
/* the PCI irq level is the logical OR of the two channels */
2793
static void cmd646_set_irq(void *opaque, int channel, int level)
2794
{
2795
    PCIIDEState *d = opaque;
2796
    int irq_mask;
2797

    
2798
    irq_mask = MRDMODE_INTR_CH0 << channel;
2799
    if (level)
2800
        d->dev.config[MRDMODE] |= irq_mask;
2801
    else
2802
        d->dev.config[MRDMODE] &= ~irq_mask;
2803
    cmd646_update_irq(d);
2804
}
2805

    
2806
/* CMD646 PCI IDE controller */
2807
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
2808
                         int secondary_ide_enabled)
2809
{
2810
    PCIIDEState *d;
2811
    uint8_t *pci_conf;
2812
    int i;
2813
    qemu_irq *irq;
2814

    
2815
    d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE", 
2816
                                           sizeof(PCIIDEState),
2817
                                           -1, 
2818
                                           NULL, NULL);
2819
    d->type = IDE_TYPE_CMD646;
2820
    pci_conf = d->dev.config;
2821
    pci_conf[0x00] = 0x95; // CMD646
2822
    pci_conf[0x01] = 0x10;
2823
    pci_conf[0x02] = 0x46;
2824
    pci_conf[0x03] = 0x06;
2825

    
2826
    pci_conf[0x08] = 0x07; // IDE controller revision
2827
    pci_conf[0x09] = 0x8f; 
2828

    
2829
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2830
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2831
    pci_conf[0x0e] = 0x00; // header_type
2832
    
2833
    if (secondary_ide_enabled) {
2834
        /* XXX: if not enabled, really disable the seconday IDE controller */
2835
        pci_conf[0x51] = 0x80; /* enable IDE1 */
2836
    }
2837

    
2838
    pci_register_io_region((PCIDevice *)d, 0, 0x8, 
2839
                           PCI_ADDRESS_SPACE_IO, ide_map);
2840
    pci_register_io_region((PCIDevice *)d, 1, 0x4, 
2841
                           PCI_ADDRESS_SPACE_IO, ide_map);
2842
    pci_register_io_region((PCIDevice *)d, 2, 0x8, 
2843
                           PCI_ADDRESS_SPACE_IO, ide_map);
2844
    pci_register_io_region((PCIDevice *)d, 3, 0x4, 
2845
                           PCI_ADDRESS_SPACE_IO, ide_map);
2846
    pci_register_io_region((PCIDevice *)d, 4, 0x10, 
2847
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2848

    
2849
    pci_conf[0x3d] = 0x01; // interrupt on pin 1
2850
    
2851
    for(i = 0; i < 4; i++)
2852
        d->ide_if[i].pci_dev = (PCIDevice *)d;
2853

    
2854
    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
2855
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
2856
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
2857
}
2858

    
2859
static void pci_ide_save(QEMUFile* f, void *opaque)
2860
{
2861
    PCIIDEState *d = opaque;
2862
    int i;
2863

    
2864
    pci_device_save(&d->dev, f);
2865

    
2866
    for(i = 0; i < 2; i++) {
2867
        BMDMAState *bm = &d->bmdma[i];
2868
        qemu_put_8s(f, &bm->cmd);
2869
        qemu_put_8s(f, &bm->status);
2870
        qemu_put_be32s(f, &bm->addr);
2871
        /* XXX: if a transfer is pending, we do not save it yet */
2872
    }
2873

    
2874
    /* per IDE interface data */
2875
    for(i = 0; i < 2; i++) {
2876
        IDEState *s = &d->ide_if[i * 2];
2877
        uint8_t drive1_selected;
2878
        qemu_put_8s(f, &s->cmd);
2879
        drive1_selected = (s->cur_drive != s);
2880
        qemu_put_8s(f, &drive1_selected);
2881
    }
2882

    
2883
    /* per IDE drive data */
2884
    for(i = 0; i < 4; i++) {
2885
        ide_save(f, &d->ide_if[i]);
2886
    }
2887
}
2888

    
2889
static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
2890
{
2891
    PCIIDEState *d = opaque;
2892
    int ret, i;
2893

    
2894
    if (version_id != 1)
2895
        return -EINVAL;
2896
    ret = pci_device_load(&d->dev, f);
2897
    if (ret < 0)
2898
        return ret;
2899

    
2900
    for(i = 0; i < 2; i++) {
2901
        BMDMAState *bm = &d->bmdma[i];
2902
        qemu_get_8s(f, &bm->cmd);
2903
        qemu_get_8s(f, &bm->status);
2904
        qemu_get_be32s(f, &bm->addr);
2905
        /* XXX: if a transfer is pending, we do not save it yet */
2906
    }
2907

    
2908
    /* per IDE interface data */
2909
    for(i = 0; i < 2; i++) {
2910
        IDEState *s = &d->ide_if[i * 2];
2911
        uint8_t drive1_selected;
2912
        qemu_get_8s(f, &s->cmd);
2913
        qemu_get_8s(f, &drive1_selected);
2914
        s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)];
2915
    }
2916

    
2917
    /* per IDE drive data */
2918
    for(i = 0; i < 4; i++) {
2919
        ide_load(f, &d->ide_if[i]);
2920
    }
2921
    return 0;
2922
}
2923

    
2924
static void piix3_reset(PCIIDEState *d)
2925
{
2926
    uint8_t *pci_conf = d->dev.config;
2927

    
2928
    pci_conf[0x04] = 0x00;
2929
    pci_conf[0x05] = 0x00;
2930
    pci_conf[0x06] = 0x80; /* FBC */
2931
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
2932
    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
2933
}
2934

    
2935
/* hd_table must contain 4 block drivers */
2936
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2937
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2938
                        qemu_irq *pic)
2939
{
2940
    PCIIDEState *d;
2941
    uint8_t *pci_conf;
2942
    
2943
    /* register a function 1 of PIIX3 */
2944
    d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE", 
2945
                                           sizeof(PCIIDEState),
2946
                                           devfn,
2947
                                           NULL, NULL);
2948
    d->type = IDE_TYPE_PIIX3;
2949

    
2950
    pci_conf = d->dev.config;
2951
    pci_conf[0x00] = 0x86; // Intel
2952
    pci_conf[0x01] = 0x80;
2953
    pci_conf[0x02] = 0x10;
2954
    pci_conf[0x03] = 0x70;
2955
    pci_conf[0x09] = 0x80; // legacy ATA mode
2956
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2957
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2958
    pci_conf[0x0e] = 0x00; // header_type
2959

    
2960
    piix3_reset(d);
2961

    
2962
    pci_register_io_region((PCIDevice *)d, 4, 0x10, 
2963
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2964

    
2965
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2966
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2967
    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2968
    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2969

    
2970
    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2971
}
2972

    
2973
/* hd_table must contain 4 block drivers */
2974
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
2975
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2976
                        qemu_irq *pic)
2977
{
2978
    PCIIDEState *d;
2979
    uint8_t *pci_conf;
2980

    
2981
    /* register a function 1 of PIIX4 */
2982
    d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
2983
                                           sizeof(PCIIDEState),
2984
                                           devfn,
2985
                                           NULL, NULL);
2986
    d->type = IDE_TYPE_PIIX4;
2987

    
2988
    pci_conf = d->dev.config;
2989
    pci_conf[0x00] = 0x86; // Intel
2990
    pci_conf[0x01] = 0x80;
2991
    pci_conf[0x02] = 0x11;
2992
    pci_conf[0x03] = 0x71;
2993
    pci_conf[0x09] = 0x80; // legacy ATA mode
2994
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2995
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2996
    pci_conf[0x0e] = 0x00; // header_type
2997

    
2998
    piix3_reset(d);
2999

    
3000
    pci_register_io_region((PCIDevice *)d, 4, 0x10,
3001
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
3002

    
3003
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
3004
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
3005
    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
3006
    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
3007

    
3008
    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
3009
}
3010

    
3011
/***********************************************************/
3012
/* MacIO based PowerPC IDE */
3013

    
3014
/* PowerMac IDE memory IO */
3015
static void pmac_ide_writeb (void *opaque,
3016
                             target_phys_addr_t addr, uint32_t val)
3017
{
3018
    addr = (addr & 0xFFF) >> 4; 
3019
    switch (addr) {
3020
    case 1 ... 7:
3021
        ide_ioport_write(opaque, addr, val);
3022
        break;
3023
    case 8:
3024
    case 22:
3025
        ide_cmd_write(opaque, 0, val);
3026
        break;
3027
    default:
3028
        break;
3029
    }
3030
}
3031

    
3032
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
3033
{
3034
    uint8_t retval;
3035

    
3036
    addr = (addr & 0xFFF) >> 4;
3037
    switch (addr) {
3038
    case 1 ... 7:
3039
        retval = ide_ioport_read(opaque, addr);
3040
        break;
3041
    case 8:
3042
    case 22:
3043
        retval = ide_status_read(opaque, 0);
3044
        break;
3045
    default:
3046
        retval = 0xFF;
3047
        break;
3048
    }
3049
    return retval;
3050
}
3051

    
3052
static void pmac_ide_writew (void *opaque,
3053
                             target_phys_addr_t addr, uint32_t val)
3054
{
3055
    addr = (addr & 0xFFF) >> 4; 
3056
#ifdef TARGET_WORDS_BIGENDIAN
3057
    val = bswap16(val);
3058
#endif
3059
    if (addr == 0) {
3060
        ide_data_writew(opaque, 0, val);
3061
    }
3062
}
3063

    
3064
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
3065
{
3066
    uint16_t retval;
3067

    
3068
    addr = (addr & 0xFFF) >> 4; 
3069
    if (addr == 0) {
3070
        retval = ide_data_readw(opaque, 0);
3071
    } else {
3072
        retval = 0xFFFF;
3073
    }
3074
#ifdef TARGET_WORDS_BIGENDIAN
3075
    retval = bswap16(retval);
3076
#endif
3077
    return retval;
3078
}
3079

    
3080
static void pmac_ide_writel (void *opaque,
3081
                             target_phys_addr_t addr, uint32_t val)
3082
{
3083
    addr = (addr & 0xFFF) >> 4; 
3084
#ifdef TARGET_WORDS_BIGENDIAN
3085
    val = bswap32(val);
3086
#endif
3087
    if (addr == 0) {
3088
        ide_data_writel(opaque, 0, val);
3089
    }
3090
}
3091

    
3092
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
3093
{
3094
    uint32_t retval;
3095

    
3096
    addr = (addr & 0xFFF) >> 4; 
3097
    if (addr == 0) {
3098
        retval = ide_data_readl(opaque, 0);
3099
    } else {
3100
        retval = 0xFFFFFFFF;
3101
    }
3102
#ifdef TARGET_WORDS_BIGENDIAN
3103
    retval = bswap32(retval);
3104
#endif
3105
    return retval;
3106
}
3107

    
3108
static CPUWriteMemoryFunc *pmac_ide_write[] = {
3109
    pmac_ide_writeb,
3110
    pmac_ide_writew,
3111
    pmac_ide_writel,
3112
};
3113

    
3114
static CPUReadMemoryFunc *pmac_ide_read[] = {
3115
    pmac_ide_readb,
3116
    pmac_ide_readw,
3117
    pmac_ide_readl,
3118
};
3119

    
3120
/* hd_table must contain 4 block drivers */
3121
/* PowerMac uses memory mapped registers, not I/O. Return the memory
3122
   I/O index to access the ide. */
3123
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
3124
{
3125
    IDEState *ide_if;
3126
    int pmac_ide_memory;
3127

    
3128
    ide_if = qemu_mallocz(sizeof(IDEState) * 2);
3129
    ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
3130
    
3131
    pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
3132
                                             pmac_ide_write, &ide_if[0]);
3133
    return pmac_ide_memory;
3134
}
3135

    
3136
/***********************************************************/
3137
/* CF-ATA Microdrive */
3138

    
3139
#define METADATA_SIZE        0x20
3140

    
3141
/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */
3142
struct md_s {
3143
    IDEState ide[2];
3144
    struct pcmcia_card_s card;
3145
    uint32_t attr_base;
3146
    uint32_t io_base;
3147

    
3148
    /* Card state */
3149
    uint8_t opt;
3150
    uint8_t stat;
3151
    uint8_t pins;
3152

    
3153
    uint8_t ctrl;
3154
    uint16_t io;
3155
    int cycle;
3156
};
3157

    
3158
/* Register bitfields */
3159
enum md_opt {
3160
    OPT_MODE_MMAP        = 0,
3161
    OPT_MODE_IOMAP16        = 1,
3162
    OPT_MODE_IOMAP1        = 2,
3163
    OPT_MODE_IOMAP2        = 3,
3164
    OPT_MODE                = 0x3f,
3165
    OPT_LEVIREQ                = 0x40,
3166
    OPT_SRESET                = 0x80,
3167
};
3168
enum md_cstat {
3169
    STAT_INT                = 0x02,
3170
    STAT_PWRDWN                = 0x04,
3171
    STAT_XE                = 0x10,
3172
    STAT_IOIS8                = 0x20,
3173
    STAT_SIGCHG                = 0x40,
3174
    STAT_CHANGED        = 0x80,
3175
};
3176
enum md_pins {
3177
    PINS_MRDY                = 0x02,
3178
    PINS_CRDY                = 0x20,
3179
};
3180
enum md_ctrl {
3181
    CTRL_IEN                = 0x02,
3182
    CTRL_SRST                = 0x04,
3183
};
3184

    
3185
static inline void md_interrupt_update(struct md_s *s)
3186
{
3187
    if (!s->card.slot)
3188
        return;
3189

    
3190
    qemu_set_irq(s->card.slot->irq,
3191
                    !(s->stat & STAT_INT) &&        /* Inverted */
3192
                    !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
3193
                    !(s->opt & OPT_SRESET));
3194
}
3195

    
3196
static void md_set_irq(void *opaque, int irq, int level)
3197
{
3198
    struct md_s *s = (struct md_s *) opaque;
3199
    if (level)
3200
        s->stat |= STAT_INT;
3201
    else
3202
        s->stat &= ~STAT_INT;
3203

    
3204
    md_interrupt_update(s);
3205
}
3206

    
3207
static void md_reset(struct md_s *s)
3208
{
3209
    s->opt = OPT_MODE_MMAP;
3210
    s->stat = 0;
3211
    s->pins = 0;
3212
    s->cycle = 0;
3213
    s->ctrl = 0;
3214
    ide_reset(s->ide);
3215
}
3216

    
3217
static uint8_t md_attr_read(void *opaque, uint32_t at)
3218
{
3219
    struct md_s *s = (struct md_s *) opaque;
3220
    if (at < s->attr_base) {
3221
        if (at < s->card.cis_len)
3222
            return s->card.cis[at];
3223
        else
3224
            return 0x00;
3225
    }
3226

    
3227
    at -= s->attr_base;
3228

    
3229
    switch (at) {
3230
    case 0x00:        /* Configuration Option Register */
3231
        return s->opt;
3232
    case 0x02:        /* Card Configuration Status Register */
3233
        if (s->ctrl & CTRL_IEN)
3234
            return s->stat & ~STAT_INT;
3235
        else
3236
            return s->stat;
3237
    case 0x04:        /* Pin Replacement Register */
3238
        return (s->pins & PINS_CRDY) | 0x0c;
3239
    case 0x06:        /* Socket and Copy Register */
3240
        return 0x00;
3241
#ifdef VERBOSE
3242
    default:
3243
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3244
#endif
3245
    }
3246

    
3247
    return 0;
3248
}
3249

    
3250
static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
3251
{
3252
    struct md_s *s = (struct md_s *) opaque;
3253
    at -= s->attr_base;
3254

    
3255
    switch (at) {
3256
    case 0x00:        /* Configuration Option Register */
3257
        s->opt = value & 0xcf;
3258
        if (value & OPT_SRESET)
3259
            md_reset(s);
3260
        md_interrupt_update(s);
3261
        break;
3262
    case 0x02:        /* Card Configuration Status Register */
3263
        if ((s->stat ^ value) & STAT_PWRDWN)
3264
            s->pins |= PINS_CRDY;
3265
        s->stat &= 0x82;
3266
        s->stat |= value & 0x74;
3267
        md_interrupt_update(s);
3268
        /* Word 170 in Identify Device must be equal to STAT_XE */
3269
        break;
3270
    case 0x04:        /* Pin Replacement Register */
3271
        s->pins &= PINS_CRDY;
3272
        s->pins |= value & PINS_MRDY;
3273
        break;
3274
    case 0x06:        /* Socket and Copy Register */
3275
        break;
3276
    default:
3277
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3278
    }
3279
}
3280

    
3281
static uint16_t md_common_read(void *opaque, uint32_t at)
3282
{
3283
    struct md_s *s = (struct md_s *) opaque;
3284
    uint16_t ret;
3285
    at -= s->io_base;
3286

    
3287
    switch (s->opt & OPT_MODE) {
3288
    case OPT_MODE_MMAP:
3289
        if ((at & ~0x3ff) == 0x400)
3290
            at = 0;
3291
        break;
3292
    case OPT_MODE_IOMAP16:
3293
        at &= 0xf;
3294
        break;
3295
    case OPT_MODE_IOMAP1:
3296
        if ((at & ~0xf) == 0x3f0)
3297
            at -= 0x3e8;
3298
        else if ((at & ~0xf) == 0x1f0)
3299
            at -= 0x1f0;
3300
        break;
3301
    case OPT_MODE_IOMAP2:
3302
        if ((at & ~0xf) == 0x370)
3303
            at -= 0x368;
3304
        else if ((at & ~0xf) == 0x170)
3305
            at -= 0x170;
3306
    }
3307

    
3308
    switch (at) {
3309
    case 0x0:        /* Even RD Data */
3310
    case 0x8:
3311
        return ide_data_readw(s->ide, 0);
3312

    
3313
        /* TODO: 8-bit accesses */
3314
        if (s->cycle)
3315
            ret = s->io >> 8;
3316
        else {
3317
            s->io = ide_data_readw(s->ide, 0);
3318
            ret = s->io & 0xff;
3319
        }
3320
        s->cycle = !s->cycle;
3321
        return ret;
3322
    case 0x9:        /* Odd RD Data */
3323
        return s->io >> 8;
3324
    case 0xd:        /* Error */
3325
        return ide_ioport_read(s->ide, 0x1);
3326
    case 0xe:        /* Alternate Status */
3327
        if (s->ide->cur_drive->bs)
3328
            return s->ide->cur_drive->status;
3329
        else
3330
            return 0;
3331
    case 0xf:        /* Device Address */
3332
        return 0xc2 | ((~s->ide->select << 2) & 0x3c);
3333
    default:
3334
        return ide_ioport_read(s->ide, at);
3335
    }
3336

    
3337
    return 0;
3338
}
3339

    
3340
static void md_common_write(void *opaque, uint32_t at, uint16_t value)
3341
{
3342
    struct md_s *s = (struct md_s *) opaque;
3343
    at -= s->io_base;
3344

    
3345
    switch (s->opt & OPT_MODE) {
3346
    case OPT_MODE_MMAP:
3347
        if ((at & ~0x3ff) == 0x400)
3348
            at = 0;
3349
        break;
3350
    case OPT_MODE_IOMAP16:
3351
        at &= 0xf;
3352
        break;
3353
    case OPT_MODE_IOMAP1:
3354
        if ((at & ~0xf) == 0x3f0)
3355
            at -= 0x3e8;
3356
        else if ((at & ~0xf) == 0x1f0)
3357
            at -= 0x1f0;
3358
        break;
3359
    case OPT_MODE_IOMAP2:
3360
        if ((at & ~0xf) == 0x370)
3361
            at -= 0x368;
3362
        else if ((at & ~0xf) == 0x170)
3363
            at -= 0x170;
3364
    }
3365

    
3366
    switch (at) {
3367
    case 0x0:        /* Even WR Data */
3368
    case 0x8:
3369
        ide_data_writew(s->ide, 0, value);
3370
        break;
3371

    
3372
        /* TODO: 8-bit accesses */
3373
        if (s->cycle)
3374
            ide_data_writew(s->ide, 0, s->io | (value << 8));
3375
        else
3376
            s->io = value & 0xff;
3377
        s->cycle = !s->cycle;
3378
        break;
3379
    case 0x9:
3380
        s->io = value & 0xff;
3381
        s->cycle = !s->cycle;
3382
        break;
3383
    case 0xd:        /* Features */
3384
        ide_ioport_write(s->ide, 0x1, value);
3385
        break;
3386
    case 0xe:        /* Device Control */
3387
        s->ctrl = value;
3388
        if (value & CTRL_SRST)
3389
            md_reset(s);
3390
        md_interrupt_update(s);
3391
        break;
3392
    default:
3393
        if (s->stat & STAT_PWRDWN) {
3394
            s->pins |= PINS_CRDY;
3395
            s->stat &= ~STAT_PWRDWN;
3396
        }
3397
        ide_ioport_write(s->ide, at, value);
3398
    }
3399
}
3400

    
3401
static void md_save(QEMUFile *f, void *opaque)
3402
{
3403
    struct md_s *s = (struct md_s *) opaque;
3404
    int i;
3405
    uint8_t drive1_selected;
3406

    
3407
    qemu_put_8s(f, &s->opt);
3408
    qemu_put_8s(f, &s->stat);
3409
    qemu_put_8s(f, &s->pins);
3410

    
3411
    qemu_put_8s(f, &s->ctrl);
3412
    qemu_put_be16s(f, &s->io);
3413
    qemu_put_byte(f, s->cycle);
3414

    
3415
    drive1_selected = (s->ide->cur_drive != s->ide);
3416
    qemu_put_8s(f, &s->ide->cmd);
3417
    qemu_put_8s(f, &drive1_selected);
3418

    
3419
    for (i = 0; i < 2; i ++)
3420
        ide_save(f, &s->ide[i]);
3421
}
3422

    
3423
static int md_load(QEMUFile *f, void *opaque, int version_id)
3424
{
3425
    struct md_s *s = (struct md_s *) opaque;
3426
    int i;
3427
    uint8_t drive1_selected;
3428

    
3429
    qemu_get_8s(f, &s->opt);
3430
    qemu_get_8s(f, &s->stat);
3431
    qemu_get_8s(f, &s->pins);
3432

    
3433
    qemu_get_8s(f, &s->ctrl);
3434
    qemu_get_be16s(f, &s->io);
3435
    s->cycle = qemu_get_byte(f);
3436

    
3437
    qemu_get_8s(f, &s->ide->cmd);
3438
    qemu_get_8s(f, &drive1_selected);
3439
    s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
3440

    
3441
    for (i = 0; i < 2; i ++)
3442
        ide_load(f, &s->ide[i]);
3443

    
3444
    return 0;
3445
}
3446

    
3447
static int md_iid = 0;
3448

    
3449
static const uint8_t dscm1xxxx_cis[0x14a] = {
3450
    [0x000] = CISTPL_DEVICE,        /* 5V Device Information */
3451
    [0x002] = 0x03,                /* Tuple length = 4 bytes */
3452
    [0x004] = 0xdb,                /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3453
    [0x006] = 0x01,                /* Size = 2K bytes */
3454
    [0x008] = CISTPL_ENDMARK,
3455

    
3456
    [0x00a] = CISTPL_DEVICE_OC,        /* Additional Device Information */
3457
    [0x00c] = 0x04,                /* Tuple length = 4 byest */
3458
    [0x00e] = 0x03,                /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
3459
    [0x010] = 0xdb,                /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3460
    [0x012] = 0x01,                /* Size = 2K bytes */
3461
    [0x014] = CISTPL_ENDMARK,
3462

    
3463
    [0x016] = CISTPL_JEDEC_C,        /* JEDEC ID */
3464
    [0x018] = 0x02,                /* Tuple length = 2 bytes */
3465
    [0x01a] = 0xdf,                /* PC Card ATA with no Vpp required */
3466
    [0x01c] = 0x01,
3467

    
3468
    [0x01e] = CISTPL_MANFID,        /* Manufacture ID */
3469
    [0x020] = 0x04,                /* Tuple length = 4 bytes */
3470
    [0x022] = 0xa4,                /* TPLMID_MANF = 00a4 (IBM) */
3471
    [0x024] = 0x00,
3472
    [0x026] = 0x00,                /* PLMID_CARD = 0000 */
3473
    [0x028] = 0x00,
3474

    
3475
    [0x02a] = CISTPL_VERS_1,        /* Level 1 Version */
3476
    [0x02c] = 0x12,                /* Tuple length = 23 bytes */
3477
    [0x02e] = 0x04,                /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
3478
    [0x030] = 0x01,                /* Minor Version = 1 */
3479
    [0x032] = 'I',
3480
    [0x034] = 'B',
3481
    [0x036] = 'M',
3482
    [0x038] = 0x00,
3483
    [0x03a] = 'm',
3484
    [0x03c] = 'i',
3485
    [0x03e] = 'c',
3486
    [0x040] = 'r',
3487
    [0x042] = 'o',
3488
    [0x044] = 'd',
3489
    [0x046] = 'r',
3490
    [0x048] = 'i',
3491
    [0x04a] = 'v',
3492
    [0x04c] = 'e',
3493
    [0x04e] = 0x00,
3494
    [0x050] = CISTPL_ENDMARK,
3495

    
3496
    [0x052] = CISTPL_FUNCID,        /* Function ID */
3497
    [0x054] = 0x02,                /* Tuple length = 2 bytes */
3498
    [0x056] = 0x04,                /* TPLFID_FUNCTION = Fixed Disk */
3499
    [0x058] = 0x01,                /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
3500

    
3501
    [0x05a] = CISTPL_FUNCE,        /* Function Extension */
3502
    [0x05c] = 0x02,                /* Tuple length = 2 bytes */
3503
    [0x05e] = 0x01,                /* TPLFE_TYPE = Disk Device Interface */
3504
    [0x060] = 0x01,                /* TPLFE_DATA = PC Card ATA Interface */
3505

    
3506
    [0x062] = CISTPL_FUNCE,        /* Function Extension */
3507
    [0x064] = 0x03,                /* Tuple length = 3 bytes */
3508
    [0x066] = 0x02,                /* TPLFE_TYPE = Basic PC Card ATA Interface */
3509
    [0x068] = 0x08,                /* TPLFE_DATA: Rotating, Unique, Single */
3510
    [0x06a] = 0x0f,                /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
3511

    
3512
    [0x06c] = CISTPL_CONFIG,        /* Configuration */
3513
    [0x06e] = 0x05,                /* Tuple length = 5 bytes */
3514
    [0x070] = 0x01,                /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
3515
    [0x072] = 0x07,                /* TPCC_LAST = 7 */
3516
    [0x074] = 0x00,                /* TPCC_RADR = 0200 */
3517
    [0x076] = 0x02,
3518
    [0x078] = 0x0f,                /* TPCC_RMSK = 200, 202, 204, 206 */
3519

    
3520
    [0x07a] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3521
    [0x07c] = 0x0b,                /* Tuple length = 11 bytes */
3522
    [0x07e] = 0xc0,                /* TPCE_INDX = Memory Mode, Default, Iface */
3523
    [0x080] = 0xc0,                /* TPCE_IF = Memory, no BVDs, no WP, READY */
3524
    [0x082] = 0xa1,                /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
3525
    [0x084] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3526
    [0x086] = 0x55,                /* NomV: 5.0 V */
3527
    [0x088] = 0x4d,                /* MinV: 4.5 V */
3528
    [0x08a] = 0x5d,                /* MaxV: 5.5 V */
3529
    [0x08c] = 0x4e,                /* Peakl: 450 mA */
3530
    [0x08e] = 0x08,                /* TPCE_MS = 1 window, 1 byte, Host address */
3531
    [0x090] = 0x00,                /* Window descriptor: Window length = 0 */
3532
    [0x092] = 0x20,                /* TPCE_MI: support power down mode, RW */
3533

    
3534
    [0x094] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3535
    [0x096] = 0x06,                /* Tuple length = 6 bytes */
3536
    [0x098] = 0x00,                /* TPCE_INDX = Memory Mode, no Default */
3537
    [0x09a] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3538
    [0x09c] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3539
    [0x09e] = 0xb5,                /* NomV: 3.3 V */
3540
    [0x0a0] = 0x1e,
3541
    [0x0a2] = 0x3e,                /* Peakl: 350 mA */
3542

    
3543
    [0x0a4] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3544
    [0x0a6] = 0x0d,                /* Tuple length = 13 bytes */
3545
    [0x0a8] = 0xc1,                /* TPCE_INDX = I/O and Memory Mode, Default */
3546
    [0x0aa] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3547
    [0x0ac] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3548
    [0x0ae] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3549
    [0x0b0] = 0x55,                /* NomV: 5.0 V */
3550
    [0x0b2] = 0x4d,                /* MinV: 4.5 V */
3551
    [0x0b4] = 0x5d,                /* MaxV: 5.5 V */
3552
    [0x0b6] = 0x4e,                /* Peakl: 450 mA */
3553
    [0x0b8] = 0x64,                /* TPCE_IO = 16-byte boundary, 16/8 accesses */
3554
    [0x0ba] = 0xf0,                /* TPCE_IR =  MASK, Level, Pulse, Share */
3555
    [0x0bc] = 0xff,                /* IRQ0..IRQ7 supported */
3556
    [0x0be] = 0xff,                /* IRQ8..IRQ15 supported */
3557
    [0x0c0] = 0x20,                /* TPCE_MI = support power down mode */
3558

    
3559
    [0x0c2] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3560
    [0x0c4] = 0x06,                /* Tuple length = 6 bytes */
3561
    [0x0c6] = 0x01,                /* TPCE_INDX = I/O and Memory Mode */
3562
    [0x0c8] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3563
    [0x0ca] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3564
    [0x0cc] = 0xb5,                /* NomV: 3.3 V */
3565
    [0x0ce] = 0x1e,
3566
    [0x0d0] = 0x3e,                /* Peakl: 350 mA */
3567

    
3568
    [0x0d2] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3569
    [0x0d4] = 0x12,                /* Tuple length = 18 bytes */
3570
    [0x0d6] = 0xc2,                /* TPCE_INDX = I/O Primary Mode */
3571
    [0x0d8] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3572
    [0x0da] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3573
    [0x0dc] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3574
    [0x0de] = 0x55,                /* NomV: 5.0 V */
3575
    [0x0e0] = 0x4d,                /* MinV: 4.5 V */
3576
    [0x0e2] = 0x5d,                /* MaxV: 5.5 V */
3577
    [0x0e4] = 0x4e,                /* Peakl: 450 mA */
3578
    [0x0e6] = 0xea,                /* TPCE_IO = 1K boundary, 16/8 access, Range */
3579
    [0x0e8] = 0x61,                /* Range: 2 fields, 2 bytes addr, 1 byte len */
3580
    [0x0ea] = 0xf0,                /* Field 1 address = 0x01f0 */
3581
    [0x0ec] = 0x01,
3582
    [0x0ee] = 0x07,                /* Address block length = 8 */
3583
    [0x0f0] = 0xf6,                /* Field 2 address = 0x03f6 */
3584
    [0x0f2] = 0x03,
3585
    [0x0f4] = 0x01,                /* Address block length = 2 */
3586
    [0x0f6] = 0xee,                /* TPCE_IR = IRQ E, Level, Pulse, Share */
3587
    [0x0f8] = 0x20,                /* TPCE_MI = support power down mode */
3588

    
3589
    [0x0fa] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3590
    [0x0fc] = 0x06,                /* Tuple length = 6 bytes */
3591
    [0x0fe] = 0x02,                /* TPCE_INDX = I/O Primary Mode, no Default */
3592
    [0x100] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3593
    [0x102] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3594
    [0x104] = 0xb5,                /* NomV: 3.3 V */
3595
    [0x106] = 0x1e,
3596
    [0x108] = 0x3e,                /* Peakl: 350 mA */
3597

    
3598
    [0x10a] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3599
    [0x10c] = 0x12,                /* Tuple length = 18 bytes */
3600
    [0x10e] = 0xc3,                /* TPCE_INDX = I/O Secondary Mode, Default */
3601
    [0x110] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3602
    [0x112] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3603
    [0x114] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3604
    [0x116] = 0x55,                /* NomV: 5.0 V */
3605
    [0x118] = 0x4d,                /* MinV: 4.5 V */
3606
    [0x11a] = 0x5d,                /* MaxV: 5.5 V */
3607
    [0x11c] = 0x4e,                /* Peakl: 450 mA */
3608
    [0x11e] = 0xea,                /* TPCE_IO = 1K boundary, 16/8 access, Range */
3609
    [0x120] = 0x61,                /* Range: 2 fields, 2 byte addr, 1 byte len */
3610
    [0x122] = 0x70,                /* Field 1 address = 0x0170 */
3611
    [0x124] = 0x01,
3612
    [0x126] = 0x07,                /* Address block length = 8 */
3613
    [0x128] = 0x76,                /* Field 2 address = 0x0376 */
3614
    [0x12a] = 0x03,
3615
    [0x12c] = 0x01,                /* Address block length = 2 */
3616
    [0x12e] = 0xee,                /* TPCE_IR = IRQ E, Level, Pulse, Share */
3617
    [0x130] = 0x20,                /* TPCE_MI = support power down mode */
3618

    
3619
    [0x132] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3620
    [0x134] = 0x06,                /* Tuple length = 6 bytes */
3621
    [0x136] = 0x03,                /* TPCE_INDX = I/O Secondary Mode */
3622
    [0x138] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3623
    [0x13a] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3624
    [0x13c] = 0xb5,                /* NomV: 3.3 V */
3625
    [0x13e] = 0x1e,
3626
    [0x140] = 0x3e,                /* Peakl: 350 mA */
3627

    
3628
    [0x142] = CISTPL_NO_LINK,        /* No Link */
3629
    [0x144] = 0x00,                /* Tuple length = 0 bytes */
3630

    
3631
    [0x146] = CISTPL_END,        /* Tuple End */
3632
};
3633

    
3634
static int dscm1xxxx_attach(void *opaque)
3635
{
3636
    struct md_s *md = (struct md_s *) opaque;
3637
    md->card.attr_read = md_attr_read;
3638
    md->card.attr_write = md_attr_write;
3639
    md->card.common_read = md_common_read;
3640
    md->card.common_write = md_common_write;
3641
    md->card.io_read = md_common_read;
3642
    md->card.io_write = md_common_write;
3643

    
3644
    md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
3645
    md->io_base = 0x0;
3646

    
3647
    md_reset(md);
3648
    md_interrupt_update(md);
3649

    
3650
    md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3651
    return 0;
3652
}
3653

    
3654
static int dscm1xxxx_detach(void *opaque)
3655
{
3656
    struct md_s *md = (struct md_s *) opaque;
3657
    md_reset(md);
3658
    return 0;
3659
}
3660

    
3661
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
3662
{
3663
    struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
3664
    md->card.state = md;
3665
    md->card.attach = dscm1xxxx_attach;
3666
    md->card.detach = dscm1xxxx_detach;
3667
    md->card.cis = dscm1xxxx_cis;
3668
    md->card.cis_len = sizeof(dscm1xxxx_cis);
3669

    
3670
    ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
3671
    md->ide->is_cf = 1;
3672
    md->ide->mdata_size = METADATA_SIZE;
3673
    md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
3674

    
3675
    register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md);
3676

    
3677
    return &md->card;
3678
}