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/*
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* QEMU TCX Frame buffer
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "pixel_ops.h" |
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|
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#define MAXX 1024 |
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#define MAXY 768 |
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#define TCX_DAC_NREGS 16 |
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#define TCX_THC_NREGS_8 0x081c |
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#define TCX_THC_NREGS_24 0x1000 |
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#define TCX_TEC_NREGS 0x1000 |
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|
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typedef struct TCXState { |
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target_phys_addr_t addr; |
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DisplayState *ds; |
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uint8_t *vram; |
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uint32_t *vram24, *cplane; |
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ram_addr_t vram_offset, vram24_offset, cplane_offset; |
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uint16_t width, height, depth; |
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uint8_t r[256], g[256], b[256]; |
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uint32_t palette[256];
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uint8_t dac_index, dac_state; |
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} TCXState; |
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|
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static void tcx_screen_dump(void *opaque, const char *filename); |
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static void tcx24_screen_dump(void *opaque, const char *filename); |
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static void tcx_invalidate_display(void *opaque); |
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static void tcx24_invalidate_display(void *opaque); |
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|
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static void update_palette_entries(TCXState *s, int start, int end) |
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{ |
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int i;
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for(i = start; i < end; i++) {
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switch(s->ds->depth) {
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default:
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case 8: |
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s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
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break;
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case 15: |
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if (s->ds->bgr)
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s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]); |
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else
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s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
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break;
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case 16: |
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if (s->ds->bgr)
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s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]); |
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else
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s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
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break;
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case 32: |
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if (s->ds->bgr)
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s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
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else
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s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
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break;
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} |
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} |
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if (s->depth == 24) |
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tcx24_invalidate_display(s); |
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else
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tcx_invalidate_display(s); |
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} |
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|
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static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint32_t *p = (uint32_t *)d; |
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|
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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|
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static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint16_t *p = (uint16_t *)d; |
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|
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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|
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static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*d++ = s1->palette[val]; |
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} |
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} |
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|
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static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width, |
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const uint32_t *cplane,
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const uint32_t *s24)
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{ |
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int x;
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uint8_t val; |
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uint32_t *p = (uint32_t *)d; |
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uint32_t dval; |
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|
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for(x = 0; x < width; x++, s++, s24++) { |
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if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct |
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dval = bswap32(*s24) & 0x00ffffff;
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} else {
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val = *s; |
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dval = s1->palette[val]; |
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} |
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*p++ = dval; |
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} |
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} |
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static inline int check_dirty(TCXState *ts, ram_addr_t page, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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int ret;
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unsigned int off; |
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ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
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for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
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ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
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ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
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} |
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return ret;
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} |
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static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
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ram_addr_t page_max, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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VGA_DIRTY_FLAG); |
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page_min -= ts->vram_offset; |
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page_max -= ts->vram_offset; |
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cpu_physical_memory_reset_dirty(page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG); |
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cpu_physical_memory_reset_dirty(cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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VGA_DIRTY_FLAG); |
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} |
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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VGA... */
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static void tcx_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
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if (ts->ds->depth == 0) |
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return;
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page = ts->vram_offset; |
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y_start = -1;
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page_min = 0xffffffff;
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page_max = 0;
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d = ts->ds->data; |
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s = ts->vram; |
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dd = ts->ds->linesize; |
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ds = 1024;
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switch (ts->ds->depth) {
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case 32: |
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f = tcx_draw_line32; |
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break;
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case 15: |
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case 16: |
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f = tcx_draw_line16; |
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break;
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default:
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case 8: |
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f = tcx_draw_line8; |
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break;
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case 0: |
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return;
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} |
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
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if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_min <= page_max) {
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cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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VGA_DIRTY_FLAG); |
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} |
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} |
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|
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static void tcx24_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max, cpage, page24; |
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int y, y_start, dd, ds;
|
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uint8_t *d, *s; |
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uint32_t *cptr, *s24; |
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|
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if (ts->ds->depth != 32) |
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return;
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page = ts->vram_offset; |
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page24 = ts->vram24_offset; |
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cpage = ts->cplane_offset; |
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y_start = -1;
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page_min = 0xffffffff;
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page_max = 0;
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d = ts->ds->data; |
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s = ts->vram; |
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s24 = ts->vram24; |
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cptr = ts->cplane; |
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dd = ts->ds->linesize; |
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ds = 1024;
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|
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
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if (check_dirty(ts, page, page24, cpage)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
314 |
d += dd * 4;
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s += ds * 4;
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cptr += ds * 4;
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s24 += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_min <= page_max) {
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reset_dirty(ts, page_min, page_max, page24, cpage); |
328 |
} |
329 |
} |
330 |
|
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static void tcx_invalidate_display(void *opaque) |
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{ |
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TCXState *s = opaque; |
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int i;
|
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|
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for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
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cpu_physical_memory_set_dirty(s->vram_offset + i); |
338 |
} |
339 |
} |
340 |
|
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static void tcx24_invalidate_display(void *opaque) |
342 |
{ |
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TCXState *s = opaque; |
344 |
int i;
|
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|
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tcx_invalidate_display(s); |
347 |
for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
348 |
cpu_physical_memory_set_dirty(s->vram24_offset + i); |
349 |
cpu_physical_memory_set_dirty(s->cplane_offset + i); |
350 |
} |
351 |
} |
352 |
|
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static void tcx_save(QEMUFile *f, void *opaque) |
354 |
{ |
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TCXState *s = opaque; |
356 |
|
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qemu_put_be16s(f, (uint16_t *)&s->height); |
358 |
qemu_put_be16s(f, (uint16_t *)&s->width); |
359 |
qemu_put_be16s(f, (uint16_t *)&s->depth); |
360 |
qemu_put_buffer(f, s->r, 256);
|
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qemu_put_buffer(f, s->g, 256);
|
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qemu_put_buffer(f, s->b, 256);
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qemu_put_8s(f, &s->dac_index); |
364 |
qemu_put_8s(f, &s->dac_state); |
365 |
} |
366 |
|
367 |
static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
368 |
{ |
369 |
TCXState *s = opaque; |
370 |
uint32_t dummy; |
371 |
|
372 |
if (version_id != 3 && version_id != 4) |
373 |
return -EINVAL;
|
374 |
|
375 |
if (version_id == 3) { |
376 |
qemu_get_be32s(f, (uint32_t *)&dummy); |
377 |
qemu_get_be32s(f, (uint32_t *)&dummy); |
378 |
qemu_get_be32s(f, (uint32_t *)&dummy); |
379 |
} |
380 |
qemu_get_be16s(f, (uint16_t *)&s->height); |
381 |
qemu_get_be16s(f, (uint16_t *)&s->width); |
382 |
qemu_get_be16s(f, (uint16_t *)&s->depth); |
383 |
qemu_get_buffer(f, s->r, 256);
|
384 |
qemu_get_buffer(f, s->g, 256);
|
385 |
qemu_get_buffer(f, s->b, 256);
|
386 |
qemu_get_8s(f, &s->dac_index); |
387 |
qemu_get_8s(f, &s->dac_state); |
388 |
update_palette_entries(s, 0, 256); |
389 |
if (s->depth == 24) |
390 |
tcx24_invalidate_display(s); |
391 |
else
|
392 |
tcx_invalidate_display(s); |
393 |
|
394 |
return 0; |
395 |
} |
396 |
|
397 |
static void tcx_reset(void *opaque) |
398 |
{ |
399 |
TCXState *s = opaque; |
400 |
|
401 |
/* Initialize palette */
|
402 |
memset(s->r, 0, 256); |
403 |
memset(s->g, 0, 256); |
404 |
memset(s->b, 0, 256); |
405 |
s->r[255] = s->g[255] = s->b[255] = 255; |
406 |
update_palette_entries(s, 0, 256); |
407 |
memset(s->vram, 0, MAXX*MAXY);
|
408 |
cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
409 |
MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
410 |
s->dac_index = 0;
|
411 |
s->dac_state = 0;
|
412 |
} |
413 |
|
414 |
static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
415 |
{ |
416 |
return 0; |
417 |
} |
418 |
|
419 |
static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
420 |
{ |
421 |
TCXState *s = opaque; |
422 |
uint32_t saddr; |
423 |
|
424 |
saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; |
425 |
switch (saddr) {
|
426 |
case 0: |
427 |
s->dac_index = val >> 24;
|
428 |
s->dac_state = 0;
|
429 |
break;
|
430 |
case 1: |
431 |
switch (s->dac_state) {
|
432 |
case 0: |
433 |
s->r[s->dac_index] = val >> 24;
|
434 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
435 |
s->dac_state++; |
436 |
break;
|
437 |
case 1: |
438 |
s->g[s->dac_index] = val >> 24;
|
439 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
440 |
s->dac_state++; |
441 |
break;
|
442 |
case 2: |
443 |
s->b[s->dac_index] = val >> 24;
|
444 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
445 |
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
446 |
default:
|
447 |
s->dac_state = 0;
|
448 |
break;
|
449 |
} |
450 |
break;
|
451 |
default:
|
452 |
break;
|
453 |
} |
454 |
return;
|
455 |
} |
456 |
|
457 |
static CPUReadMemoryFunc *tcx_dac_read[3] = { |
458 |
tcx_dac_readl, |
459 |
tcx_dac_readl, |
460 |
tcx_dac_readl, |
461 |
}; |
462 |
|
463 |
static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
464 |
tcx_dac_writel, |
465 |
tcx_dac_writel, |
466 |
tcx_dac_writel, |
467 |
}; |
468 |
|
469 |
static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
470 |
{ |
471 |
return 0; |
472 |
} |
473 |
|
474 |
static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
475 |
uint32_t val) |
476 |
{ |
477 |
} |
478 |
|
479 |
static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
480 |
tcx_dummy_readl, |
481 |
tcx_dummy_readl, |
482 |
tcx_dummy_readl, |
483 |
}; |
484 |
|
485 |
static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
486 |
tcx_dummy_writel, |
487 |
tcx_dummy_writel, |
488 |
tcx_dummy_writel, |
489 |
}; |
490 |
|
491 |
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
492 |
unsigned long vram_offset, int vram_size, int width, int height, |
493 |
int depth)
|
494 |
{ |
495 |
TCXState *s; |
496 |
int io_memory, dummy_memory;
|
497 |
int size;
|
498 |
|
499 |
s = qemu_mallocz(sizeof(TCXState));
|
500 |
if (!s)
|
501 |
return;
|
502 |
s->ds = ds; |
503 |
s->addr = addr; |
504 |
s->vram_offset = vram_offset; |
505 |
s->width = width; |
506 |
s->height = height; |
507 |
s->depth = depth; |
508 |
|
509 |
// 8-bit plane
|
510 |
s->vram = vram_base; |
511 |
size = vram_size; |
512 |
cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
|
513 |
vram_offset += size; |
514 |
vram_base += size; |
515 |
|
516 |
io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
|
517 |
cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, io_memory);
|
518 |
|
519 |
dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
|
520 |
s); |
521 |
cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
|
522 |
dummy_memory); |
523 |
if (depth == 24) { |
524 |
// 24-bit plane
|
525 |
size = vram_size * 4;
|
526 |
s->vram24 = (uint32_t *)vram_base; |
527 |
s->vram24_offset = vram_offset; |
528 |
cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
|
529 |
vram_offset += size; |
530 |
vram_base += size; |
531 |
|
532 |
// Control plane
|
533 |
size = vram_size * 4;
|
534 |
s->cplane = (uint32_t *)vram_base; |
535 |
s->cplane_offset = vram_offset; |
536 |
cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
|
537 |
graphic_console_init(s->ds, tcx24_update_display, |
538 |
tcx24_invalidate_display, tcx24_screen_dump, s); |
539 |
} else {
|
540 |
cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
|
541 |
dummy_memory); |
542 |
graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display, |
543 |
tcx_screen_dump, s); |
544 |
} |
545 |
// NetBSD writes here even with 8-bit display
|
546 |
cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
|
547 |
dummy_memory); |
548 |
|
549 |
register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
550 |
qemu_register_reset(tcx_reset, s); |
551 |
tcx_reset(s); |
552 |
dpy_resize(s->ds, width, height); |
553 |
} |
554 |
|
555 |
static void tcx_screen_dump(void *opaque, const char *filename) |
556 |
{ |
557 |
TCXState *s = opaque; |
558 |
FILE *f; |
559 |
uint8_t *d, *d1, v; |
560 |
int y, x;
|
561 |
|
562 |
f = fopen(filename, "wb");
|
563 |
if (!f)
|
564 |
return;
|
565 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
566 |
d1 = s->vram; |
567 |
for(y = 0; y < s->height; y++) { |
568 |
d = d1; |
569 |
for(x = 0; x < s->width; x++) { |
570 |
v = *d; |
571 |
fputc(s->r[v], f); |
572 |
fputc(s->g[v], f); |
573 |
fputc(s->b[v], f); |
574 |
d++; |
575 |
} |
576 |
d1 += MAXX; |
577 |
} |
578 |
fclose(f); |
579 |
return;
|
580 |
} |
581 |
|
582 |
static void tcx24_screen_dump(void *opaque, const char *filename) |
583 |
{ |
584 |
TCXState *s = opaque; |
585 |
FILE *f; |
586 |
uint8_t *d, *d1, v; |
587 |
uint32_t *s24, *cptr, dval; |
588 |
int y, x;
|
589 |
|
590 |
f = fopen(filename, "wb");
|
591 |
if (!f)
|
592 |
return;
|
593 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
594 |
d1 = s->vram; |
595 |
s24 = s->vram24; |
596 |
cptr = s->cplane; |
597 |
for(y = 0; y < s->height; y++) { |
598 |
d = d1; |
599 |
for(x = 0; x < s->width; x++, d++, s24++) { |
600 |
if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
601 |
dval = *s24 & 0x00ffffff;
|
602 |
fputc((dval >> 16) & 0xff, f); |
603 |
fputc((dval >> 8) & 0xff, f); |
604 |
fputc(dval & 0xff, f);
|
605 |
} else {
|
606 |
v = *d; |
607 |
fputc(s->r[v], f); |
608 |
fputc(s->g[v], f); |
609 |
fputc(s->b[v], f); |
610 |
} |
611 |
} |
612 |
d1 += MAXX; |
613 |
} |
614 |
fclose(f); |
615 |
return;
|
616 |
} |