root / hw / vmware_vga.c @ be20f9e9
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/*
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* QEMU VMware-SVGA "chipset".
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*
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* Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "loader.h" |
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#include "console.h" |
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#include "pci.h" |
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#include "vmware_vga.h" |
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#define VERBOSE
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#undef DIRECT_VRAM
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#define HW_RECT_ACCEL
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#define HW_FILL_ACCEL
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#define HW_MOUSE_ACCEL
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# include "vga_int.h" |
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struct vmsvga_state_s {
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VGACommonState vga; |
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int width;
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int height;
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int invalidated;
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int depth;
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int bypp;
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int enable;
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int config;
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struct {
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int id;
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int x;
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int y;
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int on;
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} cursor; |
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int index;
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int scratch_size;
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uint32_t *scratch; |
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int new_width;
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int new_height;
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uint32_t guest; |
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uint32_t svgaid; |
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uint32_t wred; |
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uint32_t wgreen; |
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uint32_t wblue; |
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int syncing;
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int fb_size;
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MemoryRegion fifo_ram; |
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uint8_t *fifo_ptr; |
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unsigned int fifo_size; |
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union {
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uint32_t *fifo; |
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struct __attribute__((__packed__)) {
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uint32_t min; |
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uint32_t max; |
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uint32_t next_cmd; |
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uint32_t stop; |
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/* Add registers here when adding capabilities. */
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uint32_t fifo[0];
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} *cmd; |
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}; |
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#define REDRAW_FIFO_LEN 512 |
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struct vmsvga_rect_s {
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int x, y, w, h;
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} redraw_fifo[REDRAW_FIFO_LEN]; |
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int redraw_fifo_first, redraw_fifo_last;
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}; |
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struct pci_vmsvga_state_s {
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PCIDevice card; |
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struct vmsvga_state_s chip;
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MemoryRegion io_bar; |
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}; |
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#define SVGA_MAGIC 0x900000UL |
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#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
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#define SVGA_ID_0 SVGA_MAKE_ID(0) |
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#define SVGA_ID_1 SVGA_MAKE_ID(1) |
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#define SVGA_ID_2 SVGA_MAKE_ID(2) |
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#define SVGA_LEGACY_BASE_PORT 0x4560 |
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#define SVGA_INDEX_PORT 0x0 |
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#define SVGA_VALUE_PORT 0x1 |
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#define SVGA_BIOS_PORT 0x2 |
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#define SVGA_VERSION_2
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#ifdef SVGA_VERSION_2
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# define SVGA_ID SVGA_ID_2
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 1 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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#else
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# define SVGA_ID SVGA_ID_1
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# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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# define SVGA_IO_MUL 4 |
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# define SVGA_FIFO_SIZE 0x10000 |
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# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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#endif
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enum {
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/* ID 0, 1 and 2 registers */
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SVGA_REG_ID = 0,
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SVGA_REG_ENABLE = 1,
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SVGA_REG_WIDTH = 2,
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SVGA_REG_HEIGHT = 3,
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SVGA_REG_MAX_WIDTH = 4,
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SVGA_REG_MAX_HEIGHT = 5,
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SVGA_REG_DEPTH = 6,
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SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
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SVGA_REG_PSEUDOCOLOR = 8,
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SVGA_REG_RED_MASK = 9,
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SVGA_REG_GREEN_MASK = 10,
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SVGA_REG_BLUE_MASK = 11,
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SVGA_REG_BYTES_PER_LINE = 12,
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SVGA_REG_FB_START = 13,
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SVGA_REG_FB_OFFSET = 14,
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SVGA_REG_VRAM_SIZE = 15,
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SVGA_REG_FB_SIZE = 16,
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/* ID 1 and 2 registers */
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SVGA_REG_CAPABILITIES = 17,
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SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
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SVGA_REG_MEM_SIZE = 19,
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SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
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SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
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SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
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SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
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SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
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SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
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SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
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SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
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SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
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SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
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SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
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SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
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SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
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SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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}; |
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#define SVGA_CAP_NONE 0 |
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#define SVGA_CAP_RECT_FILL (1 << 0) |
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#define SVGA_CAP_RECT_COPY (1 << 1) |
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#define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
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#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
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#define SVGA_CAP_RASTER_OP (1 << 4) |
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#define SVGA_CAP_CURSOR (1 << 5) |
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#define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
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#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
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#define SVGA_CAP_8BIT_EMULATION (1 << 8) |
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#define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
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#define SVGA_CAP_GLYPH (1 << 10) |
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#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
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#define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
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#define SVGA_CAP_ALPHA_BLEND (1 << 13) |
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#define SVGA_CAP_3D (1 << 14) |
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#define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
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#define SVGA_CAP_MULTIMON (1 << 16) |
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#define SVGA_CAP_PITCHLOCK (1 << 17) |
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/*
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* FIFO offsets (seen as an array of 32-bit words)
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*/
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enum {
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/*
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* The original defined FIFO offsets
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*/
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SVGA_FIFO_MIN = 0,
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SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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SVGA_FIFO_NEXT_CMD, |
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SVGA_FIFO_STOP, |
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/*
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* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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*/
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SVGA_FIFO_CAPABILITIES = 4,
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SVGA_FIFO_FLAGS, |
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SVGA_FIFO_FENCE, |
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SVGA_FIFO_3D_HWVERSION, |
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SVGA_FIFO_PITCHLOCK, |
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}; |
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#define SVGA_FIFO_CAP_NONE 0 |
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#define SVGA_FIFO_CAP_FENCE (1 << 0) |
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#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
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#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
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#define SVGA_FIFO_FLAG_NONE 0 |
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#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
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/* These values can probably be changed arbitrarily. */
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#define SVGA_SCRATCH_SIZE 0x8000 |
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#define SVGA_MAX_WIDTH 2360 |
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#define SVGA_MAX_HEIGHT 1770 |
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#ifdef VERBOSE
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# define GUEST_OS_BASE 0x5001 |
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static const char *vmsvga_guest_id[] = { |
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[0x00] = "Dos", |
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[0x01] = "Windows 3.1", |
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[0x02] = "Windows 95", |
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[0x03] = "Windows 98", |
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[0x04] = "Windows ME", |
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[0x05] = "Windows NT", |
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[0x06] = "Windows 2000", |
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[0x07] = "Linux", |
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[0x08] = "OS/2", |
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[0x09] = "an unknown OS", |
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[0x0a] = "BSD", |
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[0x0b] = "Whistler", |
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[0x0c] = "an unknown OS", |
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[0x0d] = "an unknown OS", |
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[0x0e] = "an unknown OS", |
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[0x0f] = "an unknown OS", |
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[0x10] = "an unknown OS", |
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[0x11] = "an unknown OS", |
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[0x12] = "an unknown OS", |
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[0x13] = "an unknown OS", |
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[0x14] = "an unknown OS", |
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[0x15] = "Windows 2003", |
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}; |
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#endif
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enum {
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SVGA_CMD_INVALID_CMD = 0,
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SVGA_CMD_UPDATE = 1,
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SVGA_CMD_RECT_FILL = 2,
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SVGA_CMD_RECT_COPY = 3,
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SVGA_CMD_DEFINE_BITMAP = 4,
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SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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SVGA_CMD_DEFINE_PIXMAP = 6,
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SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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SVGA_CMD_RECT_BITMAP_FILL = 8,
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SVGA_CMD_RECT_PIXMAP_FILL = 9,
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SVGA_CMD_RECT_BITMAP_COPY = 10,
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SVGA_CMD_RECT_PIXMAP_COPY = 11,
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SVGA_CMD_FREE_OBJECT = 12,
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SVGA_CMD_RECT_ROP_FILL = 13,
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SVGA_CMD_RECT_ROP_COPY = 14,
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SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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SVGA_CMD_DEFINE_CURSOR = 19,
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SVGA_CMD_DISPLAY_CURSOR = 20,
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SVGA_CMD_MOVE_CURSOR = 21,
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SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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SVGA_CMD_DRAW_GLYPH = 23,
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SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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SVGA_CMD_UPDATE_VERBOSE = 25,
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SVGA_CMD_SURFACE_FILL = 26,
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SVGA_CMD_SURFACE_COPY = 27,
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SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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SVGA_CMD_FRONT_ROP_FILL = 29,
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SVGA_CMD_FENCE = 30,
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}; |
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/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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enum {
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SVGA_CURSOR_ON_HIDE = 0,
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SVGA_CURSOR_ON_SHOW = 1,
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SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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}; |
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static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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#ifndef DIRECT_VRAM
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int line;
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int bypl;
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int width;
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int start;
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uint8_t *src; |
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uint8_t *dst; |
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if (x + w > s->width) {
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fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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__FUNCTION__, x, w); |
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x = MIN(x, s->width); |
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w = s->width - x; |
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} |
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if (y + h > s->height) {
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fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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__FUNCTION__, y, h); |
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y = MIN(y, s->height); |
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h = s->height - y; |
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} |
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line = h; |
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bypl = s->bypp * s->width; |
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width = s->bypp * w; |
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start = s->bypp * x + bypl * y; |
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src = s->vga.vram_ptr + start; |
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dst = ds_get_data(s->vga.ds) + start; |
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for (; line > 0; line --, src += bypl, dst += bypl) |
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memcpy(dst, src, width); |
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#endif
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dpy_update(s->vga.ds, x, y, w, h); |
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} |
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static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
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{ |
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#ifndef DIRECT_VRAM
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memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); |
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#endif
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dpy_update(s->vga.ds, 0, 0, s->width, s->height); |
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} |
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#ifdef DIRECT_VRAM
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# define vmsvga_update_rect_delayed vmsvga_update_rect
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#else
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static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
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int x, int y, int w, int h) |
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{ |
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struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
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s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
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rect->x = x; |
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rect->y = y; |
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rect->w = w; |
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rect->h = h; |
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} |
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#endif
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static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
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{ |
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struct vmsvga_rect_s *rect;
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if (s->invalidated) {
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s->redraw_fifo_first = s->redraw_fifo_last; |
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return;
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} |
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/* Overlapping region updates can be optimised out here - if someone
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* knows a smart algorithm to do that, please share. */
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while (s->redraw_fifo_first != s->redraw_fifo_last) {
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rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
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s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
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vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
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} |
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} |
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|
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#ifdef HW_RECT_ACCEL
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static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
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int x0, int y0, int x1, int y1, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
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# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypl = s->bypp * s->width;
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int width = s->bypp * w;
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int line = h;
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uint8_t *ptr[2];
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# ifdef DIRECT_VRAM
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if (s->ds->dpy_copy)
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qemu_console_copy(s->ds, x0, y0, x1, y1, w, h); |
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else
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# endif
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{ |
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if (y1 > y0) {
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ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
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ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
394 |
for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) |
395 |
memmove(ptr[1], ptr[0], width); |
396 |
} else {
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ptr[0] = vram + s->bypp * x0 + bypl * y0;
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ptr[1] = vram + s->bypp * x1 + bypl * y1;
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for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) |
400 |
memmove(ptr[1], ptr[0], width); |
401 |
} |
402 |
} |
403 |
|
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vmsvga_update_rect_delayed(s, x1, y1, w, h); |
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} |
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#endif
|
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|
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#ifdef HW_FILL_ACCEL
|
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static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
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uint32_t c, int x, int y, int w, int h) |
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{ |
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# ifdef DIRECT_VRAM
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uint8_t *vram = ds_get_data(s->ds); |
414 |
# else
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uint8_t *vram = s->vga.vram_ptr; |
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# endif
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int bypp = s->bypp;
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int bypl = bypp * s->width;
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int width = bypp * w;
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int line = h;
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int column;
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uint8_t *fst = vram + bypp * x + bypl * y; |
423 |
uint8_t *dst; |
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uint8_t *src; |
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uint8_t col[4];
|
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|
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# ifdef DIRECT_VRAM
|
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if (s->ds->dpy_fill)
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s->ds->dpy_fill(s->ds, x, y, w, h, c); |
430 |
else
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# endif
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{ |
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col[0] = c;
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col[1] = c >> 8; |
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col[2] = c >> 16; |
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col[3] = c >> 24; |
437 |
|
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if (line --) {
|
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dst = fst; |
440 |
src = col; |
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for (column = width; column > 0; column --) { |
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*(dst ++) = *(src ++); |
443 |
if (src - col == bypp)
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src = col; |
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} |
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dst = fst; |
447 |
for (; line > 0; line --) { |
448 |
dst += bypl; |
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memcpy(dst, fst, width); |
450 |
} |
451 |
} |
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} |
453 |
|
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vmsvga_update_rect_delayed(s, x, y, w, h); |
455 |
} |
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#endif
|
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|
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struct vmsvga_cursor_definition_s {
|
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int width;
|
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int height;
|
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int id;
|
462 |
int bpp;
|
463 |
int hot_x;
|
464 |
int hot_y;
|
465 |
uint32_t mask[1024];
|
466 |
uint32_t image[4096];
|
467 |
}; |
468 |
|
469 |
#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
470 |
#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
471 |
|
472 |
#ifdef HW_MOUSE_ACCEL
|
473 |
static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
474 |
struct vmsvga_cursor_definition_s *c)
|
475 |
{ |
476 |
QEMUCursor *qc; |
477 |
int i, pixels;
|
478 |
|
479 |
qc = cursor_alloc(c->width, c->height); |
480 |
qc->hot_x = c->hot_x; |
481 |
qc->hot_y = c->hot_y; |
482 |
switch (c->bpp) {
|
483 |
case 1: |
484 |
cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image, |
485 |
1, (void*)c->mask); |
486 |
#ifdef DEBUG
|
487 |
cursor_print_ascii_art(qc, "vmware/mono");
|
488 |
#endif
|
489 |
break;
|
490 |
case 32: |
491 |
/* fill alpha channel from mask, set color to zero */
|
492 |
cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask, |
493 |
1, (void*)c->mask); |
494 |
/* add in rgb values */
|
495 |
pixels = c->width * c->height; |
496 |
for (i = 0; i < pixels; i++) { |
497 |
qc->data[i] |= c->image[i] & 0xffffff;
|
498 |
} |
499 |
#ifdef DEBUG
|
500 |
cursor_print_ascii_art(qc, "vmware/32bit");
|
501 |
#endif
|
502 |
break;
|
503 |
default:
|
504 |
fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
505 |
__FUNCTION__, c->bpp); |
506 |
cursor_put(qc); |
507 |
qc = cursor_builtin_left_ptr(); |
508 |
} |
509 |
|
510 |
if (s->vga.ds->cursor_define)
|
511 |
s->vga.ds->cursor_define(qc); |
512 |
cursor_put(qc); |
513 |
} |
514 |
#endif
|
515 |
|
516 |
#define CMD(f) le32_to_cpu(s->cmd->f)
|
517 |
|
518 |
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) |
519 |
{ |
520 |
int num;
|
521 |
if (!s->config || !s->enable)
|
522 |
return 0; |
523 |
num = CMD(next_cmd) - CMD(stop); |
524 |
if (num < 0) |
525 |
num += CMD(max) - CMD(min); |
526 |
return num >> 2; |
527 |
} |
528 |
|
529 |
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
530 |
{ |
531 |
uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
532 |
s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
533 |
if (CMD(stop) >= CMD(max))
|
534 |
s->cmd->stop = s->cmd->min; |
535 |
return cmd;
|
536 |
} |
537 |
|
538 |
static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
539 |
{ |
540 |
return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
541 |
} |
542 |
|
543 |
static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
544 |
{ |
545 |
uint32_t cmd, colour; |
546 |
int args, len;
|
547 |
int x, y, dx, dy, width, height;
|
548 |
struct vmsvga_cursor_definition_s cursor;
|
549 |
uint32_t cmd_start; |
550 |
|
551 |
len = vmsvga_fifo_length(s); |
552 |
while (len > 0) { |
553 |
/* May need to go back to the start of the command if incomplete */
|
554 |
cmd_start = s->cmd->stop; |
555 |
|
556 |
switch (cmd = vmsvga_fifo_read(s)) {
|
557 |
case SVGA_CMD_UPDATE:
|
558 |
case SVGA_CMD_UPDATE_VERBOSE:
|
559 |
len -= 5;
|
560 |
if (len < 0) |
561 |
goto rewind;
|
562 |
|
563 |
x = vmsvga_fifo_read(s); |
564 |
y = vmsvga_fifo_read(s); |
565 |
width = vmsvga_fifo_read(s); |
566 |
height = vmsvga_fifo_read(s); |
567 |
vmsvga_update_rect_delayed(s, x, y, width, height); |
568 |
break;
|
569 |
|
570 |
case SVGA_CMD_RECT_FILL:
|
571 |
len -= 6;
|
572 |
if (len < 0) |
573 |
goto rewind;
|
574 |
|
575 |
colour = vmsvga_fifo_read(s); |
576 |
x = vmsvga_fifo_read(s); |
577 |
y = vmsvga_fifo_read(s); |
578 |
width = vmsvga_fifo_read(s); |
579 |
height = vmsvga_fifo_read(s); |
580 |
#ifdef HW_FILL_ACCEL
|
581 |
vmsvga_fill_rect(s, colour, x, y, width, height); |
582 |
break;
|
583 |
#else
|
584 |
args = 0;
|
585 |
goto badcmd;
|
586 |
#endif
|
587 |
|
588 |
case SVGA_CMD_RECT_COPY:
|
589 |
len -= 7;
|
590 |
if (len < 0) |
591 |
goto rewind;
|
592 |
|
593 |
x = vmsvga_fifo_read(s); |
594 |
y = vmsvga_fifo_read(s); |
595 |
dx = vmsvga_fifo_read(s); |
596 |
dy = vmsvga_fifo_read(s); |
597 |
width = vmsvga_fifo_read(s); |
598 |
height = vmsvga_fifo_read(s); |
599 |
#ifdef HW_RECT_ACCEL
|
600 |
vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
601 |
break;
|
602 |
#else
|
603 |
args = 0;
|
604 |
goto badcmd;
|
605 |
#endif
|
606 |
|
607 |
case SVGA_CMD_DEFINE_CURSOR:
|
608 |
len -= 8;
|
609 |
if (len < 0) |
610 |
goto rewind;
|
611 |
|
612 |
cursor.id = vmsvga_fifo_read(s); |
613 |
cursor.hot_x = vmsvga_fifo_read(s); |
614 |
cursor.hot_y = vmsvga_fifo_read(s); |
615 |
cursor.width = x = vmsvga_fifo_read(s); |
616 |
cursor.height = y = vmsvga_fifo_read(s); |
617 |
vmsvga_fifo_read(s); |
618 |
cursor.bpp = vmsvga_fifo_read(s); |
619 |
|
620 |
args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
621 |
if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || |
622 |
SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
|
623 |
goto badcmd;
|
624 |
|
625 |
len -= args; |
626 |
if (len < 0) |
627 |
goto rewind;
|
628 |
|
629 |
for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
630 |
cursor.mask[args] = vmsvga_fifo_read_raw(s); |
631 |
for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
632 |
cursor.image[args] = vmsvga_fifo_read_raw(s); |
633 |
#ifdef HW_MOUSE_ACCEL
|
634 |
vmsvga_cursor_define(s, &cursor); |
635 |
break;
|
636 |
#else
|
637 |
args = 0;
|
638 |
goto badcmd;
|
639 |
#endif
|
640 |
|
641 |
/*
|
642 |
* Other commands that we at least know the number of arguments
|
643 |
* for so we can avoid FIFO desync if driver uses them illegally.
|
644 |
*/
|
645 |
case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
646 |
len -= 6;
|
647 |
if (len < 0) |
648 |
goto rewind;
|
649 |
|
650 |
vmsvga_fifo_read(s); |
651 |
vmsvga_fifo_read(s); |
652 |
vmsvga_fifo_read(s); |
653 |
x = vmsvga_fifo_read(s); |
654 |
y = vmsvga_fifo_read(s); |
655 |
args = x * y; |
656 |
goto badcmd;
|
657 |
case SVGA_CMD_RECT_ROP_FILL:
|
658 |
args = 6;
|
659 |
goto badcmd;
|
660 |
case SVGA_CMD_RECT_ROP_COPY:
|
661 |
args = 7;
|
662 |
goto badcmd;
|
663 |
case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
664 |
len -= 4;
|
665 |
if (len < 0) |
666 |
goto rewind;
|
667 |
|
668 |
vmsvga_fifo_read(s); |
669 |
vmsvga_fifo_read(s); |
670 |
args = 7 + (vmsvga_fifo_read(s) >> 2); |
671 |
goto badcmd;
|
672 |
case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
673 |
args = 12;
|
674 |
goto badcmd;
|
675 |
|
676 |
/*
|
677 |
* Other commands that are not listed as depending on any
|
678 |
* CAPABILITIES bits, but are not described in the README either.
|
679 |
*/
|
680 |
case SVGA_CMD_SURFACE_FILL:
|
681 |
case SVGA_CMD_SURFACE_COPY:
|
682 |
case SVGA_CMD_FRONT_ROP_FILL:
|
683 |
case SVGA_CMD_FENCE:
|
684 |
case SVGA_CMD_INVALID_CMD:
|
685 |
break; /* Nop */ |
686 |
|
687 |
default:
|
688 |
args = 0;
|
689 |
badcmd:
|
690 |
len -= args; |
691 |
if (len < 0) |
692 |
goto rewind;
|
693 |
while (args --)
|
694 |
vmsvga_fifo_read(s); |
695 |
printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
696 |
__FUNCTION__, cmd); |
697 |
break;
|
698 |
|
699 |
rewind:
|
700 |
s->cmd->stop = cmd_start; |
701 |
break;
|
702 |
} |
703 |
} |
704 |
|
705 |
s->syncing = 0;
|
706 |
} |
707 |
|
708 |
static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
709 |
{ |
710 |
struct vmsvga_state_s *s = opaque;
|
711 |
return s->index;
|
712 |
} |
713 |
|
714 |
static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
715 |
{ |
716 |
struct vmsvga_state_s *s = opaque;
|
717 |
s->index = index; |
718 |
} |
719 |
|
720 |
static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
721 |
{ |
722 |
uint32_t caps; |
723 |
struct vmsvga_state_s *s = opaque;
|
724 |
switch (s->index) {
|
725 |
case SVGA_REG_ID:
|
726 |
return s->svgaid;
|
727 |
|
728 |
case SVGA_REG_ENABLE:
|
729 |
return s->enable;
|
730 |
|
731 |
case SVGA_REG_WIDTH:
|
732 |
return s->width;
|
733 |
|
734 |
case SVGA_REG_HEIGHT:
|
735 |
return s->height;
|
736 |
|
737 |
case SVGA_REG_MAX_WIDTH:
|
738 |
return SVGA_MAX_WIDTH;
|
739 |
|
740 |
case SVGA_REG_MAX_HEIGHT:
|
741 |
return SVGA_MAX_HEIGHT;
|
742 |
|
743 |
case SVGA_REG_DEPTH:
|
744 |
return s->depth;
|
745 |
|
746 |
case SVGA_REG_BITS_PER_PIXEL:
|
747 |
return (s->depth + 7) & ~7; |
748 |
|
749 |
case SVGA_REG_PSEUDOCOLOR:
|
750 |
return 0x0; |
751 |
|
752 |
case SVGA_REG_RED_MASK:
|
753 |
return s->wred;
|
754 |
case SVGA_REG_GREEN_MASK:
|
755 |
return s->wgreen;
|
756 |
case SVGA_REG_BLUE_MASK:
|
757 |
return s->wblue;
|
758 |
|
759 |
case SVGA_REG_BYTES_PER_LINE:
|
760 |
return ((s->depth + 7) >> 3) * s->new_width; |
761 |
|
762 |
case SVGA_REG_FB_START: {
|
763 |
struct pci_vmsvga_state_s *pci_vmsvga
|
764 |
= container_of(s, struct pci_vmsvga_state_s, chip);
|
765 |
return pci_get_bar_addr(&pci_vmsvga->card, 1); |
766 |
} |
767 |
|
768 |
case SVGA_REG_FB_OFFSET:
|
769 |
return 0x0; |
770 |
|
771 |
case SVGA_REG_VRAM_SIZE:
|
772 |
return s->vga.vram_size;
|
773 |
|
774 |
case SVGA_REG_FB_SIZE:
|
775 |
return s->fb_size;
|
776 |
|
777 |
case SVGA_REG_CAPABILITIES:
|
778 |
caps = SVGA_CAP_NONE; |
779 |
#ifdef HW_RECT_ACCEL
|
780 |
caps |= SVGA_CAP_RECT_COPY; |
781 |
#endif
|
782 |
#ifdef HW_FILL_ACCEL
|
783 |
caps |= SVGA_CAP_RECT_FILL; |
784 |
#endif
|
785 |
#ifdef HW_MOUSE_ACCEL
|
786 |
if (s->vga.ds->mouse_set)
|
787 |
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
788 |
SVGA_CAP_CURSOR_BYPASS; |
789 |
#endif
|
790 |
return caps;
|
791 |
|
792 |
case SVGA_REG_MEM_START: {
|
793 |
struct pci_vmsvga_state_s *pci_vmsvga
|
794 |
= container_of(s, struct pci_vmsvga_state_s, chip);
|
795 |
return pci_get_bar_addr(&pci_vmsvga->card, 2); |
796 |
} |
797 |
|
798 |
case SVGA_REG_MEM_SIZE:
|
799 |
return s->fifo_size;
|
800 |
|
801 |
case SVGA_REG_CONFIG_DONE:
|
802 |
return s->config;
|
803 |
|
804 |
case SVGA_REG_SYNC:
|
805 |
case SVGA_REG_BUSY:
|
806 |
return s->syncing;
|
807 |
|
808 |
case SVGA_REG_GUEST_ID:
|
809 |
return s->guest;
|
810 |
|
811 |
case SVGA_REG_CURSOR_ID:
|
812 |
return s->cursor.id;
|
813 |
|
814 |
case SVGA_REG_CURSOR_X:
|
815 |
return s->cursor.x;
|
816 |
|
817 |
case SVGA_REG_CURSOR_Y:
|
818 |
return s->cursor.x;
|
819 |
|
820 |
case SVGA_REG_CURSOR_ON:
|
821 |
return s->cursor.on;
|
822 |
|
823 |
case SVGA_REG_HOST_BITS_PER_PIXEL:
|
824 |
return (s->depth + 7) & ~7; |
825 |
|
826 |
case SVGA_REG_SCRATCH_SIZE:
|
827 |
return s->scratch_size;
|
828 |
|
829 |
case SVGA_REG_MEM_REGS:
|
830 |
case SVGA_REG_NUM_DISPLAYS:
|
831 |
case SVGA_REG_PITCHLOCK:
|
832 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
833 |
return 0; |
834 |
|
835 |
default:
|
836 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
837 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
838 |
return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
839 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
840 |
} |
841 |
|
842 |
return 0; |
843 |
} |
844 |
|
845 |
static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
846 |
{ |
847 |
struct vmsvga_state_s *s = opaque;
|
848 |
switch (s->index) {
|
849 |
case SVGA_REG_ID:
|
850 |
if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
851 |
s->svgaid = value; |
852 |
break;
|
853 |
|
854 |
case SVGA_REG_ENABLE:
|
855 |
s->enable = value; |
856 |
s->config &= !!value; |
857 |
s->width = -1;
|
858 |
s->height = -1;
|
859 |
s->invalidated = 1;
|
860 |
s->vga.invalidate(&s->vga); |
861 |
if (s->enable) {
|
862 |
s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
863 |
vga_dirty_log_stop(&s->vga); |
864 |
} else {
|
865 |
vga_dirty_log_start(&s->vga); |
866 |
} |
867 |
break;
|
868 |
|
869 |
case SVGA_REG_WIDTH:
|
870 |
s->new_width = value; |
871 |
s->invalidated = 1;
|
872 |
break;
|
873 |
|
874 |
case SVGA_REG_HEIGHT:
|
875 |
s->new_height = value; |
876 |
s->invalidated = 1;
|
877 |
break;
|
878 |
|
879 |
case SVGA_REG_DEPTH:
|
880 |
case SVGA_REG_BITS_PER_PIXEL:
|
881 |
if (value != s->depth) {
|
882 |
printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
883 |
s->config = 0;
|
884 |
} |
885 |
break;
|
886 |
|
887 |
case SVGA_REG_CONFIG_DONE:
|
888 |
if (value) {
|
889 |
s->fifo = (uint32_t *) s->fifo_ptr; |
890 |
/* Check range and alignment. */
|
891 |
if ((CMD(min) | CMD(max) |
|
892 |
CMD(next_cmd) | CMD(stop)) & 3)
|
893 |
break;
|
894 |
if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
895 |
break;
|
896 |
if (CMD(max) > SVGA_FIFO_SIZE)
|
897 |
break;
|
898 |
if (CMD(max) < CMD(min) + 10 * 1024) |
899 |
break;
|
900 |
} |
901 |
s->config = !!value; |
902 |
break;
|
903 |
|
904 |
case SVGA_REG_SYNC:
|
905 |
s->syncing = 1;
|
906 |
vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
907 |
break;
|
908 |
|
909 |
case SVGA_REG_GUEST_ID:
|
910 |
s->guest = value; |
911 |
#ifdef VERBOSE
|
912 |
if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
913 |
ARRAY_SIZE(vmsvga_guest_id)) |
914 |
printf("%s: guest runs %s.\n", __FUNCTION__,
|
915 |
vmsvga_guest_id[value - GUEST_OS_BASE]); |
916 |
#endif
|
917 |
break;
|
918 |
|
919 |
case SVGA_REG_CURSOR_ID:
|
920 |
s->cursor.id = value; |
921 |
break;
|
922 |
|
923 |
case SVGA_REG_CURSOR_X:
|
924 |
s->cursor.x = value; |
925 |
break;
|
926 |
|
927 |
case SVGA_REG_CURSOR_Y:
|
928 |
s->cursor.y = value; |
929 |
break;
|
930 |
|
931 |
case SVGA_REG_CURSOR_ON:
|
932 |
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
933 |
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
934 |
#ifdef HW_MOUSE_ACCEL
|
935 |
if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
936 |
s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
937 |
#endif
|
938 |
break;
|
939 |
|
940 |
case SVGA_REG_MEM_REGS:
|
941 |
case SVGA_REG_NUM_DISPLAYS:
|
942 |
case SVGA_REG_PITCHLOCK:
|
943 |
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
944 |
break;
|
945 |
|
946 |
default:
|
947 |
if (s->index >= SVGA_SCRATCH_BASE &&
|
948 |
s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
949 |
s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
950 |
break;
|
951 |
} |
952 |
printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
953 |
} |
954 |
} |
955 |
|
956 |
static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
957 |
{ |
958 |
printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
959 |
return 0xcafe; |
960 |
} |
961 |
|
962 |
static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
963 |
{ |
964 |
printf("%s: what are we supposed to do with (%08x)?\n",
|
965 |
__FUNCTION__, data); |
966 |
} |
967 |
|
968 |
static inline void vmsvga_size(struct vmsvga_state_s *s) |
969 |
{ |
970 |
if (s->new_width != s->width || s->new_height != s->height) {
|
971 |
s->width = s->new_width; |
972 |
s->height = s->new_height; |
973 |
qemu_console_resize(s->vga.ds, s->width, s->height); |
974 |
s->invalidated = 1;
|
975 |
} |
976 |
} |
977 |
|
978 |
static void vmsvga_update_display(void *opaque) |
979 |
{ |
980 |
struct vmsvga_state_s *s = opaque;
|
981 |
if (!s->enable) {
|
982 |
s->vga.update(&s->vga); |
983 |
return;
|
984 |
} |
985 |
|
986 |
vmsvga_size(s); |
987 |
|
988 |
vmsvga_fifo_run(s); |
989 |
vmsvga_update_rect_flush(s); |
990 |
|
991 |
/*
|
992 |
* Is it more efficient to look at vram VGA-dirty bits or wait
|
993 |
* for the driver to issue SVGA_CMD_UPDATE?
|
994 |
*/
|
995 |
if (s->invalidated) {
|
996 |
s->invalidated = 0;
|
997 |
vmsvga_update_screen(s); |
998 |
} |
999 |
} |
1000 |
|
1001 |
static void vmsvga_reset(struct vmsvga_state_s *s) |
1002 |
{ |
1003 |
s->index = 0;
|
1004 |
s->enable = 0;
|
1005 |
s->config = 0;
|
1006 |
s->width = -1;
|
1007 |
s->height = -1;
|
1008 |
s->svgaid = SVGA_ID; |
1009 |
s->depth = ds_get_bits_per_pixel(s->vga.ds); |
1010 |
s->bypp = ds_get_bytes_per_pixel(s->vga.ds); |
1011 |
s->cursor.on = 0;
|
1012 |
s->redraw_fifo_first = 0;
|
1013 |
s->redraw_fifo_last = 0;
|
1014 |
switch (s->depth) {
|
1015 |
case 8: |
1016 |
s->wred = 0x00000007;
|
1017 |
s->wgreen = 0x00000038;
|
1018 |
s->wblue = 0x000000c0;
|
1019 |
break;
|
1020 |
case 15: |
1021 |
s->wred = 0x0000001f;
|
1022 |
s->wgreen = 0x000003e0;
|
1023 |
s->wblue = 0x00007c00;
|
1024 |
break;
|
1025 |
case 16: |
1026 |
s->wred = 0x0000001f;
|
1027 |
s->wgreen = 0x000007e0;
|
1028 |
s->wblue = 0x0000f800;
|
1029 |
break;
|
1030 |
case 24: |
1031 |
s->wred = 0x00ff0000;
|
1032 |
s->wgreen = 0x0000ff00;
|
1033 |
s->wblue = 0x000000ff;
|
1034 |
break;
|
1035 |
case 32: |
1036 |
s->wred = 0x00ff0000;
|
1037 |
s->wgreen = 0x0000ff00;
|
1038 |
s->wblue = 0x000000ff;
|
1039 |
break;
|
1040 |
} |
1041 |
s->syncing = 0;
|
1042 |
|
1043 |
vga_dirty_log_start(&s->vga); |
1044 |
} |
1045 |
|
1046 |
static void vmsvga_invalidate_display(void *opaque) |
1047 |
{ |
1048 |
struct vmsvga_state_s *s = opaque;
|
1049 |
if (!s->enable) {
|
1050 |
s->vga.invalidate(&s->vga); |
1051 |
return;
|
1052 |
} |
1053 |
|
1054 |
s->invalidated = 1;
|
1055 |
} |
1056 |
|
1057 |
/* save the vga display in a PPM image even if no display is
|
1058 |
available */
|
1059 |
static void vmsvga_screen_dump(void *opaque, const char *filename) |
1060 |
{ |
1061 |
struct vmsvga_state_s *s = opaque;
|
1062 |
if (!s->enable) {
|
1063 |
s->vga.screen_dump(&s->vga, filename); |
1064 |
return;
|
1065 |
} |
1066 |
|
1067 |
if (s->depth == 32) { |
1068 |
DisplaySurface *ds = qemu_create_displaysurface_from(s->width, |
1069 |
s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
|
1070 |
ppm_save(filename, ds); |
1071 |
g_free(ds); |
1072 |
} |
1073 |
} |
1074 |
|
1075 |
static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
1076 |
{ |
1077 |
struct vmsvga_state_s *s = opaque;
|
1078 |
|
1079 |
if (s->vga.text_update)
|
1080 |
s->vga.text_update(&s->vga, chardata); |
1081 |
} |
1082 |
|
1083 |
#ifdef DIRECT_VRAM
|
1084 |
static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr) |
1085 |
{ |
1086 |
struct vmsvga_state_s *s = opaque;
|
1087 |
if (addr < s->fb_size)
|
1088 |
return *(uint8_t *) (ds_get_data(s->ds) + addr);
|
1089 |
else
|
1090 |
return *(uint8_t *) (s->vram_ptr + addr);
|
1091 |
} |
1092 |
|
1093 |
static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr) |
1094 |
{ |
1095 |
struct vmsvga_state_s *s = opaque;
|
1096 |
if (addr < s->fb_size)
|
1097 |
return *(uint16_t *) (ds_get_data(s->ds) + addr);
|
1098 |
else
|
1099 |
return *(uint16_t *) (s->vram_ptr + addr);
|
1100 |
} |
1101 |
|
1102 |
static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr) |
1103 |
{ |
1104 |
struct vmsvga_state_s *s = opaque;
|
1105 |
if (addr < s->fb_size)
|
1106 |
return *(uint32_t *) (ds_get_data(s->ds) + addr);
|
1107 |
else
|
1108 |
return *(uint32_t *) (s->vram_ptr + addr);
|
1109 |
} |
1110 |
|
1111 |
static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr, |
1112 |
uint32_t value) |
1113 |
{ |
1114 |
struct vmsvga_state_s *s = opaque;
|
1115 |
if (addr < s->fb_size)
|
1116 |
*(uint8_t *) (ds_get_data(s->ds) + addr) = value; |
1117 |
else
|
1118 |
*(uint8_t *) (s->vram_ptr + addr) = value; |
1119 |
} |
1120 |
|
1121 |
static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr, |
1122 |
uint32_t value) |
1123 |
{ |
1124 |
struct vmsvga_state_s *s = opaque;
|
1125 |
if (addr < s->fb_size)
|
1126 |
*(uint16_t *) (ds_get_data(s->ds) + addr) = value; |
1127 |
else
|
1128 |
*(uint16_t *) (s->vram_ptr + addr) = value; |
1129 |
} |
1130 |
|
1131 |
static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr, |
1132 |
uint32_t value) |
1133 |
{ |
1134 |
struct vmsvga_state_s *s = opaque;
|
1135 |
if (addr < s->fb_size)
|
1136 |
*(uint32_t *) (ds_get_data(s->ds) + addr) = value; |
1137 |
else
|
1138 |
*(uint32_t *) (s->vram_ptr + addr) = value; |
1139 |
} |
1140 |
|
1141 |
static const MemoryRegionOps vmsvga_vram_io_ops = { |
1142 |
.old_mmio = { |
1143 |
.read = { |
1144 |
vmsvga_vram_readb, |
1145 |
vmsvga_vram_readw, |
1146 |
vmsvga_vram_readl, |
1147 |
}, |
1148 |
.write = { |
1149 |
vmsvga_vram_writeb, |
1150 |
vmsvga_vram_writew, |
1151 |
vmsvga_vram_writel, |
1152 |
}, |
1153 |
}, |
1154 |
.endianness = DEVICE_NATIVE_ENDIAN, |
1155 |
} |
1156 |
|
1157 |
#endif
|
1158 |
|
1159 |
static int vmsvga_post_load(void *opaque, int version_id) |
1160 |
{ |
1161 |
struct vmsvga_state_s *s = opaque;
|
1162 |
|
1163 |
s->invalidated = 1;
|
1164 |
if (s->config)
|
1165 |
s->fifo = (uint32_t *) s->fifo_ptr; |
1166 |
|
1167 |
return 0; |
1168 |
} |
1169 |
|
1170 |
static const VMStateDescription vmstate_vmware_vga_internal = { |
1171 |
.name = "vmware_vga_internal",
|
1172 |
.version_id = 0,
|
1173 |
.minimum_version_id = 0,
|
1174 |
.minimum_version_id_old = 0,
|
1175 |
.post_load = vmsvga_post_load, |
1176 |
.fields = (VMStateField []) { |
1177 |
VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
|
1178 |
VMSTATE_INT32(enable, struct vmsvga_state_s),
|
1179 |
VMSTATE_INT32(config, struct vmsvga_state_s),
|
1180 |
VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
1181 |
VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
1182 |
VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
1183 |
VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
1184 |
VMSTATE_INT32(index, struct vmsvga_state_s),
|
1185 |
VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
1186 |
scratch_size, 0, vmstate_info_uint32, uint32_t),
|
1187 |
VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
1188 |
VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
1189 |
VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
1190 |
VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
1191 |
VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
1192 |
VMSTATE_INT32(fb_size, struct vmsvga_state_s),
|
1193 |
VMSTATE_END_OF_LIST() |
1194 |
} |
1195 |
}; |
1196 |
|
1197 |
static const VMStateDescription vmstate_vmware_vga = { |
1198 |
.name = "vmware_vga",
|
1199 |
.version_id = 0,
|
1200 |
.minimum_version_id = 0,
|
1201 |
.minimum_version_id_old = 0,
|
1202 |
.fields = (VMStateField []) { |
1203 |
VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
|
1204 |
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1205 |
vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
1206 |
VMSTATE_END_OF_LIST() |
1207 |
} |
1208 |
}; |
1209 |
|
1210 |
static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size, |
1211 |
MemoryRegion *address_space) |
1212 |
{ |
1213 |
s->scratch_size = SVGA_SCRATCH_SIZE; |
1214 |
s->scratch = g_malloc(s->scratch_size * 4);
|
1215 |
|
1216 |
s->vga.ds = graphic_console_init(vmsvga_update_display, |
1217 |
vmsvga_invalidate_display, |
1218 |
vmsvga_screen_dump, |
1219 |
vmsvga_text_update, s); |
1220 |
|
1221 |
|
1222 |
s->fifo_size = SVGA_FIFO_SIZE; |
1223 |
memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size); |
1224 |
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); |
1225 |
|
1226 |
vga_common_init(&s->vga, vga_ram_size); |
1227 |
vga_init(&s->vga, address_space); |
1228 |
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
1229 |
|
1230 |
vmsvga_reset(s); |
1231 |
} |
1232 |
|
1233 |
static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr, |
1234 |
unsigned size)
|
1235 |
{ |
1236 |
struct vmsvga_state_s *s = opaque;
|
1237 |
|
1238 |
switch (addr) {
|
1239 |
case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); |
1240 |
case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); |
1241 |
case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); |
1242 |
default: return -1u; |
1243 |
} |
1244 |
} |
1245 |
|
1246 |
static void vmsvga_io_write(void *opaque, target_phys_addr_t addr, |
1247 |
uint64_t data, unsigned size)
|
1248 |
{ |
1249 |
struct vmsvga_state_s *s = opaque;
|
1250 |
|
1251 |
switch (addr) {
|
1252 |
case SVGA_IO_MUL * SVGA_INDEX_PORT:
|
1253 |
return vmsvga_index_write(s, addr, data);
|
1254 |
case SVGA_IO_MUL * SVGA_VALUE_PORT:
|
1255 |
return vmsvga_value_write(s, addr, data);
|
1256 |
case SVGA_IO_MUL * SVGA_BIOS_PORT:
|
1257 |
return vmsvga_bios_write(s, addr, data);
|
1258 |
} |
1259 |
} |
1260 |
|
1261 |
static const MemoryRegionOps vmsvga_io_ops = { |
1262 |
.read = vmsvga_io_read, |
1263 |
.write = vmsvga_io_write, |
1264 |
.endianness = DEVICE_LITTLE_ENDIAN, |
1265 |
.valid = { |
1266 |
.min_access_size = 4,
|
1267 |
.max_access_size = 4,
|
1268 |
}, |
1269 |
}; |
1270 |
|
1271 |
static int pci_vmsvga_initfn(PCIDevice *dev) |
1272 |
{ |
1273 |
struct pci_vmsvga_state_s *s =
|
1274 |
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1275 |
MemoryRegion *iomem; |
1276 |
|
1277 |
#ifdef DIRECT_VRAM
|
1278 |
DirectMem *directmem = g_malloc(sizeof(*directmem));
|
1279 |
|
1280 |
iomem = &directmem->mr; |
1281 |
memory_region_init_io(iomem, &vmsvga_vram_io_ops, &s->chip, "vmsvga",
|
1282 |
memory_region_size(&s->chip.vga.vram)); |
1283 |
#else
|
1284 |
iomem = &s->chip.vga.vram; |
1285 |
#endif
|
1286 |
|
1287 |
vga_dirty_log_restart(&s->chip.vga); |
1288 |
|
1289 |
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
1290 |
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ |
1291 |
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ |
1292 |
|
1293 |
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, |
1294 |
"vmsvga-io", 0x10); |
1295 |
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1296 |
|
1297 |
vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev)); |
1298 |
|
1299 |
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
|
1300 |
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
1301 |
&s->chip.fifo_ram); |
1302 |
|
1303 |
if (!dev->rom_bar) {
|
1304 |
/* compatibility with pc-0.13 and older */
|
1305 |
vga_init_vbe(&s->chip.vga, pci_address_space(dev)); |
1306 |
} |
1307 |
|
1308 |
return 0; |
1309 |
} |
1310 |
|
1311 |
static PCIDeviceInfo vmsvga_info = {
|
1312 |
.qdev.name = "vmware-svga",
|
1313 |
.qdev.size = sizeof(struct pci_vmsvga_state_s), |
1314 |
.qdev.vmsd = &vmstate_vmware_vga, |
1315 |
.no_hotplug = 1,
|
1316 |
.init = pci_vmsvga_initfn, |
1317 |
.romfile = "vgabios-vmware.bin",
|
1318 |
|
1319 |
.vendor_id = PCI_VENDOR_ID_VMWARE, |
1320 |
.device_id = SVGA_PCI_DEVICE_ID, |
1321 |
.class_id = PCI_CLASS_DISPLAY_VGA, |
1322 |
.subsystem_vendor_id = PCI_VENDOR_ID_VMWARE, |
1323 |
.subsystem_id = SVGA_PCI_DEVICE_ID, |
1324 |
}; |
1325 |
|
1326 |
static void vmsvga_register(void) |
1327 |
{ |
1328 |
pci_qdev_register(&vmsvga_info); |
1329 |
} |
1330 |
device_init(vmsvga_register); |