MPC8544DS: Remove CPU nodes
We want to generate the CPU nodes in machine init code, so remove them fromthe device tree definition that we precompile.
Signed-off-by: Alexander Graf <agraf@suse.de>
device tree: give dt more size
We currently load a device tree blob and then just take its size x2 toaccount for modifications we do inside. While this is nice and great,it fails when we have a small device tree as blob and lots of nodes addedin machine init code....
PPC: E500: Update cpu-release-addr property in cpu nodes
The guest OS wants to know where the guest spins, so let's tell him whileupdating the CPU nodes with the frequencies anyways.
v1 -> v2:
- use new spin table address
device tree: add add_subnode command
We want to be able to create subnodes in our device tree, so export it throughthe qemu device tree abstraction framework.
device tree: dont fail operations
When we screw up and issue an FDT command that doesn't work, we really need toknow immediately and usually can't continue to create the machine. To make surewe don't need to add error checking in all device tree modification code users,...
PPC: E500: Add PV spinning code
CPUs that are not the boot CPU need to run in spinning code to check if theyshould run off to execute and if so where to jump to. This usually happensby leaving secondary CPUs looping and checking if some variable in memory...
PPC: KVM: Remove kvmppc_read_host_property
We just got rid of the last user of kvmppc_read_host_property, so wecan now safely remove it.
PPC: KVM: Add stubs for kvm helper functions
We have a bunch of helper functions that don't have any stubs for them in casewe don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc canoptimize them out pretty well, but we should really provide them....
PPC: E500: Update freqs for all CPUs
Now that we can so nicely find out the host's frequencies, we should alsomake sure that we get them into all virtual CPUs' device tree nodes.
PPC: E500: Remove unneeded CPU nodes
We should only keep CPU nodes in the device tree around that we really havevirtual CPUs for. So remove all superfluous entries that we just keep therein case someone wants to create a lot of vCPUs.
device tree: add nop_node
We have a qemu internal abstraction layer on FDT. While I'm not fully convincedwe need it at all, it's missing the nop_node functionality that we now needon e500. So let's add it and think about the general future of that API later....
PPC: bamboo: Move host fdt copy to target
We have some code in generic kvm_ppc.c that is only used by 440. Move tothe 440 specific device code.
PPC: KVM: Add generic function to read host clockfreq
We need to find out the host's clock-frequency when running on KVM, solet's export a respective function.
- enable 64bit values
PPC: E500: Use generic kvm function for freq
Now that we have generic KVM functions to read out the host tb and clockfrequencies, let's use them in the e500 code!
PPC: E500: Remove mpc8544_copy_soc_cell
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly readinghost values and writing guest values respectively.
PPC: bamboo: Use kvm api for freq and clock frequencies
Now that we have nice and shiny APIs to read out the host's clock and timebasefrequencies, let's use them in the bamboo code as well!
PPC: Add CPU local MMIO regions to MPIC
The MPIC exports a register set for each CPU connected to it. They can allbe accessed through specific registers or using a shadow page that is mappeddifferently depending on which CPU accesses it.
This patch implements the shadow map, making it possible for guests to access...
PPC: Extend MPIC MMIO range
The MPIC exports a page for each CPU that it controls. To support more thanone CPU, we need to also reserve the MMIO space according to the amount ofCPUs we want to support.
PPC: Fix IPI support in MPIC
The current IPI support in the MPIC code is incomplete and doesn't work. Thiscode adds proper support for IPIs in MPIC by using the IDE register to rememberwhich CPUs IPIs are still outstanding to. New triggers through the IPI trigger...
PPC: Set MPIC IDE for IPI to 0
We use the IDE register with IPIs as a mask to keep track which processorshave already acknowledged the respective interrupt. So we need to initializeit to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the...
PPC: MPIC: Remove read functionality for WO registers
The IPI dispatch registers are write only according to every MPICspec I have found. So instead of pretending you could read back somethingfrom them, better not handle them at all.
Reported-by: Elie Richa <richa@adacore.com>...
PPC: MPIC: Fix CI bit definitions
The bit definitions for critical interrupt routing are in PowerPC order(most significant bit is 0), while we end up shifting it with normal bitorder. Turn the numbers around so we actually end up fetching theright ones....
PPC: Bump MPIC up to 32 supported CPUs
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that inthe code exporting the numbers out and fix an integer overflow while at it.
v1 -> v2:...
PPC: E500: create multiple envs
When creating a VM, we should go through smp_cpus and create a virtual CPU forevery CPU the user requested. This patch adds support for that and moves somecode around to make that more convenient.
PPC: E500: Generate IRQ lines for many CPUs
Now that we can generate multiple envs for all our virtual CPUs, wealso need to tell the MPIC that we have multiple CPUs connected andconnect them all to the respective virtual interrupt lines.
spapr: proper qdevification
Right now the spapr devices cannot be instantiated with -device,because the IRQs need to be passed to the spapr_*_create functions.Do this instead in the bus's init wrapper.
This is particularly important with the conversion from scsi-disk...
spapr: prepare for qdevification of irq
Restructure common properties for sPAPR devices so that IRQ definitionscan be added in one place.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Cc: Alexander Graf <agraf@suse.de>Cc: David Gibson <david@gibson.dropbear.id.au>...
spapr: make irq customizable via qdev
This also lets the user see the irq in "info qtree".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Cc: Alexander Graf <agraf@suse.de>Cc: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Move openpic to target specific code compilation
The MPIC has some funny feature where it maps different registers to an MMIOregion depending which CPU accesses them.
To be able to reflect that, we need to make OpenPIC be compiled in the targetcode, so it can access cpu_single_env....
qed: fix use-after-free during l2 cache commit
QED's metadata caching strategy allows two parallel requests to race formetadata lookup. The first one to complete will populate the metadatacache and the second one will drop the data it just read in favor of the...
etrax-dma: Remove bogus if statement
Reported-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
memory: Print region priority
Useful to discover eclipses.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Avi Kivity <avi@redhat.com>
memory: Do not print empty PIO root
memory: Print regions in ascending order
Makes reading the output more user friendly.
memory: simple memory tree printer
Add a monitor command 'info mtree' to show the memory hierarchymuch like /proc/iomem in Linux.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Avi Kivity <avi@redhat.com>
Move GETPC from dyngen-exec.h to exec-all.h
GETPC can be used even from outside of helper code. Move the macro toa more accessible location. Avoid a compile warning from redefining it in exec.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Document softmmu templates
Add some comments to describe each file.
ESP: convert to trace framework
PPC: Drop initial ESCC mapping
We are mapping ESCC to a static (incorrect) address on machine init. Thisoverlaps with our vram, rendering the screen barely usable.
Since openBIOS is clever enough to map ESCC to where it needs to be, we canjust drop that invalid map and everyone's happy....
tcg-i386: Introduce limited deposit support
x86 cannot provide an optimized generic deposit implementation. But atleast for a few special cases, namely for writing bits 0..7, 8..15, and0..15, versions using only a single instruction are feasible.Introducing such limited support improves emulating 16-bit x86 code on...
mips_fulong2e: Reorder ISA bus and i8259 creation
Missed during memory region conversion: The i8259 now depends on the ISAbus being created first. Reorder the initialization.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386: Remove redundant word mask in port out instructions
T0 was already masked to 16 bits when loading it.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softfloat: Reinstate accidentally disabled target-specific NaN handling
Include config.h in softfloat.c, so that the target specific ifdefs insoftfloat-specialize.h are evaluated correctly. This was accidentallybroken in commit 789ec7ce2 when config-target.h was removed from...
tcg/arm: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ARM TCG backend;this fixes a compilation failure on ARM hosts with newer gcc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
configure: Detect predefined compiler symbols for ARM and HPPA
To be able to detect some ARM / HPPA based architectures such as withOpenBSD/(armish / zaurus) or OpenBSD/hppa.
Signed-off-by: Brad Smith <brad@comstyle.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Add some assertions
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Add forward declarations for local functions
These functions are defined in the tcg target specific filetcg-target.c.
The forward declarations assert that every tcg target usesthe same function prototype.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,so the tcg target specific declarations are redundant.
tcg: Declare TCG_TARGET_REG_BITS in tcg.h
TCG_TARGET_REG_BITS can be determined by the compiler,so there is no need to declare it for each individual tcg target.
This is especially important for new tcg targetswhich will be supported by the tcg interpreter....
Merge remote-tracking branch 'kiszka/queues/slirp' into staging
Merge remote-tracking branch 'aneesh/for-upstream-5' into staging
Add OpenBIOS as a submodule
Update OpenBIOS images to r1047 built from submodule.
slirp: Fix packet expiration
The two new variables "arp_requested" and "expiration_date" in the mbufstructure have been added after the variable-sized "m_dat_" array. Thevariables have to be added before the m_dat_ array instead.Without this patch, the expiration_date gets clobbered by code that...
slirp: Fix use after release on tcp_input
ti points into the m buffer. But the latter may already be releasedright after the dodata: label. Move the test before the potentialrelease.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
PPC: use memory API to construct the PCI hole
Avoid vga.chain4 mapping by constructing a PCI hole for upper2G of the PCI space.
Merge remote-tracking branch 'qemu-kvm-tmp/memory/urgent' into staging
Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into staging
Merge remote-tracking branch 'qemu-kvm-tmp/memory/core' into staging
Merge remote-tracking branch 'pmaydell/omap-for-upstream' into staging
Merge remote-tracking branch 'riku/linux-user-for-upstream' into staging
ppc_prep: fix pci config space initialization
Use data_mem for the data mmio region, not conf_mem.
Signed-off-by: Avi Kivity <avi@redhat.com>
mips_r4k: initialize i8259 after the ISA bus
Succeeding i8259 conversion to ISA requires this.
ppc_prep: initialize i8259 after the ISA bus
i8259: Convert to MemoryRegion
The only non-obvious part is pic_poll_read which used"addr1 >> 7" to detect whether one referred to eitherthe master or slave PIC. Instead, test this directly.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Avi Kivity <avi@redhat.com>
pckbd: Convert to MemoryRegion
Slightly non-obvious with mips_jazz passing in the regionstructure to populate.
serial: Convert serial_isa_initfn to MemoryRegion
The serial_mm_init path is as yet unconverted.
fdc: Convert isabus_fdc_init1 to MemoryRegion
This requires some amount of hoop-jumping, so that we don'tinadvertently claim port 0x3f6, which is used by ISA IDE.
The sysbus initialization path is as yet unconverted.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
isa: add isa_register_ioport()
To replace isa_init_ioport and isa_init_ioport_rangeas the ISA devices are converted to the memory api.
[avi: use memory_region_size()]
pc: Re-order pc_init1 to initialize the ISA bus before ISA devices
In particular, the i8259 was being initialized before the ISA bus,leading to a crash.
cs4231a: Convert to MemoryRegion
i8254: Convert to MemoryRegion
mips_malta: move i8259 initialization after piix4 initialization
i8259 is an ISA device (or at least, depends on the ISA infrastructure toregister its ioport); and the ISA bus is supplied by piix4. Later patchesmake this dependency explicit.
Use qemu_irq_proxy() to stop the cycle by adding an extra layer of...
mips_jazz: initialize i8259 after the ISA bus
isa: Pass i/o address space to isa_bus_new
Not used yet, but at least we're provided with the correct region.
pci: add pci_address_space_io()
Returns the I/O address space. Useful for implementingPCI-ISA bridge devices.
memory: implement memory_region_set_readonly()
The property is inheritable, but only if set to true. This is sothat memory routers can mark sections of RAM as read-only via aliases.
Makefile: Remove 'tarbin' target
Remove the 'tarbin' target -- it isn't used as part of the officialQEMU release process, and it's out of date (various new bios fileswere never added to its list of files). It's better not to provideit at all than to have a broken makefile target we never use or test....
MAINTAINERS: update maintainer for target-arm and ARM devboards
Add myself as co-maintainer alongside Paul Brook for the TCG ARMguest implementation (target-arm) and the ARM dev boards (integratorcp,realview, stellaris, versatilepb).
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>...
adlib: remove write-only variable
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
qemu-char: use qemu_set_fd_handler/2 consistently
Now that qemu_set_fd_handler and qemu_set_fd_handler2 have differentimplementations, one using qemu iohandlers and the other glib, it is notsafe to mix the two when inserting/deleting handlers.
Fixes kvm-autotest....
Move macro QEMU_GNUC_PREREQ to compiler.h
The macro is compiler specific and does not depend on the operating system.
Move macro QEMU_GNUC_PREREQ from osdep.h to compiler.hand use it to simplify existing code.
host-utils.h uses this macro, so it now needs compiler.h...
Fix and clean code which tests the gcc version
The code which tests whether gcc supports warn_unused_result was wrong.Remove the wrong test from configure and replace it by code usingmacro QEMU_GNUC_PREREQ in compiler.h.
virtio: Use global memory barrier macros
The virtio code uses wmb() macros in several places, as required by theSMP-aware virtio protocol. However the wmb() macro is locally definedto be a compiler barrier only. This is probably sufficient on x86due to its strong storage ordering model, but it certainly isn't on other...
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrierprimitives used in several places throughout qemu. However, apartfrom the compiler-only barrier, the defined wmb() is correct only for...
irq: introduce qemu_irq_proxy()
In some cases we have a circular dependency involving irqs - the irqcontroller depends on a bus, which in turn depends on the irq controller.Add qemu_irq_proxy() which acts as a passthrough, except that the targetirq may be set later on....
build: fix race with creating qapi-generated
Since qapi-generated/ is a global QEMU include path, we need to makesure it is created before anything is compiled, so do this in theconfigure phase rather than via the Makefile.
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>...
isapc: give system address space when pci is disabled
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
pci-devfn: check that device/slot number is within range
Need to check that guest slot/device number is not > 31 or walk offthe devfn table when checking if a devfn is available or not in a guest.
before this fix, passing in an addr=abc or addr=34,can crash qemu, sometimes fail gracefully if data past end...
pc: Unbreak ROM mapping for ISA machine
This is based on the original fix by Hervé Poussineau: pc_memory_initactually takes a memory region for mapping BIOS and extension ROMs. Thatequals the PCI memory region if PCI is available, but must be systemmemory in the ISA case....
pc: Disable HPET for ISA machine
There was no HPET on ISA boxes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
vga: Unbreak ISA support
We need to initialize legacy_address_space during ISA VGA setup so thatthe chain-4 alias can be registered properly.
cirrus: Unbreak ISA support
Do not try to map against the PCI bar in the ISA version of the device.
core: remove qemu_service_io
qemu_service_io was mainly an alias to qemu_notify_event,currently used only by PPC for timer hack, so callqemu_notify_event directly.
Signed-off-by: Frediano Ziglio <freddy77@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
e1000: Don't set the Capabilities List bit
[Originally sent to qemu-kvm list, but I was redirected here]
The Capabilities Pointer is NULL, so this bit shouldn't be set. The state ofthis bit doesn't appear to change any behavior on Linux/Windows versions we've...
MAINTAINERS: claim maintainership for the OMAP devices
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
hw/omap1: Wire up GPIO clock
Wire up the OMAP1 GPIO clock -- this fixes a hw_error() on startupwith OMAP1 based machines (sx1, cheetah).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
omap_intc: Use MemoryRegion API
Convert omap_intc to use the MemoryRegion API
omap_intc: Qdevify
Convert the omap_intc devices to qdev. This includes addinga 'revision' property which will be needed for omap3.
The bulk of this patch is the replacement of "s->irq[x][y]" with "qdev_get_gpio_in(s->ih[x], y)" now that the interrupt...
hw/omap_gpmc: Modify correct field when writing IRQSTATUS register
Writing to IRQSTATUS should affect irqst, not irqen -- errorspotted by Andrzej Zaborowski.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>