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1 | 267002cd | bellard | /*
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2 | 267002cd | bellard | * QEMU CUDA support
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3 | 267002cd | bellard | *
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4 | 267002cd | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 267002cd | bellard | *
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6 | 267002cd | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 267002cd | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 267002cd | bellard | * in the Software without restriction, including without limitation the rights
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9 | 267002cd | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 267002cd | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 267002cd | bellard | * furnished to do so, subject to the following conditions:
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12 | 267002cd | bellard | *
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13 | 267002cd | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 267002cd | bellard | * all copies or substantial portions of the Software.
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15 | 267002cd | bellard | *
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16 | 267002cd | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 267002cd | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 267002cd | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 267002cd | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 267002cd | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 267002cd | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 267002cd | bellard | * THE SOFTWARE.
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23 | 267002cd | bellard | */
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24 | 267002cd | bellard | #include "vl.h" |
25 | 267002cd | bellard | |
26 | 61271e5c | bellard | /* XXX: implement all timer modes */
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27 | 61271e5c | bellard | |
28 | 819e712b | bellard | //#define DEBUG_CUDA
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29 | 819e712b | bellard | //#define DEBUG_CUDA_PACKET
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30 | 819e712b | bellard | |
31 | 267002cd | bellard | /* Bits in B data register: all active low */
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32 | 267002cd | bellard | #define TREQ 0x08 /* Transfer request (input) */ |
33 | 267002cd | bellard | #define TACK 0x10 /* Transfer acknowledge (output) */ |
34 | 267002cd | bellard | #define TIP 0x20 /* Transfer in progress (output) */ |
35 | 267002cd | bellard | |
36 | 267002cd | bellard | /* Bits in ACR */
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37 | 267002cd | bellard | #define SR_CTRL 0x1c /* Shift register control bits */ |
38 | 267002cd | bellard | #define SR_EXT 0x0c /* Shift on external clock */ |
39 | 267002cd | bellard | #define SR_OUT 0x10 /* Shift out if 1 */ |
40 | 267002cd | bellard | |
41 | 267002cd | bellard | /* Bits in IFR and IER */
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42 | 267002cd | bellard | #define IER_SET 0x80 /* set bits in IER */ |
43 | 267002cd | bellard | #define IER_CLR 0 /* clear bits in IER */ |
44 | 267002cd | bellard | #define SR_INT 0x04 /* Shift register full/empty */ |
45 | 267002cd | bellard | #define T1_INT 0x40 /* Timer 1 interrupt */ |
46 | 61271e5c | bellard | #define T2_INT 0x20 /* Timer 2 interrupt */ |
47 | 267002cd | bellard | |
48 | 267002cd | bellard | /* Bits in ACR */
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49 | 267002cd | bellard | #define T1MODE 0xc0 /* Timer 1 mode */ |
50 | 267002cd | bellard | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
51 | 267002cd | bellard | |
52 | 267002cd | bellard | /* commands (1st byte) */
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53 | 267002cd | bellard | #define ADB_PACKET 0 |
54 | 267002cd | bellard | #define CUDA_PACKET 1 |
55 | 267002cd | bellard | #define ERROR_PACKET 2 |
56 | 267002cd | bellard | #define TIMER_PACKET 3 |
57 | 267002cd | bellard | #define POWER_PACKET 4 |
58 | 267002cd | bellard | #define MACIIC_PACKET 5 |
59 | 267002cd | bellard | #define PMU_PACKET 6 |
60 | 267002cd | bellard | |
61 | 267002cd | bellard | |
62 | 267002cd | bellard | /* CUDA commands (2nd byte) */
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63 | 267002cd | bellard | #define CUDA_WARM_START 0x0 |
64 | 267002cd | bellard | #define CUDA_AUTOPOLL 0x1 |
65 | 267002cd | bellard | #define CUDA_GET_6805_ADDR 0x2 |
66 | 267002cd | bellard | #define CUDA_GET_TIME 0x3 |
67 | 267002cd | bellard | #define CUDA_GET_PRAM 0x7 |
68 | 267002cd | bellard | #define CUDA_SET_6805_ADDR 0x8 |
69 | 267002cd | bellard | #define CUDA_SET_TIME 0x9 |
70 | 267002cd | bellard | #define CUDA_POWERDOWN 0xa |
71 | 267002cd | bellard | #define CUDA_POWERUP_TIME 0xb |
72 | 267002cd | bellard | #define CUDA_SET_PRAM 0xc |
73 | 267002cd | bellard | #define CUDA_MS_RESET 0xd |
74 | 267002cd | bellard | #define CUDA_SEND_DFAC 0xe |
75 | 267002cd | bellard | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
76 | 267002cd | bellard | #define CUDA_RESET_SYSTEM 0x11 |
77 | 267002cd | bellard | #define CUDA_SET_IPL 0x12 |
78 | 267002cd | bellard | #define CUDA_FILE_SERVER_FLAG 0x13 |
79 | 267002cd | bellard | #define CUDA_SET_AUTO_RATE 0x14 |
80 | 267002cd | bellard | #define CUDA_GET_AUTO_RATE 0x16 |
81 | 267002cd | bellard | #define CUDA_SET_DEVICE_LIST 0x19 |
82 | 267002cd | bellard | #define CUDA_GET_DEVICE_LIST 0x1a |
83 | 267002cd | bellard | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
84 | 267002cd | bellard | #define CUDA_SET_POWER_MESSAGES 0x21 |
85 | 267002cd | bellard | #define CUDA_GET_SET_IIC 0x22 |
86 | 267002cd | bellard | #define CUDA_WAKEUP 0x23 |
87 | 267002cd | bellard | #define CUDA_TIMER_TICKLE 0x24 |
88 | 267002cd | bellard | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
89 | 267002cd | bellard | |
90 | 267002cd | bellard | #define CUDA_TIMER_FREQ (4700000 / 6) |
91 | e2733d20 | bellard | #define CUDA_ADB_POLL_FREQ 50 |
92 | 267002cd | bellard | |
93 | d7ce296f | bellard | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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94 | d7ce296f | bellard | #define RTC_OFFSET 2082844800 |
95 | d7ce296f | bellard | |
96 | 267002cd | bellard | typedef struct CUDATimer { |
97 | 61271e5c | bellard | int index;
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98 | 61271e5c | bellard | uint16_t latch; |
99 | 267002cd | bellard | uint16_t counter_value; /* counter value at load time */
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100 | 267002cd | bellard | int64_t load_time; |
101 | 267002cd | bellard | int64_t next_irq_time; |
102 | 267002cd | bellard | QEMUTimer *timer; |
103 | 267002cd | bellard | } CUDATimer; |
104 | 267002cd | bellard | |
105 | 267002cd | bellard | typedef struct CUDAState { |
106 | 267002cd | bellard | /* cuda registers */
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107 | 267002cd | bellard | uint8_t b; /* B-side data */
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108 | 267002cd | bellard | uint8_t a; /* A-side data */
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109 | 267002cd | bellard | uint8_t dirb; /* B-side direction (1=output) */
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110 | 267002cd | bellard | uint8_t dira; /* A-side direction (1=output) */
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111 | 267002cd | bellard | uint8_t sr; /* Shift register */
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112 | 267002cd | bellard | uint8_t acr; /* Auxiliary control register */
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113 | 267002cd | bellard | uint8_t pcr; /* Peripheral control register */
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114 | 267002cd | bellard | uint8_t ifr; /* Interrupt flag register */
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115 | 267002cd | bellard | uint8_t ier; /* Interrupt enable register */
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116 | 267002cd | bellard | uint8_t anh; /* A-side data, no handshake */
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117 | 267002cd | bellard | |
118 | 267002cd | bellard | CUDATimer timers[2];
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119 | 267002cd | bellard | |
120 | 267002cd | bellard | uint8_t last_b; /* last value of B register */
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121 | 267002cd | bellard | uint8_t last_acr; /* last value of B register */
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122 | 267002cd | bellard | |
123 | 267002cd | bellard | int data_in_size;
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124 | 267002cd | bellard | int data_in_index;
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125 | 267002cd | bellard | int data_out_index;
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126 | 267002cd | bellard | |
127 | cadae95f | bellard | SetIRQFunc *set_irq; |
128 | 267002cd | bellard | int irq;
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129 | cadae95f | bellard | void *irq_opaque;
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130 | 267002cd | bellard | uint8_t autopoll; |
131 | 267002cd | bellard | uint8_t data_in[128];
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132 | 267002cd | bellard | uint8_t data_out[16];
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133 | e2733d20 | bellard | QEMUTimer *adb_poll_timer; |
134 | 267002cd | bellard | } CUDAState; |
135 | 267002cd | bellard | |
136 | 267002cd | bellard | static CUDAState cuda_state;
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137 | 267002cd | bellard | ADBBusState adb_bus; |
138 | 267002cd | bellard | |
139 | 267002cd | bellard | static void cuda_update(CUDAState *s); |
140 | 267002cd | bellard | static void cuda_receive_packet_from_host(CUDAState *s, |
141 | 267002cd | bellard | const uint8_t *data, int len); |
142 | 819e712b | bellard | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
143 | 819e712b | bellard | int64_t current_time); |
144 | 267002cd | bellard | |
145 | 267002cd | bellard | static void cuda_update_irq(CUDAState *s) |
146 | 267002cd | bellard | { |
147 | 819e712b | bellard | if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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148 | cadae95f | bellard | s->set_irq(s->irq_opaque, s->irq, 1);
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149 | 267002cd | bellard | } else {
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150 | cadae95f | bellard | s->set_irq(s->irq_opaque, s->irq, 0);
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151 | 267002cd | bellard | } |
152 | 267002cd | bellard | } |
153 | 267002cd | bellard | |
154 | 267002cd | bellard | static unsigned int get_counter(CUDATimer *s) |
155 | 267002cd | bellard | { |
156 | 267002cd | bellard | int64_t d; |
157 | 267002cd | bellard | unsigned int counter; |
158 | 267002cd | bellard | |
159 | 267002cd | bellard | d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
160 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
161 | 61271e5c | bellard | if (s->index == 0) { |
162 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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163 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
164 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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165 | 61271e5c | bellard | } else {
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166 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
167 | 61271e5c | bellard | counter = (s->latch - counter) & 0xffff;
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168 | 61271e5c | bellard | } |
169 | 267002cd | bellard | } else {
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170 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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171 | 267002cd | bellard | } |
172 | 267002cd | bellard | return counter;
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173 | 267002cd | bellard | } |
174 | 267002cd | bellard | |
175 | 819e712b | bellard | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
176 | 267002cd | bellard | { |
177 | 819e712b | bellard | #ifdef DEBUG_CUDA
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178 | 819e712b | bellard | printf("cuda: T%d.counter=%d\n",
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179 | 819e712b | bellard | 1 + (ti->timer == NULL), val); |
180 | 819e712b | bellard | #endif
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181 | 819e712b | bellard | ti->load_time = qemu_get_clock(vm_clock); |
182 | 819e712b | bellard | ti->counter_value = val; |
183 | 819e712b | bellard | cuda_timer_update(s, ti, ti->load_time); |
184 | 267002cd | bellard | } |
185 | 267002cd | bellard | |
186 | 267002cd | bellard | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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187 | 267002cd | bellard | { |
188 | 61271e5c | bellard | int64_t d, next_time; |
189 | 61271e5c | bellard | unsigned int counter; |
190 | 61271e5c | bellard | |
191 | 267002cd | bellard | /* current counter value */
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192 | 267002cd | bellard | d = muldiv64(current_time - s->load_time, |
193 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
194 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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195 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
196 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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197 | 61271e5c | bellard | } else {
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198 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
199 | 61271e5c | bellard | counter = (s->latch - counter) & 0xffff;
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200 | 61271e5c | bellard | } |
201 | 61271e5c | bellard | |
202 | 61271e5c | bellard | /* Note: we consider the irq is raised on 0 */
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203 | 61271e5c | bellard | if (counter == 0xffff) { |
204 | 61271e5c | bellard | next_time = d + s->latch + 1;
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205 | 61271e5c | bellard | } else if (counter == 0) { |
206 | 61271e5c | bellard | next_time = d + s->latch + 2;
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207 | 61271e5c | bellard | } else {
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208 | 61271e5c | bellard | next_time = d + counter; |
209 | 267002cd | bellard | } |
210 | dccfafc4 | bellard | #if 0
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211 | 819e712b | bellard | #ifdef DEBUG_CUDA
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212 | 26a76461 | bellard | printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
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213 | 819e712b | bellard | s->latch, d, next_time - d);
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214 | 819e712b | bellard | #endif
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215 | dccfafc4 | bellard | #endif
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216 | 267002cd | bellard | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
217 | 267002cd | bellard | s->load_time; |
218 | 267002cd | bellard | if (next_time <= current_time)
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219 | 267002cd | bellard | next_time = current_time + 1;
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220 | 267002cd | bellard | return next_time;
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221 | 267002cd | bellard | } |
222 | 267002cd | bellard | |
223 | 819e712b | bellard | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
224 | 819e712b | bellard | int64_t current_time) |
225 | 819e712b | bellard | { |
226 | 819e712b | bellard | if (!ti->timer)
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227 | 819e712b | bellard | return;
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228 | 819e712b | bellard | if ((s->acr & T1MODE) != T1MODE_CONT) {
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229 | 819e712b | bellard | qemu_del_timer(ti->timer); |
230 | 819e712b | bellard | } else {
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231 | 819e712b | bellard | ti->next_irq_time = get_next_irq_time(ti, current_time); |
232 | 819e712b | bellard | qemu_mod_timer(ti->timer, ti->next_irq_time); |
233 | 819e712b | bellard | } |
234 | 819e712b | bellard | } |
235 | 819e712b | bellard | |
236 | 267002cd | bellard | static void cuda_timer1(void *opaque) |
237 | 267002cd | bellard | { |
238 | 267002cd | bellard | CUDAState *s = opaque; |
239 | 267002cd | bellard | CUDATimer *ti = &s->timers[0];
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240 | 267002cd | bellard | |
241 | 819e712b | bellard | cuda_timer_update(s, ti, ti->next_irq_time); |
242 | 267002cd | bellard | s->ifr |= T1_INT; |
243 | 267002cd | bellard | cuda_update_irq(s); |
244 | 267002cd | bellard | } |
245 | 267002cd | bellard | |
246 | 267002cd | bellard | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
247 | 267002cd | bellard | { |
248 | 267002cd | bellard | CUDAState *s = opaque; |
249 | 267002cd | bellard | uint32_t val; |
250 | 267002cd | bellard | |
251 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
252 | 267002cd | bellard | switch(addr) {
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253 | 267002cd | bellard | case 0: |
254 | 267002cd | bellard | val = s->b; |
255 | 267002cd | bellard | break;
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256 | 267002cd | bellard | case 1: |
257 | 267002cd | bellard | val = s->a; |
258 | 267002cd | bellard | break;
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259 | 267002cd | bellard | case 2: |
260 | 267002cd | bellard | val = s->dirb; |
261 | 267002cd | bellard | break;
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262 | 267002cd | bellard | case 3: |
263 | 267002cd | bellard | val = s->dira; |
264 | 267002cd | bellard | break;
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265 | 267002cd | bellard | case 4: |
266 | 267002cd | bellard | val = get_counter(&s->timers[0]) & 0xff; |
267 | 267002cd | bellard | s->ifr &= ~T1_INT; |
268 | 267002cd | bellard | cuda_update_irq(s); |
269 | 267002cd | bellard | break;
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270 | 267002cd | bellard | case 5: |
271 | 267002cd | bellard | val = get_counter(&s->timers[0]) >> 8; |
272 | 267002cd | bellard | cuda_update_irq(s); |
273 | 267002cd | bellard | break;
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274 | 267002cd | bellard | case 6: |
275 | 267002cd | bellard | val = s->timers[0].latch & 0xff; |
276 | 267002cd | bellard | break;
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277 | 267002cd | bellard | case 7: |
278 | 61271e5c | bellard | /* XXX: check this */
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279 | 267002cd | bellard | val = (s->timers[0].latch >> 8) & 0xff; |
280 | 267002cd | bellard | break;
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281 | 267002cd | bellard | case 8: |
282 | 267002cd | bellard | val = get_counter(&s->timers[1]) & 0xff; |
283 | 61271e5c | bellard | s->ifr &= ~T2_INT; |
284 | 267002cd | bellard | break;
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285 | 267002cd | bellard | case 9: |
286 | 267002cd | bellard | val = get_counter(&s->timers[1]) >> 8; |
287 | 267002cd | bellard | break;
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288 | 267002cd | bellard | case 10: |
289 | 819e712b | bellard | val = s->sr; |
290 | 819e712b | bellard | s->ifr &= ~SR_INT; |
291 | 819e712b | bellard | cuda_update_irq(s); |
292 | 267002cd | bellard | break;
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293 | 267002cd | bellard | case 11: |
294 | 267002cd | bellard | val = s->acr; |
295 | 267002cd | bellard | break;
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296 | 267002cd | bellard | case 12: |
297 | 267002cd | bellard | val = s->pcr; |
298 | 267002cd | bellard | break;
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299 | 267002cd | bellard | case 13: |
300 | 267002cd | bellard | val = s->ifr; |
301 | b7c7b181 | bellard | if (s->ifr & s->ier)
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302 | b7c7b181 | bellard | val |= 0x80;
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303 | 267002cd | bellard | break;
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304 | 267002cd | bellard | case 14: |
305 | b7c7b181 | bellard | val = s->ier | 0x80;
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306 | 267002cd | bellard | break;
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307 | 267002cd | bellard | default:
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308 | 267002cd | bellard | case 15: |
309 | 267002cd | bellard | val = s->anh; |
310 | 267002cd | bellard | break;
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311 | 267002cd | bellard | } |
312 | 267002cd | bellard | #ifdef DEBUG_CUDA
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313 | 819e712b | bellard | if (addr != 13 || val != 0) |
314 | 819e712b | bellard | printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
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315 | 267002cd | bellard | #endif
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316 | 267002cd | bellard | return val;
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317 | 267002cd | bellard | } |
318 | 267002cd | bellard | |
319 | 267002cd | bellard | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
320 | 267002cd | bellard | { |
321 | 267002cd | bellard | CUDAState *s = opaque; |
322 | 267002cd | bellard | |
323 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
324 | 267002cd | bellard | #ifdef DEBUG_CUDA
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325 | 267002cd | bellard | printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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326 | 267002cd | bellard | #endif
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327 | 267002cd | bellard | |
328 | 267002cd | bellard | switch(addr) {
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329 | 267002cd | bellard | case 0: |
330 | 267002cd | bellard | s->b = val; |
331 | 267002cd | bellard | cuda_update(s); |
332 | 267002cd | bellard | break;
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333 | 267002cd | bellard | case 1: |
334 | 267002cd | bellard | s->a = val; |
335 | 267002cd | bellard | break;
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336 | 267002cd | bellard | case 2: |
337 | 267002cd | bellard | s->dirb = val; |
338 | 267002cd | bellard | break;
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339 | 267002cd | bellard | case 3: |
340 | 267002cd | bellard | s->dira = val; |
341 | 267002cd | bellard | break;
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342 | 267002cd | bellard | case 4: |
343 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
344 | 61271e5c | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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345 | 267002cd | bellard | break;
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346 | 267002cd | bellard | case 5: |
347 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
348 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
349 | 61271e5c | bellard | set_counter(s, &s->timers[0], s->timers[0].latch); |
350 | 267002cd | bellard | break;
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351 | 267002cd | bellard | case 6: |
352 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
353 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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354 | 267002cd | bellard | break;
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355 | 267002cd | bellard | case 7: |
356 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
357 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
358 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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359 | 267002cd | bellard | break;
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360 | 267002cd | bellard | case 8: |
361 | 61271e5c | bellard | s->timers[1].latch = val;
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362 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
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363 | 267002cd | bellard | break;
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364 | 267002cd | bellard | case 9: |
365 | 61271e5c | bellard | set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
366 | 267002cd | bellard | break;
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367 | 267002cd | bellard | case 10: |
368 | 267002cd | bellard | s->sr = val; |
369 | 267002cd | bellard | break;
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370 | 267002cd | bellard | case 11: |
371 | 267002cd | bellard | s->acr = val; |
372 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
373 | 267002cd | bellard | cuda_update(s); |
374 | 267002cd | bellard | break;
|
375 | 267002cd | bellard | case 12: |
376 | 267002cd | bellard | s->pcr = val; |
377 | 267002cd | bellard | break;
|
378 | 267002cd | bellard | case 13: |
379 | 267002cd | bellard | /* reset bits */
|
380 | 267002cd | bellard | s->ifr &= ~val; |
381 | 267002cd | bellard | cuda_update_irq(s); |
382 | 267002cd | bellard | break;
|
383 | 267002cd | bellard | case 14: |
384 | 267002cd | bellard | if (val & IER_SET) {
|
385 | 267002cd | bellard | /* set bits */
|
386 | 267002cd | bellard | s->ier |= val & 0x7f;
|
387 | 267002cd | bellard | } else {
|
388 | 267002cd | bellard | /* reset bits */
|
389 | 267002cd | bellard | s->ier &= ~val; |
390 | 267002cd | bellard | } |
391 | 267002cd | bellard | cuda_update_irq(s); |
392 | 267002cd | bellard | break;
|
393 | 267002cd | bellard | default:
|
394 | 267002cd | bellard | case 15: |
395 | 267002cd | bellard | s->anh = val; |
396 | 267002cd | bellard | break;
|
397 | 267002cd | bellard | } |
398 | 267002cd | bellard | } |
399 | 267002cd | bellard | |
400 | 267002cd | bellard | /* NOTE: TIP and TREQ are negated */
|
401 | 267002cd | bellard | static void cuda_update(CUDAState *s) |
402 | 267002cd | bellard | { |
403 | 819e712b | bellard | int packet_received, len;
|
404 | 819e712b | bellard | |
405 | 819e712b | bellard | packet_received = 0;
|
406 | 819e712b | bellard | if (!(s->b & TIP)) {
|
407 | 819e712b | bellard | /* transfer requested from host */
|
408 | 267002cd | bellard | |
409 | 819e712b | bellard | if (s->acr & SR_OUT) {
|
410 | 819e712b | bellard | /* data output */
|
411 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
412 | 819e712b | bellard | if (s->data_out_index < sizeof(s->data_out)) { |
413 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
414 | 819e712b | bellard | printf("cuda: send: %02x\n", s->sr);
|
415 | 819e712b | bellard | #endif
|
416 | 819e712b | bellard | s->data_out[s->data_out_index++] = s->sr; |
417 | 819e712b | bellard | s->ifr |= SR_INT; |
418 | 819e712b | bellard | cuda_update_irq(s); |
419 | 819e712b | bellard | } |
420 | 819e712b | bellard | } |
421 | 819e712b | bellard | } else {
|
422 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
423 | 819e712b | bellard | /* data input */
|
424 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
425 | 819e712b | bellard | s->sr = s->data_in[s->data_in_index++]; |
426 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
427 | 819e712b | bellard | printf("cuda: recv: %02x\n", s->sr);
|
428 | 819e712b | bellard | #endif
|
429 | 819e712b | bellard | /* indicate end of transfer */
|
430 | 819e712b | bellard | if (s->data_in_index >= s->data_in_size) {
|
431 | 819e712b | bellard | s->b = (s->b | TREQ); |
432 | 819e712b | bellard | } |
433 | 819e712b | bellard | s->ifr |= SR_INT; |
434 | 819e712b | bellard | cuda_update_irq(s); |
435 | 819e712b | bellard | } |
436 | 267002cd | bellard | } |
437 | 819e712b | bellard | } |
438 | 819e712b | bellard | } else {
|
439 | 819e712b | bellard | /* no transfer requested: handle sync case */
|
440 | 819e712b | bellard | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
441 | 819e712b | bellard | /* update TREQ state each time TACK change state */
|
442 | 819e712b | bellard | if (s->b & TACK)
|
443 | 819e712b | bellard | s->b = (s->b | TREQ); |
444 | 819e712b | bellard | else
|
445 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
446 | 267002cd | bellard | s->ifr |= SR_INT; |
447 | 267002cd | bellard | cuda_update_irq(s); |
448 | 819e712b | bellard | } else {
|
449 | 819e712b | bellard | if (!(s->last_b & TIP)) {
|
450 | 819e712b | bellard | /* handle end of host to cuda transfert */
|
451 | 819e712b | bellard | packet_received = (s->data_out_index > 0);
|
452 | 819e712b | bellard | /* always an IRQ at the end of transfert */
|
453 | 819e712b | bellard | s->ifr |= SR_INT; |
454 | 819e712b | bellard | cuda_update_irq(s); |
455 | 819e712b | bellard | } |
456 | 819e712b | bellard | /* signal if there is data to read */
|
457 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
458 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
459 | 819e712b | bellard | } |
460 | 267002cd | bellard | } |
461 | 267002cd | bellard | } |
462 | 267002cd | bellard | |
463 | 267002cd | bellard | s->last_acr = s->acr; |
464 | 267002cd | bellard | s->last_b = s->b; |
465 | 819e712b | bellard | |
466 | 819e712b | bellard | /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
467 | 819e712b | bellard | recursively */
|
468 | 819e712b | bellard | if (packet_received) {
|
469 | 819e712b | bellard | len = s->data_out_index; |
470 | 819e712b | bellard | s->data_out_index = 0;
|
471 | 819e712b | bellard | cuda_receive_packet_from_host(s, s->data_out, len); |
472 | 819e712b | bellard | } |
473 | 267002cd | bellard | } |
474 | 267002cd | bellard | |
475 | 267002cd | bellard | static void cuda_send_packet_to_host(CUDAState *s, |
476 | 267002cd | bellard | const uint8_t *data, int len) |
477 | 267002cd | bellard | { |
478 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
479 | 819e712b | bellard | { |
480 | 819e712b | bellard | int i;
|
481 | 819e712b | bellard | printf("cuda_send_packet_to_host:\n");
|
482 | 819e712b | bellard | for(i = 0; i < len; i++) |
483 | 819e712b | bellard | printf(" %02x", data[i]);
|
484 | 819e712b | bellard | printf("\n");
|
485 | 819e712b | bellard | } |
486 | 819e712b | bellard | #endif
|
487 | 267002cd | bellard | memcpy(s->data_in, data, len); |
488 | 267002cd | bellard | s->data_in_size = len; |
489 | 267002cd | bellard | s->data_in_index = 0;
|
490 | 267002cd | bellard | cuda_update(s); |
491 | 267002cd | bellard | s->ifr |= SR_INT; |
492 | 267002cd | bellard | cuda_update_irq(s); |
493 | 267002cd | bellard | } |
494 | 267002cd | bellard | |
495 | 7db4eea6 | bellard | static void cuda_adb_poll(void *opaque) |
496 | e2733d20 | bellard | { |
497 | e2733d20 | bellard | CUDAState *s = opaque; |
498 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
499 | e2733d20 | bellard | int olen;
|
500 | e2733d20 | bellard | |
501 | e2733d20 | bellard | olen = adb_poll(&adb_bus, obuf + 2);
|
502 | e2733d20 | bellard | if (olen > 0) { |
503 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
504 | e2733d20 | bellard | obuf[1] = 0x40; /* polled data */ |
505 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
506 | e2733d20 | bellard | } |
507 | e2733d20 | bellard | qemu_mod_timer(s->adb_poll_timer, |
508 | e2733d20 | bellard | qemu_get_clock(vm_clock) + |
509 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
510 | e2733d20 | bellard | } |
511 | e2733d20 | bellard | |
512 | 267002cd | bellard | static void cuda_receive_packet(CUDAState *s, |
513 | 267002cd | bellard | const uint8_t *data, int len) |
514 | 267002cd | bellard | { |
515 | 267002cd | bellard | uint8_t obuf[16];
|
516 | e2733d20 | bellard | int ti, autopoll;
|
517 | 267002cd | bellard | |
518 | 267002cd | bellard | switch(data[0]) { |
519 | 267002cd | bellard | case CUDA_AUTOPOLL:
|
520 | e2733d20 | bellard | autopoll = (data[1] != 0); |
521 | e2733d20 | bellard | if (autopoll != s->autopoll) {
|
522 | e2733d20 | bellard | s->autopoll = autopoll; |
523 | e2733d20 | bellard | if (autopoll) {
|
524 | e2733d20 | bellard | qemu_mod_timer(s->adb_poll_timer, |
525 | e2733d20 | bellard | qemu_get_clock(vm_clock) + |
526 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
527 | e2733d20 | bellard | } else {
|
528 | e2733d20 | bellard | qemu_del_timer(s->adb_poll_timer); |
529 | e2733d20 | bellard | } |
530 | e2733d20 | bellard | } |
531 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
532 | 267002cd | bellard | obuf[1] = data[1]; |
533 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
534 | 267002cd | bellard | break;
|
535 | 267002cd | bellard | case CUDA_GET_TIME:
|
536 | dccfafc4 | bellard | case CUDA_SET_TIME:
|
537 | 267002cd | bellard | /* XXX: add time support ? */
|
538 | d7ce296f | bellard | ti = time(NULL) + RTC_OFFSET;
|
539 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
540 | 267002cd | bellard | obuf[1] = 0; |
541 | 267002cd | bellard | obuf[2] = 0; |
542 | 267002cd | bellard | obuf[3] = ti >> 24; |
543 | 267002cd | bellard | obuf[4] = ti >> 16; |
544 | 267002cd | bellard | obuf[5] = ti >> 8; |
545 | 267002cd | bellard | obuf[6] = ti;
|
546 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 7);
|
547 | 267002cd | bellard | break;
|
548 | 267002cd | bellard | case CUDA_FILE_SERVER_FLAG:
|
549 | 267002cd | bellard | case CUDA_SET_DEVICE_LIST:
|
550 | 267002cd | bellard | case CUDA_SET_AUTO_RATE:
|
551 | 267002cd | bellard | case CUDA_SET_POWER_MESSAGES:
|
552 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
553 | 267002cd | bellard | obuf[1] = 0; |
554 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
555 | 267002cd | bellard | break;
|
556 | d7ce296f | bellard | case CUDA_POWERDOWN:
|
557 | d7ce296f | bellard | obuf[0] = CUDA_PACKET;
|
558 | d7ce296f | bellard | obuf[1] = 0; |
559 | d7ce296f | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
560 | d7ce296f | bellard | qemu_system_shutdown_request(); |
561 | d7ce296f | bellard | break;
|
562 | 267002cd | bellard | default:
|
563 | 267002cd | bellard | break;
|
564 | 267002cd | bellard | } |
565 | 267002cd | bellard | } |
566 | 267002cd | bellard | |
567 | 267002cd | bellard | static void cuda_receive_packet_from_host(CUDAState *s, |
568 | 267002cd | bellard | const uint8_t *data, int len) |
569 | 267002cd | bellard | { |
570 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
571 | 819e712b | bellard | { |
572 | 819e712b | bellard | int i;
|
573 | cadae95f | bellard | printf("cuda_receive_packet_from_host:\n");
|
574 | 819e712b | bellard | for(i = 0; i < len; i++) |
575 | 819e712b | bellard | printf(" %02x", data[i]);
|
576 | 819e712b | bellard | printf("\n");
|
577 | 819e712b | bellard | } |
578 | 819e712b | bellard | #endif
|
579 | 267002cd | bellard | switch(data[0]) { |
580 | 267002cd | bellard | case ADB_PACKET:
|
581 | e2733d20 | bellard | { |
582 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
583 | e2733d20 | bellard | int olen;
|
584 | e2733d20 | bellard | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
585 | 38f0b147 | bellard | if (olen > 0) { |
586 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
587 | e2733d20 | bellard | obuf[1] = 0x00; |
588 | e2733d20 | bellard | } else {
|
589 | 38f0b147 | bellard | /* error */
|
590 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
591 | 38f0b147 | bellard | obuf[1] = -olen;
|
592 | 38f0b147 | bellard | olen = 0;
|
593 | e2733d20 | bellard | } |
594 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
595 | e2733d20 | bellard | } |
596 | 267002cd | bellard | break;
|
597 | 267002cd | bellard | case CUDA_PACKET:
|
598 | 267002cd | bellard | cuda_receive_packet(s, data + 1, len - 1); |
599 | 267002cd | bellard | break;
|
600 | 267002cd | bellard | } |
601 | 267002cd | bellard | } |
602 | 267002cd | bellard | |
603 | 267002cd | bellard | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
604 | 267002cd | bellard | { |
605 | 267002cd | bellard | } |
606 | 267002cd | bellard | |
607 | 267002cd | bellard | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
608 | 267002cd | bellard | { |
609 | 267002cd | bellard | } |
610 | 267002cd | bellard | |
611 | 267002cd | bellard | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
612 | 267002cd | bellard | { |
613 | 267002cd | bellard | return 0; |
614 | 267002cd | bellard | } |
615 | 267002cd | bellard | |
616 | 267002cd | bellard | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
617 | 267002cd | bellard | { |
618 | 267002cd | bellard | return 0; |
619 | 267002cd | bellard | } |
620 | 267002cd | bellard | |
621 | 267002cd | bellard | static CPUWriteMemoryFunc *cuda_write[] = {
|
622 | 267002cd | bellard | &cuda_writeb, |
623 | 267002cd | bellard | &cuda_writew, |
624 | 267002cd | bellard | &cuda_writel, |
625 | 267002cd | bellard | }; |
626 | 267002cd | bellard | |
627 | 267002cd | bellard | static CPUReadMemoryFunc *cuda_read[] = {
|
628 | 267002cd | bellard | &cuda_readb, |
629 | 267002cd | bellard | &cuda_readw, |
630 | 267002cd | bellard | &cuda_readl, |
631 | 267002cd | bellard | }; |
632 | 267002cd | bellard | |
633 | cadae95f | bellard | int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq) |
634 | 267002cd | bellard | { |
635 | 267002cd | bellard | CUDAState *s = &cuda_state; |
636 | 267002cd | bellard | int cuda_mem_index;
|
637 | 267002cd | bellard | |
638 | cadae95f | bellard | s->set_irq = set_irq; |
639 | cadae95f | bellard | s->irq_opaque = irq_opaque; |
640 | 819e712b | bellard | s->irq = irq; |
641 | 819e712b | bellard | |
642 | 61271e5c | bellard | s->timers[0].index = 0; |
643 | 267002cd | bellard | s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
644 | 61271e5c | bellard | s->timers[0].latch = 0xffff; |
645 | 819e712b | bellard | set_counter(s, &s->timers[0], 0xffff); |
646 | 61271e5c | bellard | |
647 | 61271e5c | bellard | s->timers[1].index = 1; |
648 | 61271e5c | bellard | s->timers[1].latch = 0; |
649 | cadae95f | bellard | // s->ier = T1_INT | SR_INT;
|
650 | cadae95f | bellard | s->ier = 0;
|
651 | 819e712b | bellard | set_counter(s, &s->timers[1], 0xffff); |
652 | e2733d20 | bellard | |
653 | e2733d20 | bellard | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
654 | 267002cd | bellard | cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
655 | 267002cd | bellard | return cuda_mem_index;
|
656 | 267002cd | bellard | } |