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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU NE2000 emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | /* debug NE2000 card */
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27 | 80cabfad | bellard | //#define DEBUG_NE2000
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28 | 80cabfad | bellard | |
29 | b41a2cd1 | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
32 | 80cabfad | bellard | /* Page 0 register offsets. */
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33 | 80cabfad | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
34 | 80cabfad | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
35 | 80cabfad | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
36 | 80cabfad | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
37 | 80cabfad | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
38 | 80cabfad | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
39 | 80cabfad | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
40 | 80cabfad | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
41 | 80cabfad | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
42 | 80cabfad | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
43 | 80cabfad | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
44 | 80cabfad | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
45 | 80cabfad | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
46 | 80cabfad | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
47 | 80cabfad | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
48 | 80cabfad | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
49 | 80cabfad | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
50 | 089af991 | bellard | #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
51 | 80cabfad | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
52 | 089af991 | bellard | #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
53 | 80cabfad | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
54 | 80cabfad | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
55 | 80cabfad | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
56 | 80cabfad | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
57 | 80cabfad | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
58 | 80cabfad | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
59 | 80cabfad | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
60 | 80cabfad | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
61 | 80cabfad | bellard | |
62 | 80cabfad | bellard | #define EN1_PHYS 0x11 |
63 | 80cabfad | bellard | #define EN1_CURPAG 0x17 |
64 | 80cabfad | bellard | #define EN1_MULT 0x18 |
65 | 80cabfad | bellard | |
66 | a343df16 | bellard | #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
67 | a343df16 | bellard | #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
68 | a343df16 | bellard | |
69 | 089af991 | bellard | #define EN3_CONFIG0 0x33 |
70 | 089af991 | bellard | #define EN3_CONFIG1 0x34 |
71 | 089af991 | bellard | #define EN3_CONFIG2 0x35 |
72 | 089af991 | bellard | #define EN3_CONFIG3 0x36 |
73 | 089af991 | bellard | |
74 | 80cabfad | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
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75 | 80cabfad | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
76 | 80cabfad | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
77 | 80cabfad | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
78 | 80cabfad | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
79 | 80cabfad | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
80 | 80cabfad | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
81 | 80cabfad | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
82 | 80cabfad | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
83 | 80cabfad | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
84 | 80cabfad | bellard | |
85 | 80cabfad | bellard | /* Bits in EN0_ISR - Interrupt status register */
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86 | 80cabfad | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
87 | 80cabfad | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
88 | 80cabfad | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
89 | 80cabfad | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
90 | 80cabfad | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
91 | 80cabfad | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
92 | 80cabfad | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
93 | 80cabfad | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
94 | 80cabfad | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
95 | 80cabfad | bellard | |
96 | 80cabfad | bellard | /* Bits in received packet status byte and EN0_RSR*/
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97 | 80cabfad | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
98 | 80cabfad | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
99 | 80cabfad | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
100 | 80cabfad | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
101 | 80cabfad | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
102 | 80cabfad | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
103 | 80cabfad | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
104 | 80cabfad | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
105 | 80cabfad | bellard | |
106 | 80cabfad | bellard | /* Transmitted packet status, EN0_TSR. */
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107 | 80cabfad | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
108 | 80cabfad | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
109 | 80cabfad | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
110 | 80cabfad | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
111 | 80cabfad | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
112 | 80cabfad | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
113 | 80cabfad | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
114 | 80cabfad | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
115 | 80cabfad | bellard | |
116 | ee9dbb29 | bellard | #define NE2000_PMEM_SIZE (32*1024) |
117 | ee9dbb29 | bellard | #define NE2000_PMEM_START (16*1024) |
118 | ee9dbb29 | bellard | #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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119 | ee9dbb29 | bellard | #define NE2000_MEM_SIZE NE2000_PMEM_END
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120 | 80cabfad | bellard | |
121 | 80cabfad | bellard | typedef struct NE2000State { |
122 | 80cabfad | bellard | uint8_t cmd; |
123 | 80cabfad | bellard | uint32_t start; |
124 | 80cabfad | bellard | uint32_t stop; |
125 | 80cabfad | bellard | uint8_t boundary; |
126 | 80cabfad | bellard | uint8_t tsr; |
127 | 80cabfad | bellard | uint8_t tpsr; |
128 | 80cabfad | bellard | uint16_t tcnt; |
129 | 80cabfad | bellard | uint16_t rcnt; |
130 | 80cabfad | bellard | uint32_t rsar; |
131 | 8d6c7eb8 | bellard | uint8_t rsr; |
132 | 7c9d8e07 | bellard | uint8_t rxcr; |
133 | 80cabfad | bellard | uint8_t isr; |
134 | 80cabfad | bellard | uint8_t dcfg; |
135 | 80cabfad | bellard | uint8_t imr; |
136 | 80cabfad | bellard | uint8_t phys[6]; /* mac address */ |
137 | 80cabfad | bellard | uint8_t curpag; |
138 | 80cabfad | bellard | uint8_t mult[8]; /* multicast mask array */ |
139 | 80cabfad | bellard | int irq;
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140 | 4a9c9687 | bellard | PCIDevice *pci_dev; |
141 | 7c9d8e07 | bellard | VLANClientState *vc; |
142 | 7c9d8e07 | bellard | uint8_t macaddr[6];
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143 | 80cabfad | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
144 | 80cabfad | bellard | } NE2000State; |
145 | 80cabfad | bellard | |
146 | 80cabfad | bellard | static void ne2000_reset(NE2000State *s) |
147 | 80cabfad | bellard | { |
148 | 80cabfad | bellard | int i;
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149 | 80cabfad | bellard | |
150 | 80cabfad | bellard | s->isr = ENISR_RESET; |
151 | 7c9d8e07 | bellard | memcpy(s->mem, s->macaddr, 6);
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152 | 80cabfad | bellard | s->mem[14] = 0x57; |
153 | 80cabfad | bellard | s->mem[15] = 0x57; |
154 | 80cabfad | bellard | |
155 | 80cabfad | bellard | /* duplicate prom data */
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156 | 80cabfad | bellard | for(i = 15;i >= 0; i--) { |
157 | 80cabfad | bellard | s->mem[2 * i] = s->mem[i];
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158 | 80cabfad | bellard | s->mem[2 * i + 1] = s->mem[i]; |
159 | 80cabfad | bellard | } |
160 | 80cabfad | bellard | } |
161 | 80cabfad | bellard | |
162 | 80cabfad | bellard | static void ne2000_update_irq(NE2000State *s) |
163 | 80cabfad | bellard | { |
164 | 80cabfad | bellard | int isr;
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165 | a343df16 | bellard | isr = (s->isr & s->imr) & 0x7f;
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166 | a541f297 | bellard | #if defined(DEBUG_NE2000)
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167 | a541f297 | bellard | printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
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168 | a541f297 | bellard | s->irq, isr ? 1 : 0, s->isr, s->imr); |
169 | a541f297 | bellard | #endif
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170 | 4a9c9687 | bellard | if (s->irq == 16) { |
171 | 4a9c9687 | bellard | /* PCI irq */
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172 | 4a9c9687 | bellard | pci_set_irq(s->pci_dev, 0, (isr != 0)); |
173 | 4a9c9687 | bellard | } else {
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174 | 4a9c9687 | bellard | /* ISA irq */
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175 | 4a9c9687 | bellard | pic_set_irq(s->irq, (isr != 0));
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176 | 4a9c9687 | bellard | } |
177 | 80cabfad | bellard | } |
178 | 80cabfad | bellard | |
179 | 7c9d8e07 | bellard | #define POLYNOMIAL 0x04c11db6 |
180 | 7c9d8e07 | bellard | |
181 | 7c9d8e07 | bellard | /* From FreeBSD */
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182 | 7c9d8e07 | bellard | /* XXX: optimize */
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183 | 7c9d8e07 | bellard | static int compute_mcast_idx(const uint8_t *ep) |
184 | 7c9d8e07 | bellard | { |
185 | 7c9d8e07 | bellard | uint32_t crc; |
186 | 7c9d8e07 | bellard | int carry, i, j;
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187 | 7c9d8e07 | bellard | uint8_t b; |
188 | 7c9d8e07 | bellard | |
189 | 7c9d8e07 | bellard | crc = 0xffffffff;
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190 | 7c9d8e07 | bellard | for (i = 0; i < 6; i++) { |
191 | 7c9d8e07 | bellard | b = *ep++; |
192 | 7c9d8e07 | bellard | for (j = 0; j < 8; j++) { |
193 | 7c9d8e07 | bellard | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
194 | 7c9d8e07 | bellard | crc <<= 1;
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195 | 7c9d8e07 | bellard | b >>= 1;
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196 | 7c9d8e07 | bellard | if (carry)
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197 | 7c9d8e07 | bellard | crc = ((crc ^ POLYNOMIAL) | carry); |
198 | 7c9d8e07 | bellard | } |
199 | 7c9d8e07 | bellard | } |
200 | 7c9d8e07 | bellard | return (crc >> 26); |
201 | 7c9d8e07 | bellard | } |
202 | 7c9d8e07 | bellard | |
203 | d861b05e | pbrook | static int ne2000_buffer_full(NE2000State *s) |
204 | 80cabfad | bellard | { |
205 | 80cabfad | bellard | int avail, index, boundary;
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206 | d861b05e | pbrook | |
207 | 80cabfad | bellard | index = s->curpag << 8;
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208 | 80cabfad | bellard | boundary = s->boundary << 8;
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209 | 28c1c656 | ths | if (index < boundary)
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210 | 80cabfad | bellard | avail = boundary - index; |
211 | 80cabfad | bellard | else
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212 | 80cabfad | bellard | avail = (s->stop - s->start) - (index - boundary); |
213 | 80cabfad | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
214 | d861b05e | pbrook | return 1; |
215 | d861b05e | pbrook | return 0; |
216 | d861b05e | pbrook | } |
217 | d861b05e | pbrook | |
218 | d861b05e | pbrook | static int ne2000_can_receive(void *opaque) |
219 | d861b05e | pbrook | { |
220 | d861b05e | pbrook | NE2000State *s = opaque; |
221 | d861b05e | pbrook | |
222 | d861b05e | pbrook | if (s->cmd & E8390_STOP)
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223 | d861b05e | pbrook | return 1; |
224 | d861b05e | pbrook | return !ne2000_buffer_full(s);
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225 | 80cabfad | bellard | } |
226 | 80cabfad | bellard | |
227 | b41a2cd1 | bellard | #define MIN_BUF_SIZE 60 |
228 | b41a2cd1 | bellard | |
229 | b41a2cd1 | bellard | static void ne2000_receive(void *opaque, const uint8_t *buf, int size) |
230 | 80cabfad | bellard | { |
231 | b41a2cd1 | bellard | NE2000State *s = opaque; |
232 | 80cabfad | bellard | uint8_t *p; |
233 | 7c9d8e07 | bellard | int total_len, next, avail, len, index, mcast_idx;
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234 | b41a2cd1 | bellard | uint8_t buf1[60];
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235 | 7c9d8e07 | bellard | static const uint8_t broadcast_macaddr[6] = |
236 | 7c9d8e07 | bellard | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
237 | b41a2cd1 | bellard | |
238 | 80cabfad | bellard | #if defined(DEBUG_NE2000)
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239 | 80cabfad | bellard | printf("NE2000: received len=%d\n", size);
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240 | 80cabfad | bellard | #endif
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241 | 80cabfad | bellard | |
242 | d861b05e | pbrook | if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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243 | 7c9d8e07 | bellard | return;
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244 | 7c9d8e07 | bellard | |
245 | 7c9d8e07 | bellard | /* XXX: check this */
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246 | 7c9d8e07 | bellard | if (s->rxcr & 0x10) { |
247 | 7c9d8e07 | bellard | /* promiscuous: receive all */
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248 | 7c9d8e07 | bellard | } else {
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249 | 7c9d8e07 | bellard | if (!memcmp(buf, broadcast_macaddr, 6)) { |
250 | 7c9d8e07 | bellard | /* broadcast address */
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251 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x04)) |
252 | 7c9d8e07 | bellard | return;
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253 | 7c9d8e07 | bellard | } else if (buf[0] & 0x01) { |
254 | 7c9d8e07 | bellard | /* multicast */
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255 | 7c9d8e07 | bellard | if (!(s->rxcr & 0x08)) |
256 | 7c9d8e07 | bellard | return;
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257 | 7c9d8e07 | bellard | mcast_idx = compute_mcast_idx(buf); |
258 | 7c9d8e07 | bellard | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
259 | 7c9d8e07 | bellard | return;
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260 | 7c9d8e07 | bellard | } else if (s->mem[0] == buf[0] && |
261 | 7c9d8e07 | bellard | s->mem[2] == buf[1] && |
262 | 7c9d8e07 | bellard | s->mem[4] == buf[2] && |
263 | 7c9d8e07 | bellard | s->mem[6] == buf[3] && |
264 | 7c9d8e07 | bellard | s->mem[8] == buf[4] && |
265 | 7c9d8e07 | bellard | s->mem[10] == buf[5]) { |
266 | 7c9d8e07 | bellard | /* match */
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267 | 7c9d8e07 | bellard | } else {
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268 | 7c9d8e07 | bellard | return;
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269 | 7c9d8e07 | bellard | } |
270 | 7c9d8e07 | bellard | } |
271 | 7c9d8e07 | bellard | |
272 | 7c9d8e07 | bellard | |
273 | b41a2cd1 | bellard | /* if too small buffer, then expand it */
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274 | b41a2cd1 | bellard | if (size < MIN_BUF_SIZE) {
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275 | b41a2cd1 | bellard | memcpy(buf1, buf, size); |
276 | b41a2cd1 | bellard | memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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277 | b41a2cd1 | bellard | buf = buf1; |
278 | b41a2cd1 | bellard | size = MIN_BUF_SIZE; |
279 | b41a2cd1 | bellard | } |
280 | b41a2cd1 | bellard | |
281 | 80cabfad | bellard | index = s->curpag << 8;
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282 | 80cabfad | bellard | /* 4 bytes for header */
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283 | 80cabfad | bellard | total_len = size + 4;
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284 | 80cabfad | bellard | /* address for next packet (4 bytes for CRC) */
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285 | 80cabfad | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
286 | 80cabfad | bellard | if (next >= s->stop)
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287 | 80cabfad | bellard | next -= (s->stop - s->start); |
288 | 80cabfad | bellard | /* prepare packet header */
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289 | 80cabfad | bellard | p = s->mem + index; |
290 | 8d6c7eb8 | bellard | s->rsr = ENRSR_RXOK; /* receive status */
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291 | 8d6c7eb8 | bellard | /* XXX: check this */
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292 | 8d6c7eb8 | bellard | if (buf[0] & 0x01) |
293 | 8d6c7eb8 | bellard | s->rsr |= ENRSR_PHY; |
294 | 8d6c7eb8 | bellard | p[0] = s->rsr;
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295 | 80cabfad | bellard | p[1] = next >> 8; |
296 | 80cabfad | bellard | p[2] = total_len;
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297 | 80cabfad | bellard | p[3] = total_len >> 8; |
298 | 80cabfad | bellard | index += 4;
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299 | 80cabfad | bellard | |
300 | 80cabfad | bellard | /* write packet data */
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301 | 80cabfad | bellard | while (size > 0) { |
302 | 80cabfad | bellard | avail = s->stop - index; |
303 | 80cabfad | bellard | len = size; |
304 | 80cabfad | bellard | if (len > avail)
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305 | 80cabfad | bellard | len = avail; |
306 | 80cabfad | bellard | memcpy(s->mem + index, buf, len); |
307 | 80cabfad | bellard | buf += len; |
308 | 80cabfad | bellard | index += len; |
309 | 80cabfad | bellard | if (index == s->stop)
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310 | 80cabfad | bellard | index = s->start; |
311 | 80cabfad | bellard | size -= len; |
312 | 80cabfad | bellard | } |
313 | 80cabfad | bellard | s->curpag = next >> 8;
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314 | 8d6c7eb8 | bellard | |
315 | 9f083493 | ths | /* now we can signal we have received something */
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316 | 80cabfad | bellard | s->isr |= ENISR_RX; |
317 | 80cabfad | bellard | ne2000_update_irq(s); |
318 | 80cabfad | bellard | } |
319 | 80cabfad | bellard | |
320 | b41a2cd1 | bellard | static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
321 | 80cabfad | bellard | { |
322 | b41a2cd1 | bellard | NE2000State *s = opaque; |
323 | 40545f84 | bellard | int offset, page, index;
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324 | 80cabfad | bellard | |
325 | 80cabfad | bellard | addr &= 0xf;
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326 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
327 | 80cabfad | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
328 | 80cabfad | bellard | #endif
|
329 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
330 | 80cabfad | bellard | /* control register */
|
331 | 80cabfad | bellard | s->cmd = val; |
332 | a343df16 | bellard | if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
333 | ee9dbb29 | bellard | s->isr &= ~ENISR_RESET; |
334 | 80cabfad | bellard | /* test specific case: zero length transfert */
|
335 | 80cabfad | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
336 | 80cabfad | bellard | s->rcnt == 0) {
|
337 | 80cabfad | bellard | s->isr |= ENISR_RDC; |
338 | 80cabfad | bellard | ne2000_update_irq(s); |
339 | 80cabfad | bellard | } |
340 | 80cabfad | bellard | if (val & E8390_TRANS) {
|
341 | 40545f84 | bellard | index = (s->tpsr << 8);
|
342 | 40545f84 | bellard | /* XXX: next 2 lines are a hack to make netware 3.11 work */
|
343 | 40545f84 | bellard | if (index >= NE2000_PMEM_END)
|
344 | 40545f84 | bellard | index -= NE2000_PMEM_SIZE; |
345 | 40545f84 | bellard | /* fail safe: check range on the transmitted length */
|
346 | 40545f84 | bellard | if (index + s->tcnt <= NE2000_PMEM_END) {
|
347 | 7c9d8e07 | bellard | qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
348 | 40545f84 | bellard | } |
349 | 80cabfad | bellard | /* signal end of transfert */
|
350 | 80cabfad | bellard | s->tsr = ENTSR_PTX; |
351 | 80cabfad | bellard | s->isr |= ENISR_TX; |
352 | 40545f84 | bellard | s->cmd &= ~E8390_TRANS; |
353 | 80cabfad | bellard | ne2000_update_irq(s); |
354 | 80cabfad | bellard | } |
355 | 80cabfad | bellard | } |
356 | 80cabfad | bellard | } else {
|
357 | 80cabfad | bellard | page = s->cmd >> 6;
|
358 | 80cabfad | bellard | offset = addr | (page << 4);
|
359 | 80cabfad | bellard | switch(offset) {
|
360 | 80cabfad | bellard | case EN0_STARTPG:
|
361 | 80cabfad | bellard | s->start = val << 8;
|
362 | 80cabfad | bellard | break;
|
363 | 80cabfad | bellard | case EN0_STOPPG:
|
364 | 80cabfad | bellard | s->stop = val << 8;
|
365 | 80cabfad | bellard | break;
|
366 | 80cabfad | bellard | case EN0_BOUNDARY:
|
367 | 80cabfad | bellard | s->boundary = val; |
368 | 80cabfad | bellard | break;
|
369 | 80cabfad | bellard | case EN0_IMR:
|
370 | 80cabfad | bellard | s->imr = val; |
371 | 80cabfad | bellard | ne2000_update_irq(s); |
372 | 80cabfad | bellard | break;
|
373 | 80cabfad | bellard | case EN0_TPSR:
|
374 | 80cabfad | bellard | s->tpsr = val; |
375 | 80cabfad | bellard | break;
|
376 | 80cabfad | bellard | case EN0_TCNTLO:
|
377 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
378 | 80cabfad | bellard | break;
|
379 | 80cabfad | bellard | case EN0_TCNTHI:
|
380 | 80cabfad | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
381 | 80cabfad | bellard | break;
|
382 | 80cabfad | bellard | case EN0_RSARLO:
|
383 | 80cabfad | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
384 | 80cabfad | bellard | break;
|
385 | 80cabfad | bellard | case EN0_RSARHI:
|
386 | 80cabfad | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
387 | 80cabfad | bellard | break;
|
388 | 80cabfad | bellard | case EN0_RCNTLO:
|
389 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
390 | 80cabfad | bellard | break;
|
391 | 80cabfad | bellard | case EN0_RCNTHI:
|
392 | 80cabfad | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
393 | 80cabfad | bellard | break;
|
394 | 7c9d8e07 | bellard | case EN0_RXCR:
|
395 | 7c9d8e07 | bellard | s->rxcr = val; |
396 | 7c9d8e07 | bellard | break;
|
397 | 80cabfad | bellard | case EN0_DCFG:
|
398 | 80cabfad | bellard | s->dcfg = val; |
399 | 80cabfad | bellard | break;
|
400 | 80cabfad | bellard | case EN0_ISR:
|
401 | ee9dbb29 | bellard | s->isr &= ~(val & 0x7f);
|
402 | 80cabfad | bellard | ne2000_update_irq(s); |
403 | 80cabfad | bellard | break;
|
404 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
405 | 80cabfad | bellard | s->phys[offset - EN1_PHYS] = val; |
406 | 80cabfad | bellard | break;
|
407 | 80cabfad | bellard | case EN1_CURPAG:
|
408 | 80cabfad | bellard | s->curpag = val; |
409 | 80cabfad | bellard | break;
|
410 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
411 | 80cabfad | bellard | s->mult[offset - EN1_MULT] = val; |
412 | 80cabfad | bellard | break;
|
413 | 80cabfad | bellard | } |
414 | 80cabfad | bellard | } |
415 | 80cabfad | bellard | } |
416 | 80cabfad | bellard | |
417 | b41a2cd1 | bellard | static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
418 | 80cabfad | bellard | { |
419 | b41a2cd1 | bellard | NE2000State *s = opaque; |
420 | 80cabfad | bellard | int offset, page, ret;
|
421 | 80cabfad | bellard | |
422 | 80cabfad | bellard | addr &= 0xf;
|
423 | 80cabfad | bellard | if (addr == E8390_CMD) {
|
424 | 80cabfad | bellard | ret = s->cmd; |
425 | 80cabfad | bellard | } else {
|
426 | 80cabfad | bellard | page = s->cmd >> 6;
|
427 | 80cabfad | bellard | offset = addr | (page << 4);
|
428 | 80cabfad | bellard | switch(offset) {
|
429 | 80cabfad | bellard | case EN0_TSR:
|
430 | 80cabfad | bellard | ret = s->tsr; |
431 | 80cabfad | bellard | break;
|
432 | 80cabfad | bellard | case EN0_BOUNDARY:
|
433 | 80cabfad | bellard | ret = s->boundary; |
434 | 80cabfad | bellard | break;
|
435 | 80cabfad | bellard | case EN0_ISR:
|
436 | 80cabfad | bellard | ret = s->isr; |
437 | 80cabfad | bellard | break;
|
438 | ee9dbb29 | bellard | case EN0_RSARLO:
|
439 | ee9dbb29 | bellard | ret = s->rsar & 0x00ff;
|
440 | ee9dbb29 | bellard | break;
|
441 | ee9dbb29 | bellard | case EN0_RSARHI:
|
442 | ee9dbb29 | bellard | ret = s->rsar >> 8;
|
443 | ee9dbb29 | bellard | break;
|
444 | 80cabfad | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
445 | 80cabfad | bellard | ret = s->phys[offset - EN1_PHYS]; |
446 | 80cabfad | bellard | break;
|
447 | 80cabfad | bellard | case EN1_CURPAG:
|
448 | 80cabfad | bellard | ret = s->curpag; |
449 | 80cabfad | bellard | break;
|
450 | 80cabfad | bellard | case EN1_MULT ... EN1_MULT + 7: |
451 | 80cabfad | bellard | ret = s->mult[offset - EN1_MULT]; |
452 | 80cabfad | bellard | break;
|
453 | 8d6c7eb8 | bellard | case EN0_RSR:
|
454 | 8d6c7eb8 | bellard | ret = s->rsr; |
455 | 8d6c7eb8 | bellard | break;
|
456 | a343df16 | bellard | case EN2_STARTPG:
|
457 | a343df16 | bellard | ret = s->start >> 8;
|
458 | a343df16 | bellard | break;
|
459 | a343df16 | bellard | case EN2_STOPPG:
|
460 | a343df16 | bellard | ret = s->stop >> 8;
|
461 | a343df16 | bellard | break;
|
462 | 089af991 | bellard | case EN0_RTL8029ID0:
|
463 | 089af991 | bellard | ret = 0x50;
|
464 | 089af991 | bellard | break;
|
465 | 089af991 | bellard | case EN0_RTL8029ID1:
|
466 | 089af991 | bellard | ret = 0x43;
|
467 | 089af991 | bellard | break;
|
468 | 089af991 | bellard | case EN3_CONFIG0:
|
469 | 089af991 | bellard | ret = 0; /* 10baseT media */ |
470 | 089af991 | bellard | break;
|
471 | 089af991 | bellard | case EN3_CONFIG2:
|
472 | 089af991 | bellard | ret = 0x40; /* 10baseT active */ |
473 | 089af991 | bellard | break;
|
474 | 089af991 | bellard | case EN3_CONFIG3:
|
475 | 089af991 | bellard | ret = 0x40; /* Full duplex */ |
476 | 089af991 | bellard | break;
|
477 | 80cabfad | bellard | default:
|
478 | 80cabfad | bellard | ret = 0x00;
|
479 | 80cabfad | bellard | break;
|
480 | 80cabfad | bellard | } |
481 | 80cabfad | bellard | } |
482 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
483 | 80cabfad | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
484 | 80cabfad | bellard | #endif
|
485 | 80cabfad | bellard | return ret;
|
486 | 80cabfad | bellard | } |
487 | 80cabfad | bellard | |
488 | ee9dbb29 | bellard | static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
489 | 69b91039 | bellard | uint32_t val) |
490 | ee9dbb29 | bellard | { |
491 | ee9dbb29 | bellard | if (addr < 32 || |
492 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
493 | ee9dbb29 | bellard | s->mem[addr] = val; |
494 | ee9dbb29 | bellard | } |
495 | ee9dbb29 | bellard | } |
496 | ee9dbb29 | bellard | |
497 | ee9dbb29 | bellard | static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
498 | ee9dbb29 | bellard | uint32_t val) |
499 | ee9dbb29 | bellard | { |
500 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
501 | ee9dbb29 | bellard | if (addr < 32 || |
502 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
503 | 69b91039 | bellard | *(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
504 | 69b91039 | bellard | } |
505 | 69b91039 | bellard | } |
506 | 69b91039 | bellard | |
507 | 69b91039 | bellard | static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
508 | 69b91039 | bellard | uint32_t val) |
509 | 69b91039 | bellard | { |
510 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
511 | 69b91039 | bellard | if (addr < 32 || |
512 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
513 | 57ccbabe | bellard | cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
514 | ee9dbb29 | bellard | } |
515 | ee9dbb29 | bellard | } |
516 | ee9dbb29 | bellard | |
517 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
518 | ee9dbb29 | bellard | { |
519 | ee9dbb29 | bellard | if (addr < 32 || |
520 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
521 | ee9dbb29 | bellard | return s->mem[addr];
|
522 | ee9dbb29 | bellard | } else {
|
523 | ee9dbb29 | bellard | return 0xff; |
524 | ee9dbb29 | bellard | } |
525 | ee9dbb29 | bellard | } |
526 | ee9dbb29 | bellard | |
527 | ee9dbb29 | bellard | static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
528 | ee9dbb29 | bellard | { |
529 | ee9dbb29 | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
530 | ee9dbb29 | bellard | if (addr < 32 || |
531 | ee9dbb29 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
532 | 69b91039 | bellard | return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
533 | ee9dbb29 | bellard | } else {
|
534 | ee9dbb29 | bellard | return 0xffff; |
535 | ee9dbb29 | bellard | } |
536 | ee9dbb29 | bellard | } |
537 | ee9dbb29 | bellard | |
538 | 69b91039 | bellard | static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
539 | 69b91039 | bellard | { |
540 | 57ccbabe | bellard | addr &= ~1; /* XXX: check exact behaviour if not even */ |
541 | 69b91039 | bellard | if (addr < 32 || |
542 | 69b91039 | bellard | (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { |
543 | 57ccbabe | bellard | return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
544 | 69b91039 | bellard | } else {
|
545 | 69b91039 | bellard | return 0xffffffff; |
546 | 69b91039 | bellard | } |
547 | 69b91039 | bellard | } |
548 | 69b91039 | bellard | |
549 | 3df3f6fd | bellard | static inline void ne2000_dma_update(NE2000State *s, int len) |
550 | 3df3f6fd | bellard | { |
551 | 3df3f6fd | bellard | s->rsar += len; |
552 | 3df3f6fd | bellard | /* wrap */
|
553 | 3df3f6fd | bellard | /* XXX: check what to do if rsar > stop */
|
554 | 3df3f6fd | bellard | if (s->rsar == s->stop)
|
555 | 3df3f6fd | bellard | s->rsar = s->start; |
556 | 3df3f6fd | bellard | |
557 | 3df3f6fd | bellard | if (s->rcnt <= len) {
|
558 | 3df3f6fd | bellard | s->rcnt = 0;
|
559 | 3df3f6fd | bellard | /* signal end of transfert */
|
560 | 3df3f6fd | bellard | s->isr |= ENISR_RDC; |
561 | 3df3f6fd | bellard | ne2000_update_irq(s); |
562 | 3df3f6fd | bellard | } else {
|
563 | 3df3f6fd | bellard | s->rcnt -= len; |
564 | 3df3f6fd | bellard | } |
565 | 3df3f6fd | bellard | } |
566 | 3df3f6fd | bellard | |
567 | b41a2cd1 | bellard | static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
568 | 80cabfad | bellard | { |
569 | b41a2cd1 | bellard | NE2000State *s = opaque; |
570 | 80cabfad | bellard | |
571 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
572 | 80cabfad | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
573 | 80cabfad | bellard | #endif
|
574 | ee9dbb29 | bellard | if (s->rcnt == 0) |
575 | 3df3f6fd | bellard | return;
|
576 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
577 | 80cabfad | bellard | /* 16 bit access */
|
578 | ee9dbb29 | bellard | ne2000_mem_writew(s, s->rsar, val); |
579 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
580 | 80cabfad | bellard | } else {
|
581 | 80cabfad | bellard | /* 8 bit access */
|
582 | ee9dbb29 | bellard | ne2000_mem_writeb(s, s->rsar, val); |
583 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
584 | 80cabfad | bellard | } |
585 | 80cabfad | bellard | } |
586 | 80cabfad | bellard | |
587 | b41a2cd1 | bellard | static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
588 | 80cabfad | bellard | { |
589 | b41a2cd1 | bellard | NE2000State *s = opaque; |
590 | 80cabfad | bellard | int ret;
|
591 | 80cabfad | bellard | |
592 | 80cabfad | bellard | if (s->dcfg & 0x01) { |
593 | 80cabfad | bellard | /* 16 bit access */
|
594 | ee9dbb29 | bellard | ret = ne2000_mem_readw(s, s->rsar); |
595 | 3df3f6fd | bellard | ne2000_dma_update(s, 2);
|
596 | 80cabfad | bellard | } else {
|
597 | 80cabfad | bellard | /* 8 bit access */
|
598 | ee9dbb29 | bellard | ret = ne2000_mem_readb(s, s->rsar); |
599 | 3df3f6fd | bellard | ne2000_dma_update(s, 1);
|
600 | 80cabfad | bellard | } |
601 | 80cabfad | bellard | #ifdef DEBUG_NE2000
|
602 | 80cabfad | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
603 | 80cabfad | bellard | #endif
|
604 | 80cabfad | bellard | return ret;
|
605 | 80cabfad | bellard | } |
606 | 80cabfad | bellard | |
607 | 69b91039 | bellard | static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
608 | 69b91039 | bellard | { |
609 | 69b91039 | bellard | NE2000State *s = opaque; |
610 | 69b91039 | bellard | |
611 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
612 | 69b91039 | bellard | printf("NE2000: asic writel val=0x%04x\n", val);
|
613 | 69b91039 | bellard | #endif
|
614 | 69b91039 | bellard | if (s->rcnt == 0) |
615 | 3df3f6fd | bellard | return;
|
616 | 69b91039 | bellard | /* 32 bit access */
|
617 | 69b91039 | bellard | ne2000_mem_writel(s, s->rsar, val); |
618 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
619 | 69b91039 | bellard | } |
620 | 69b91039 | bellard | |
621 | 69b91039 | bellard | static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
622 | 69b91039 | bellard | { |
623 | 69b91039 | bellard | NE2000State *s = opaque; |
624 | 69b91039 | bellard | int ret;
|
625 | 69b91039 | bellard | |
626 | 69b91039 | bellard | /* 32 bit access */
|
627 | 69b91039 | bellard | ret = ne2000_mem_readl(s, s->rsar); |
628 | 3df3f6fd | bellard | ne2000_dma_update(s, 4);
|
629 | 69b91039 | bellard | #ifdef DEBUG_NE2000
|
630 | 69b91039 | bellard | printf("NE2000: asic readl val=0x%04x\n", ret);
|
631 | 69b91039 | bellard | #endif
|
632 | 69b91039 | bellard | return ret;
|
633 | 69b91039 | bellard | } |
634 | 69b91039 | bellard | |
635 | b41a2cd1 | bellard | static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
636 | 80cabfad | bellard | { |
637 | 80cabfad | bellard | /* nothing to do (end of reset pulse) */
|
638 | 80cabfad | bellard | } |
639 | 80cabfad | bellard | |
640 | b41a2cd1 | bellard | static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
641 | 80cabfad | bellard | { |
642 | b41a2cd1 | bellard | NE2000State *s = opaque; |
643 | 80cabfad | bellard | ne2000_reset(s); |
644 | 80cabfad | bellard | return 0; |
645 | 80cabfad | bellard | } |
646 | 80cabfad | bellard | |
647 | 30ca2aab | bellard | static void ne2000_save(QEMUFile* f,void* opaque) |
648 | 30ca2aab | bellard | { |
649 | 30ca2aab | bellard | NE2000State* s=(NE2000State*)opaque; |
650 | 30ca2aab | bellard | |
651 | 1941d19c | bellard | if (s->pci_dev)
|
652 | 1941d19c | bellard | pci_device_save(s->pci_dev, f); |
653 | 1941d19c | bellard | |
654 | acff9df6 | bellard | qemu_put_8s(f, &s->rxcr); |
655 | acff9df6 | bellard | |
656 | 30ca2aab | bellard | qemu_put_8s(f, &s->cmd); |
657 | 30ca2aab | bellard | qemu_put_be32s(f, &s->start); |
658 | 30ca2aab | bellard | qemu_put_be32s(f, &s->stop); |
659 | 30ca2aab | bellard | qemu_put_8s(f, &s->boundary); |
660 | 30ca2aab | bellard | qemu_put_8s(f, &s->tsr); |
661 | 30ca2aab | bellard | qemu_put_8s(f, &s->tpsr); |
662 | 30ca2aab | bellard | qemu_put_be16s(f, &s->tcnt); |
663 | 30ca2aab | bellard | qemu_put_be16s(f, &s->rcnt); |
664 | 30ca2aab | bellard | qemu_put_be32s(f, &s->rsar); |
665 | 30ca2aab | bellard | qemu_put_8s(f, &s->rsr); |
666 | 30ca2aab | bellard | qemu_put_8s(f, &s->isr); |
667 | 30ca2aab | bellard | qemu_put_8s(f, &s->dcfg); |
668 | 30ca2aab | bellard | qemu_put_8s(f, &s->imr); |
669 | 30ca2aab | bellard | qemu_put_buffer(f, s->phys, 6);
|
670 | 30ca2aab | bellard | qemu_put_8s(f, &s->curpag); |
671 | 30ca2aab | bellard | qemu_put_buffer(f, s->mult, 8);
|
672 | 30ca2aab | bellard | qemu_put_be32s(f, &s->irq); |
673 | 30ca2aab | bellard | qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
674 | 30ca2aab | bellard | } |
675 | 30ca2aab | bellard | |
676 | 30ca2aab | bellard | static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
677 | 30ca2aab | bellard | { |
678 | 30ca2aab | bellard | NE2000State* s=(NE2000State*)opaque; |
679 | 1941d19c | bellard | int ret;
|
680 | 1941d19c | bellard | |
681 | 1941d19c | bellard | if (version_id > 3) |
682 | 1941d19c | bellard | return -EINVAL;
|
683 | 1941d19c | bellard | |
684 | 1941d19c | bellard | if (s->pci_dev && version_id >= 3) { |
685 | 1941d19c | bellard | ret = pci_device_load(s->pci_dev, f); |
686 | 1941d19c | bellard | if (ret < 0) |
687 | 1941d19c | bellard | return ret;
|
688 | 1941d19c | bellard | } |
689 | 30ca2aab | bellard | |
690 | 1941d19c | bellard | if (version_id >= 2) { |
691 | acff9df6 | bellard | qemu_get_8s(f, &s->rxcr); |
692 | acff9df6 | bellard | } else {
|
693 | 1941d19c | bellard | s->rxcr = 0x0c;
|
694 | acff9df6 | bellard | } |
695 | 30ca2aab | bellard | |
696 | 30ca2aab | bellard | qemu_get_8s(f, &s->cmd); |
697 | 30ca2aab | bellard | qemu_get_be32s(f, &s->start); |
698 | 30ca2aab | bellard | qemu_get_be32s(f, &s->stop); |
699 | 30ca2aab | bellard | qemu_get_8s(f, &s->boundary); |
700 | 30ca2aab | bellard | qemu_get_8s(f, &s->tsr); |
701 | 30ca2aab | bellard | qemu_get_8s(f, &s->tpsr); |
702 | 30ca2aab | bellard | qemu_get_be16s(f, &s->tcnt); |
703 | 30ca2aab | bellard | qemu_get_be16s(f, &s->rcnt); |
704 | 30ca2aab | bellard | qemu_get_be32s(f, &s->rsar); |
705 | 30ca2aab | bellard | qemu_get_8s(f, &s->rsr); |
706 | 30ca2aab | bellard | qemu_get_8s(f, &s->isr); |
707 | 30ca2aab | bellard | qemu_get_8s(f, &s->dcfg); |
708 | 30ca2aab | bellard | qemu_get_8s(f, &s->imr); |
709 | 30ca2aab | bellard | qemu_get_buffer(f, s->phys, 6);
|
710 | 30ca2aab | bellard | qemu_get_8s(f, &s->curpag); |
711 | 30ca2aab | bellard | qemu_get_buffer(f, s->mult, 8);
|
712 | 30ca2aab | bellard | qemu_get_be32s(f, &s->irq); |
713 | 30ca2aab | bellard | qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
714 | 30ca2aab | bellard | |
715 | 30ca2aab | bellard | return 0; |
716 | 30ca2aab | bellard | } |
717 | 30ca2aab | bellard | |
718 | 7c9d8e07 | bellard | void isa_ne2000_init(int base, int irq, NICInfo *nd) |
719 | 80cabfad | bellard | { |
720 | b41a2cd1 | bellard | NE2000State *s; |
721 | 7c9d8e07 | bellard | |
722 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(NE2000State));
|
723 | b41a2cd1 | bellard | if (!s)
|
724 | b41a2cd1 | bellard | return;
|
725 | b41a2cd1 | bellard | |
726 | b41a2cd1 | bellard | register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
727 | b41a2cd1 | bellard | register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
728 | 80cabfad | bellard | |
729 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
730 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
731 | b41a2cd1 | bellard | register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
732 | b41a2cd1 | bellard | register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
733 | 80cabfad | bellard | |
734 | b41a2cd1 | bellard | register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
735 | b41a2cd1 | bellard | register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
736 | 80cabfad | bellard | s->irq = irq; |
737 | 7c9d8e07 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
738 | 80cabfad | bellard | |
739 | 80cabfad | bellard | ne2000_reset(s); |
740 | b41a2cd1 | bellard | |
741 | d861b05e | pbrook | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
742 | d861b05e | pbrook | ne2000_can_receive, s); |
743 | 7c9d8e07 | bellard | |
744 | 7c9d8e07 | bellard | snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
745 | 7c9d8e07 | bellard | "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
746 | 7c9d8e07 | bellard | s->macaddr[0],
|
747 | 7c9d8e07 | bellard | s->macaddr[1],
|
748 | 7c9d8e07 | bellard | s->macaddr[2],
|
749 | 7c9d8e07 | bellard | s->macaddr[3],
|
750 | 7c9d8e07 | bellard | s->macaddr[4],
|
751 | 7c9d8e07 | bellard | s->macaddr[5]);
|
752 | 7c9d8e07 | bellard | |
753 | acff9df6 | bellard | register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s); |
754 | 80cabfad | bellard | } |
755 | 69b91039 | bellard | |
756 | 69b91039 | bellard | /***********************************************************/
|
757 | 69b91039 | bellard | /* PCI NE2000 definitions */
|
758 | 69b91039 | bellard | |
759 | 69b91039 | bellard | typedef struct PCINE2000State { |
760 | 69b91039 | bellard | PCIDevice dev; |
761 | 69b91039 | bellard | NE2000State ne2000; |
762 | 69b91039 | bellard | } PCINE2000State; |
763 | 69b91039 | bellard | |
764 | 69b91039 | bellard | static void ne2000_map(PCIDevice *pci_dev, int region_num, |
765 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type)
|
766 | 69b91039 | bellard | { |
767 | 69b91039 | bellard | PCINE2000State *d = (PCINE2000State *)pci_dev; |
768 | 69b91039 | bellard | NE2000State *s = &d->ne2000; |
769 | 69b91039 | bellard | |
770 | 69b91039 | bellard | register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
771 | 69b91039 | bellard | register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
772 | 69b91039 | bellard | |
773 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
774 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
775 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
776 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
777 | 69b91039 | bellard | register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
778 | 69b91039 | bellard | register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
779 | 69b91039 | bellard | |
780 | 69b91039 | bellard | register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
781 | 69b91039 | bellard | register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
782 | 69b91039 | bellard | } |
783 | 69b91039 | bellard | |
784 | abcebc7e | ths | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn) |
785 | 69b91039 | bellard | { |
786 | 69b91039 | bellard | PCINE2000State *d; |
787 | 69b91039 | bellard | NE2000State *s; |
788 | 69b91039 | bellard | uint8_t *pci_conf; |
789 | 69b91039 | bellard | |
790 | 46e50e9d | bellard | d = (PCINE2000State *)pci_register_device(bus, |
791 | 46e50e9d | bellard | "NE2000", sizeof(PCINE2000State), |
792 | abcebc7e | ths | devfn, |
793 | 4a9c9687 | bellard | NULL, NULL); |
794 | 69b91039 | bellard | pci_conf = d->dev.config; |
795 | 69b91039 | bellard | pci_conf[0x00] = 0xec; // Realtek 8029 |
796 | 69b91039 | bellard | pci_conf[0x01] = 0x10; |
797 | 69b91039 | bellard | pci_conf[0x02] = 0x29; |
798 | 69b91039 | bellard | pci_conf[0x03] = 0x80; |
799 | 69b91039 | bellard | pci_conf[0x0a] = 0x00; // ethernet network controller |
800 | 69b91039 | bellard | pci_conf[0x0b] = 0x02; |
801 | 69b91039 | bellard | pci_conf[0x0e] = 0x00; // header_type |
802 | 4a9c9687 | bellard | pci_conf[0x3d] = 1; // interrupt pin 0 |
803 | 69b91039 | bellard | |
804 | 30ca2aab | bellard | pci_register_io_region(&d->dev, 0, 0x100, |
805 | 69b91039 | bellard | PCI_ADDRESS_SPACE_IO, ne2000_map); |
806 | 69b91039 | bellard | s = &d->ne2000; |
807 | 4a9c9687 | bellard | s->irq = 16; // PCI interrupt |
808 | 4a9c9687 | bellard | s->pci_dev = (PCIDevice *)d; |
809 | 7c9d8e07 | bellard | memcpy(s->macaddr, nd->macaddr, 6);
|
810 | 69b91039 | bellard | ne2000_reset(s); |
811 | d861b05e | pbrook | s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, |
812 | d861b05e | pbrook | ne2000_can_receive, s); |
813 | 7c9d8e07 | bellard | |
814 | 7c9d8e07 | bellard | snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
815 | 7c9d8e07 | bellard | "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
816 | 7c9d8e07 | bellard | s->macaddr[0],
|
817 | 7c9d8e07 | bellard | s->macaddr[1],
|
818 | 7c9d8e07 | bellard | s->macaddr[2],
|
819 | 7c9d8e07 | bellard | s->macaddr[3],
|
820 | 7c9d8e07 | bellard | s->macaddr[4],
|
821 | 7c9d8e07 | bellard | s->macaddr[5]);
|
822 | 7c9d8e07 | bellard | |
823 | 30ca2aab | bellard | /* XXX: instance number ? */
|
824 | 1941d19c | bellard | register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s); |
825 | 69b91039 | bellard | } |