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/*
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* QEMU USB OHCI Emulation
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* Copyright (c) 2004 Gianni Tedesco
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* Copyright (c) 2006 CodeSourcery
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* TODO:
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* o Isochronous transfers
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* o Allocate bandwidth in frames properly
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* o Disable timers when nothing needs to be done, or remove timer usage
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* all together.
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* o Handle unrecoverable errors properly
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* o BIOS work to boot from USB storage
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*/
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#include "vl.h" |
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//#define DEBUG_OHCI
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/* Dump packet contents. */
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//#define DEBUG_PACKET
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
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#ifdef DEBUG_OHCI
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#define dprintf printf
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#else
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#define dprintf(...)
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#endif
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/* Number of Downstream Ports on the root hub. */
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#define OHCI_MAX_PORTS 15 |
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
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typedef struct OHCIPort { |
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USBPort port; |
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uint32_t ctrl; |
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} OHCIPort; |
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enum ohci_type {
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OHCI_TYPE_PCI, |
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OHCI_TYPE_PXA |
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}; |
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typedef struct { |
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void *pic;
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int irq;
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enum ohci_type type;
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target_phys_addr_t mem_base; |
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int mem;
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int num_ports;
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const char *name; |
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QEMUTimer *eof_timer; |
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int64_t sof_time; |
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/* OHCI state */
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/* Control partition */
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uint32_t ctl, status; |
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uint32_t intr_status; |
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uint32_t intr; |
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/* memory pointer partition */
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uint32_t hcca; |
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uint32_t ctrl_head, ctrl_cur; |
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uint32_t bulk_head, bulk_cur; |
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uint32_t per_cur; |
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uint32_t done; |
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int done_count;
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/* Frame counter partition */
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uint32_t fsmps:15;
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uint32_t fit:1;
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uint32_t fi:14;
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uint32_t frt:1;
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uint16_t frame_number; |
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uint16_t padding; |
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uint32_t pstart; |
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uint32_t lst; |
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/* Root Hub partition */
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uint32_t rhdesc_a, rhdesc_b; |
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uint32_t rhstatus; |
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OHCIPort rhport[OHCI_MAX_PORTS]; |
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/* PXA27x Non-OHCI events */
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uint32_t hstatus; |
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uint32_t hmask; |
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uint32_t hreset; |
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uint32_t htest; |
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/* Active packets. */
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uint32_t old_ctl; |
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USBPacket usb_packet; |
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uint8_t usb_buf[8192];
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uint32_t async_td; |
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int async_complete;
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|
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} OHCIState; |
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/* Host Controller Communications Area */
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struct ohci_hcca {
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uint32_t intr[32];
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uint16_t frame, pad; |
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uint32_t done; |
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}; |
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/* Bitfields for the first word of an Endpoint Desciptor. */
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#define OHCI_ED_FA_SHIFT 0 |
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#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) |
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#define OHCI_ED_EN_SHIFT 7 |
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#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) |
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#define OHCI_ED_D_SHIFT 11 |
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) |
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#define OHCI_ED_S (1<<13) |
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#define OHCI_ED_K (1<<14) |
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#define OHCI_ED_F (1<<15) |
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#define OHCI_ED_MPS_SHIFT 7 |
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#define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT) |
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/* Flags in the head field of an Endpoint Desciptor. */
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#define OHCI_ED_H 1 |
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#define OHCI_ED_C 2 |
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/* Bitfields for the first word of a Transfer Desciptor. */
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#define OHCI_TD_R (1<<18) |
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#define OHCI_TD_DP_SHIFT 19 |
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) |
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#define OHCI_TD_DI_SHIFT 21 |
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) |
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#define OHCI_TD_T0 (1<<24) |
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#define OHCI_TD_T1 (1<<24) |
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#define OHCI_TD_EC_SHIFT 26 |
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) |
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#define OHCI_TD_CC_SHIFT 28 |
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) |
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#define OHCI_DPTR_MASK 0xfffffff0 |
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) |
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#define OHCI_SET_BM(val, field, newval) do { \ |
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val &= ~OHCI_##field##_MASK; \ |
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ |
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} while(0) |
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/* endpoint descriptor */
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struct ohci_ed {
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uint32_t flags; |
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uint32_t tail; |
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uint32_t head; |
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uint32_t next; |
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}; |
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/* General transfer descriptor */
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struct ohci_td {
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uint32_t flags; |
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uint32_t cbp; |
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uint32_t next; |
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uint32_t be; |
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}; |
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#define USB_HZ 12000000 |
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/* OHCI Local stuff */
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#define OHCI_CTL_CBSR ((1<<0)|(1<<1)) |
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#define OHCI_CTL_PLE (1<<2) |
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#define OHCI_CTL_IE (1<<3) |
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#define OHCI_CTL_CLE (1<<4) |
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#define OHCI_CTL_BLE (1<<5) |
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#define OHCI_CTL_HCFS ((1<<6)|(1<<7)) |
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#define OHCI_USB_RESET 0x00 |
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#define OHCI_USB_RESUME 0x40 |
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#define OHCI_USB_OPERATIONAL 0x80 |
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#define OHCI_USB_SUSPEND 0xc0 |
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#define OHCI_CTL_IR (1<<8) |
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#define OHCI_CTL_RWC (1<<9) |
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#define OHCI_CTL_RWE (1<<10) |
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#define OHCI_STATUS_HCR (1<<0) |
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#define OHCI_STATUS_CLF (1<<1) |
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#define OHCI_STATUS_BLF (1<<2) |
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#define OHCI_STATUS_OCR (1<<3) |
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#define OHCI_STATUS_SOC ((1<<6)|(1<<7)) |
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#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ |
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#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ |
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#define OHCI_INTR_SF (1<<2) /* Start of frame */ |
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#define OHCI_INTR_RD (1<<3) /* Resume detect */ |
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#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ |
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#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ |
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#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ |
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#define OHCI_INTR_OC (1<<30) /* Ownership change */ |
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#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ |
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#define OHCI_HCCA_SIZE 0x100 |
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#define OHCI_HCCA_MASK 0xffffff00 |
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#define OHCI_EDPTR_MASK 0xfffffff0 |
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#define OHCI_FMI_FI 0x00003fff |
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#define OHCI_FMI_FSMPS 0xffff0000 |
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#define OHCI_FMI_FIT 0x80000000 |
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#define OHCI_FR_RT (1<<31) |
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#define OHCI_LS_THRESH 0x628 |
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#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ |
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#define OHCI_RHA_PSM (1<<8) |
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#define OHCI_RHA_NPS (1<<9) |
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#define OHCI_RHA_DT (1<<10) |
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#define OHCI_RHA_OCPM (1<<11) |
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#define OHCI_RHA_NOCP (1<<12) |
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#define OHCI_RHA_POTPGT_MASK 0xff000000 |
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#define OHCI_RHS_LPS (1<<0) |
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#define OHCI_RHS_OCI (1<<1) |
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#define OHCI_RHS_DRWE (1<<15) |
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#define OHCI_RHS_LPSC (1<<16) |
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#define OHCI_RHS_OCIC (1<<17) |
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#define OHCI_RHS_CRWE (1<<31) |
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#define OHCI_PORT_CCS (1<<0) |
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#define OHCI_PORT_PES (1<<1) |
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#define OHCI_PORT_PSS (1<<2) |
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#define OHCI_PORT_POCI (1<<3) |
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#define OHCI_PORT_PRS (1<<4) |
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#define OHCI_PORT_PPS (1<<8) |
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#define OHCI_PORT_LSDA (1<<9) |
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#define OHCI_PORT_CSC (1<<16) |
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#define OHCI_PORT_PESC (1<<17) |
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#define OHCI_PORT_PSSC (1<<18) |
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#define OHCI_PORT_OCIC (1<<19) |
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#define OHCI_PORT_PRSC (1<<20) |
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#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
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|OHCI_PORT_OCIC|OHCI_PORT_PRSC) |
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#define OHCI_TD_DIR_SETUP 0x0 |
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#define OHCI_TD_DIR_OUT 0x1 |
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#define OHCI_TD_DIR_IN 0x2 |
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#define OHCI_TD_DIR_RESERVED 0x3 |
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|
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#define OHCI_CC_NOERROR 0x0 |
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#define OHCI_CC_CRC 0x1 |
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#define OHCI_CC_BITSTUFFING 0x2 |
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3 |
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#define OHCI_CC_STALL 0x4 |
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#define OHCI_CC_DEVICENOTRESPONDING 0x5 |
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#define OHCI_CC_PIDCHECKFAILURE 0x6 |
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#define OHCI_CC_UNDEXPETEDPID 0x7 |
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#define OHCI_CC_DATAOVERRUN 0x8 |
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#define OHCI_CC_DATAUNDERRUN 0x9 |
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#define OHCI_CC_BUFFEROVERRUN 0xc |
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#define OHCI_CC_BUFFERUNDERRUN 0xd |
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#define OHCI_HRESET_FSBIR (1 << 0) |
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/* Update IRQ levels */
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static inline void ohci_intr_update(OHCIState *ohci) |
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{ |
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int level = 0; |
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if ((ohci->intr & OHCI_INTR_MIE) &&
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(ohci->intr_status & ohci->intr)) |
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level = 1;
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if (ohci->type == OHCI_TYPE_PCI)
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pci_set_irq((PCIDevice *)ohci->pic, ohci->irq, level); |
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else
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pic_set_irq_new(ohci->pic, ohci->irq, level); |
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} |
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/* Set an interrupt */
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static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) |
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{ |
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ohci->intr_status |= intr; |
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ohci_intr_update(ohci); |
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} |
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/* Attach or detach a device on a root hub port. */
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static void ohci_attach(USBPort *port1, USBDevice *dev) |
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{ |
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OHCIState *s = port1->opaque; |
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OHCIPort *port = &s->rhport[port1->index]; |
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uint32_t old_state = port->ctrl; |
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if (dev) {
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if (port->port.dev) {
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usb_attach(port1, NULL);
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} |
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/* set connect status */
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port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; |
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/* update speed */
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if (dev->speed == USB_SPEED_LOW)
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port->ctrl |= OHCI_PORT_LSDA; |
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else
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port->ctrl &= ~OHCI_PORT_LSDA; |
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port->port.dev = dev; |
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/* notify of remote-wakeup */
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if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
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ohci_set_interrupt(s, OHCI_INTR_RD); |
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/* send the attach message */
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usb_send_msg(dev, USB_MSG_ATTACH); |
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dprintf("usb-ohci: Attached port %d\n", port1->index);
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} else {
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/* set connect status */
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if (port->ctrl & OHCI_PORT_CCS) {
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port->ctrl &= ~OHCI_PORT_CCS; |
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port->ctrl |= OHCI_PORT_CSC; |
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} |
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/* disable port */
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if (port->ctrl & OHCI_PORT_PES) {
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port->ctrl &= ~OHCI_PORT_PES; |
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port->ctrl |= OHCI_PORT_PESC; |
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} |
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dev = port->port.dev; |
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if (dev) {
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/* send the detach message */
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usb_send_msg(dev, USB_MSG_DETACH); |
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} |
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port->port.dev = NULL;
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dprintf("usb-ohci: Detached port %d\n", port1->index);
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} |
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|
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if (old_state != port->ctrl)
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ohci_set_interrupt(s, OHCI_INTR_RHSC); |
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} |
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|
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/* Reset the controller */
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static void ohci_reset(OHCIState *ohci) |
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{ |
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OHCIPort *port; |
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int i;
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ohci->ctl = 0;
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ohci->old_ctl = 0;
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ohci->status = 0;
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ohci->intr_status = 0;
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ohci->intr = OHCI_INTR_MIE; |
361 |
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ohci->hcca = 0;
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ohci->ctrl_head = ohci->ctrl_cur = 0;
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ohci->bulk_head = ohci->bulk_cur = 0;
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ohci->per_cur = 0;
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ohci->done = 0;
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ohci->done_count = 7;
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/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
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* I took the value linux sets ...
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*/
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ohci->fsmps = 0x2778;
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ohci->fi = 0x2edf;
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ohci->fit = 0;
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ohci->frt = 0;
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ohci->frame_number = 0;
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ohci->pstart = 0;
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ohci->lst = OHCI_LS_THRESH; |
379 |
|
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ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
381 |
ohci->rhdesc_b = 0x0; /* Impl. specific */ |
382 |
ohci->rhstatus = 0;
|
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|
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for (i = 0; i < ohci->num_ports; i++) |
385 |
{ |
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port = &ohci->rhport[i]; |
387 |
port->ctrl = 0;
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if (port->port.dev)
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ohci_attach(&port->port, port->port.dev); |
390 |
} |
391 |
if (ohci->async_td) {
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usb_cancel_packet(&ohci->usb_packet); |
393 |
ohci->async_td = 0;
|
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} |
395 |
dprintf("usb-ohci: Reset %s\n", ohci->name);
|
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} |
397 |
|
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/* Get an array of dwords from main memory */
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static inline int get_dwords(uint32_t addr, uint32_t *buf, int num) |
400 |
{ |
401 |
int i;
|
402 |
|
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for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
404 |
cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0); |
405 |
*buf = le32_to_cpu(*buf); |
406 |
} |
407 |
|
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return 1; |
409 |
} |
410 |
|
411 |
/* Put an array of dwords in to main memory */
|
412 |
static inline int put_dwords(uint32_t addr, uint32_t *buf, int num) |
413 |
{ |
414 |
int i;
|
415 |
|
416 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
417 |
uint32_t tmp = cpu_to_le32(*buf); |
418 |
cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1); |
419 |
} |
420 |
|
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return 1; |
422 |
} |
423 |
|
424 |
static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed) |
425 |
{ |
426 |
return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
427 |
} |
428 |
|
429 |
static inline int ohci_read_td(uint32_t addr, struct ohci_td *td) |
430 |
{ |
431 |
return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2); |
432 |
} |
433 |
|
434 |
static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed) |
435 |
{ |
436 |
return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
437 |
} |
438 |
|
439 |
static inline int ohci_put_td(uint32_t addr, struct ohci_td *td) |
440 |
{ |
441 |
return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2); |
442 |
} |
443 |
|
444 |
/* Read/Write the contents of a TD from/to main memory. */
|
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static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write) |
446 |
{ |
447 |
uint32_t ptr; |
448 |
uint32_t n; |
449 |
|
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ptr = td->cbp; |
451 |
n = 0x1000 - (ptr & 0xfff); |
452 |
if (n > len)
|
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n = len; |
454 |
cpu_physical_memory_rw(ptr, buf, n, write); |
455 |
if (n == len)
|
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return;
|
457 |
ptr = td->be & ~0xfffu;
|
458 |
buf += n; |
459 |
cpu_physical_memory_rw(ptr, buf, len - n, write); |
460 |
} |
461 |
|
462 |
static void ohci_process_lists(OHCIState *ohci); |
463 |
|
464 |
static void ohci_async_complete_packet(USBPacket * packet, void *opaque) |
465 |
{ |
466 |
OHCIState *ohci = opaque; |
467 |
#ifdef DEBUG_PACKET
|
468 |
dprintf("Async packet complete\n");
|
469 |
#endif
|
470 |
ohci->async_complete = 1;
|
471 |
ohci_process_lists(ohci); |
472 |
} |
473 |
|
474 |
/* Service a transport descriptor.
|
475 |
Returns nonzero to terminate processing of this endpoint. */
|
476 |
|
477 |
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) |
478 |
{ |
479 |
int dir;
|
480 |
size_t len = 0;
|
481 |
char *str = NULL; |
482 |
int pid;
|
483 |
int ret;
|
484 |
int i;
|
485 |
USBDevice *dev; |
486 |
struct ohci_td td;
|
487 |
uint32_t addr; |
488 |
int flag_r;
|
489 |
int completion;
|
490 |
|
491 |
addr = ed->head & OHCI_DPTR_MASK; |
492 |
/* See if this TD has already been submitted to the device. */
|
493 |
completion = (addr == ohci->async_td); |
494 |
if (completion && !ohci->async_complete) {
|
495 |
#ifdef DEBUG_PACKET
|
496 |
dprintf("Skipping async TD\n");
|
497 |
#endif
|
498 |
return 1; |
499 |
} |
500 |
if (!ohci_read_td(addr, &td)) {
|
501 |
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
502 |
return 0; |
503 |
} |
504 |
|
505 |
dir = OHCI_BM(ed->flags, ED_D); |
506 |
switch (dir) {
|
507 |
case OHCI_TD_DIR_OUT:
|
508 |
case OHCI_TD_DIR_IN:
|
509 |
/* Same value. */
|
510 |
break;
|
511 |
default:
|
512 |
dir = OHCI_BM(td.flags, TD_DP); |
513 |
break;
|
514 |
} |
515 |
|
516 |
switch (dir) {
|
517 |
case OHCI_TD_DIR_IN:
|
518 |
str = "in";
|
519 |
pid = USB_TOKEN_IN; |
520 |
break;
|
521 |
case OHCI_TD_DIR_OUT:
|
522 |
str = "out";
|
523 |
pid = USB_TOKEN_OUT; |
524 |
break;
|
525 |
case OHCI_TD_DIR_SETUP:
|
526 |
str = "setup";
|
527 |
pid = USB_TOKEN_SETUP; |
528 |
break;
|
529 |
default:
|
530 |
fprintf(stderr, "usb-ohci: Bad direction\n");
|
531 |
return 1; |
532 |
} |
533 |
if (td.cbp && td.be) {
|
534 |
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
535 |
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); |
536 |
} else {
|
537 |
len = (td.be - td.cbp) + 1;
|
538 |
} |
539 |
|
540 |
if (len && dir != OHCI_TD_DIR_IN && !completion) {
|
541 |
ohci_copy_td(&td, ohci->usb_buf, len, 0);
|
542 |
} |
543 |
} |
544 |
|
545 |
flag_r = (td.flags & OHCI_TD_R) != 0;
|
546 |
#ifdef DEBUG_PACKET
|
547 |
dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
|
548 |
addr, len, str, flag_r, td.cbp, td.be); |
549 |
|
550 |
if (len >= 0 && dir != OHCI_TD_DIR_IN) { |
551 |
dprintf(" data:");
|
552 |
for (i = 0; i < len; i++) |
553 |
printf(" %.2x", ohci->usb_buf[i]);
|
554 |
dprintf("\n");
|
555 |
} |
556 |
#endif
|
557 |
if (completion) {
|
558 |
ret = ohci->usb_packet.len; |
559 |
ohci->async_td = 0;
|
560 |
ohci->async_complete = 0;
|
561 |
} else {
|
562 |
ret = USB_RET_NODEV; |
563 |
for (i = 0; i < ohci->num_ports; i++) { |
564 |
dev = ohci->rhport[i].port.dev; |
565 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
566 |
continue;
|
567 |
|
568 |
if (ohci->async_td) {
|
569 |
/* ??? The hardware should allow one active packet per
|
570 |
endpoint. We only allow one active packet per controller.
|
571 |
This should be sufficient as long as devices respond in a
|
572 |
timely manner.
|
573 |
*/
|
574 |
#ifdef DEBUG_PACKET
|
575 |
dprintf("Too many pending packets\n");
|
576 |
#endif
|
577 |
return 1; |
578 |
} |
579 |
ohci->usb_packet.pid = pid; |
580 |
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); |
581 |
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); |
582 |
ohci->usb_packet.data = ohci->usb_buf; |
583 |
ohci->usb_packet.len = len; |
584 |
ohci->usb_packet.complete_cb = ohci_async_complete_packet; |
585 |
ohci->usb_packet.complete_opaque = ohci; |
586 |
ret = dev->handle_packet(dev, &ohci->usb_packet); |
587 |
if (ret != USB_RET_NODEV)
|
588 |
break;
|
589 |
} |
590 |
#ifdef DEBUG_PACKET
|
591 |
dprintf("ret=%d\n", ret);
|
592 |
#endif
|
593 |
if (ret == USB_RET_ASYNC) {
|
594 |
ohci->async_td = addr; |
595 |
return 1; |
596 |
} |
597 |
} |
598 |
if (ret >= 0) { |
599 |
if (dir == OHCI_TD_DIR_IN) {
|
600 |
ohci_copy_td(&td, ohci->usb_buf, ret, 1);
|
601 |
#ifdef DEBUG_PACKET
|
602 |
dprintf(" data:");
|
603 |
for (i = 0; i < ret; i++) |
604 |
printf(" %.2x", ohci->usb_buf[i]);
|
605 |
dprintf("\n");
|
606 |
#endif
|
607 |
} else {
|
608 |
ret = len; |
609 |
} |
610 |
} |
611 |
|
612 |
/* Writeback */
|
613 |
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
614 |
/* Transmission succeeded. */
|
615 |
if (ret == len) {
|
616 |
td.cbp = 0;
|
617 |
} else {
|
618 |
td.cbp += ret; |
619 |
if ((td.cbp & 0xfff) + ret > 0xfff) { |
620 |
td.cbp &= 0xfff;
|
621 |
td.cbp |= td.be & ~0xfff;
|
622 |
} |
623 |
} |
624 |
td.flags |= OHCI_TD_T1; |
625 |
td.flags ^= OHCI_TD_T0; |
626 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); |
627 |
OHCI_SET_BM(td.flags, TD_EC, 0);
|
628 |
|
629 |
ed->head &= ~OHCI_ED_C; |
630 |
if (td.flags & OHCI_TD_T0)
|
631 |
ed->head |= OHCI_ED_C; |
632 |
} else {
|
633 |
if (ret >= 0) { |
634 |
dprintf("usb-ohci: Underrun\n");
|
635 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
636 |
} else {
|
637 |
switch (ret) {
|
638 |
case USB_RET_NODEV:
|
639 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
640 |
case USB_RET_NAK:
|
641 |
dprintf("usb-ohci: got NAK\n");
|
642 |
return 1; |
643 |
case USB_RET_STALL:
|
644 |
dprintf("usb-ohci: got STALL\n");
|
645 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
646 |
break;
|
647 |
case USB_RET_BABBLE:
|
648 |
dprintf("usb-ohci: got BABBLE\n");
|
649 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
650 |
break;
|
651 |
default:
|
652 |
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
653 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
654 |
OHCI_SET_BM(td.flags, TD_EC, 3);
|
655 |
break;
|
656 |
} |
657 |
} |
658 |
ed->head |= OHCI_ED_H; |
659 |
} |
660 |
|
661 |
/* Retire this TD */
|
662 |
ed->head &= ~OHCI_DPTR_MASK; |
663 |
ed->head |= td.next & OHCI_DPTR_MASK; |
664 |
td.next = ohci->done; |
665 |
ohci->done = addr; |
666 |
i = OHCI_BM(td.flags, TD_DI); |
667 |
if (i < ohci->done_count)
|
668 |
ohci->done_count = i; |
669 |
ohci_put_td(addr, &td); |
670 |
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
671 |
} |
672 |
|
673 |
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
674 |
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head) |
675 |
{ |
676 |
struct ohci_ed ed;
|
677 |
uint32_t next_ed; |
678 |
uint32_t cur; |
679 |
int active;
|
680 |
|
681 |
active = 0;
|
682 |
|
683 |
if (head == 0) |
684 |
return 0; |
685 |
|
686 |
for (cur = head; cur; cur = next_ed) {
|
687 |
if (!ohci_read_ed(cur, &ed)) {
|
688 |
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
689 |
return 0; |
690 |
} |
691 |
|
692 |
next_ed = ed.next & OHCI_DPTR_MASK; |
693 |
|
694 |
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
|
695 |
uint32_t addr; |
696 |
/* Cancel pending packets for ED that have been paused. */
|
697 |
addr = ed.head & OHCI_DPTR_MASK; |
698 |
if (ohci->async_td && addr == ohci->async_td) {
|
699 |
usb_cancel_packet(&ohci->usb_packet); |
700 |
ohci->async_td = 0;
|
701 |
} |
702 |
continue;
|
703 |
} |
704 |
|
705 |
/* Skip isochronous endpoints. */
|
706 |
if (ed.flags & OHCI_ED_F)
|
707 |
continue;
|
708 |
|
709 |
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
710 |
#ifdef DEBUG_PACKET
|
711 |
dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
712 |
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
713 |
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
714 |
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
715 |
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, |
716 |
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
717 |
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
718 |
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); |
719 |
#endif
|
720 |
active = 1;
|
721 |
|
722 |
if (ohci_service_td(ohci, &ed))
|
723 |
break;
|
724 |
} |
725 |
|
726 |
ohci_put_ed(cur, &ed); |
727 |
} |
728 |
|
729 |
return active;
|
730 |
} |
731 |
|
732 |
/* Generate a SOF event, and set a timer for EOF */
|
733 |
static void ohci_sof(OHCIState *ohci) |
734 |
{ |
735 |
ohci->sof_time = qemu_get_clock(vm_clock); |
736 |
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
737 |
ohci_set_interrupt(ohci, OHCI_INTR_SF); |
738 |
} |
739 |
|
740 |
/* Process Control and Bulk lists. */
|
741 |
static void ohci_process_lists(OHCIState *ohci) |
742 |
{ |
743 |
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
744 |
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
|
745 |
dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
|
746 |
if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
|
747 |
ohci->ctrl_cur = 0;
|
748 |
ohci->status &= ~OHCI_STATUS_CLF; |
749 |
} |
750 |
} |
751 |
|
752 |
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
753 |
if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
|
754 |
ohci->bulk_cur = 0;
|
755 |
ohci->status &= ~OHCI_STATUS_BLF; |
756 |
} |
757 |
} |
758 |
} |
759 |
|
760 |
/* Do frame processing on frame boundary */
|
761 |
static void ohci_frame_boundary(void *opaque) |
762 |
{ |
763 |
OHCIState *ohci = opaque; |
764 |
struct ohci_hcca hcca;
|
765 |
|
766 |
cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0); |
767 |
|
768 |
/* Process all the lists at the end of the frame */
|
769 |
if (ohci->ctl & OHCI_CTL_PLE) {
|
770 |
int n;
|
771 |
|
772 |
n = ohci->frame_number & 0x1f;
|
773 |
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n])); |
774 |
} |
775 |
|
776 |
/* Cancel all pending packets if either of the lists has been disabled. */
|
777 |
if (ohci->async_td &&
|
778 |
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
779 |
usb_cancel_packet(&ohci->usb_packet); |
780 |
ohci->async_td = 0;
|
781 |
} |
782 |
ohci->old_ctl = ohci->ctl; |
783 |
ohci_process_lists(ohci); |
784 |
|
785 |
/* Frame boundary, so do EOF stuf here */
|
786 |
ohci->frt = ohci->fit; |
787 |
|
788 |
/* XXX: endianness */
|
789 |
ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
790 |
hcca.frame = cpu_to_le32(ohci->frame_number); |
791 |
|
792 |
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { |
793 |
if (!ohci->done)
|
794 |
abort(); |
795 |
if (ohci->intr & ohci->intr_status)
|
796 |
ohci->done |= 1;
|
797 |
hcca.done = cpu_to_le32(ohci->done); |
798 |
ohci->done = 0;
|
799 |
ohci->done_count = 7;
|
800 |
ohci_set_interrupt(ohci, OHCI_INTR_WD); |
801 |
} |
802 |
|
803 |
if (ohci->done_count != 7 && ohci->done_count != 0) |
804 |
ohci->done_count--; |
805 |
|
806 |
/* Do SOF stuff here */
|
807 |
ohci_sof(ohci); |
808 |
|
809 |
/* Writeback HCCA */
|
810 |
cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1); |
811 |
} |
812 |
|
813 |
/* Start sending SOF tokens across the USB bus, lists are processed in
|
814 |
* next frame
|
815 |
*/
|
816 |
static int ohci_bus_start(OHCIState *ohci) |
817 |
{ |
818 |
ohci->eof_timer = qemu_new_timer(vm_clock, |
819 |
ohci_frame_boundary, |
820 |
ohci); |
821 |
|
822 |
if (ohci->eof_timer == NULL) { |
823 |
fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
|
824 |
/* TODO: Signal unrecoverable error */
|
825 |
return 0; |
826 |
} |
827 |
|
828 |
dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
|
829 |
|
830 |
ohci_sof(ohci); |
831 |
|
832 |
return 1; |
833 |
} |
834 |
|
835 |
/* Stop sending SOF tokens on the bus */
|
836 |
static void ohci_bus_stop(OHCIState *ohci) |
837 |
{ |
838 |
if (ohci->eof_timer)
|
839 |
qemu_del_timer(ohci->eof_timer); |
840 |
} |
841 |
|
842 |
/* Sets a flag in a port status register but only set it if the port is
|
843 |
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
844 |
* return 1.
|
845 |
*/
|
846 |
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) |
847 |
{ |
848 |
int ret = 1; |
849 |
|
850 |
/* writing a 0 has no effect */
|
851 |
if (val == 0) |
852 |
return 0; |
853 |
|
854 |
/* If CurrentConnectStatus is cleared we set
|
855 |
* ConnectStatusChange
|
856 |
*/
|
857 |
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
858 |
ohci->rhport[i].ctrl |= OHCI_PORT_CSC; |
859 |
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
860 |
/* TODO: CSC is a wakeup event */
|
861 |
} |
862 |
return 0; |
863 |
} |
864 |
|
865 |
if (ohci->rhport[i].ctrl & val)
|
866 |
ret = 0;
|
867 |
|
868 |
/* set the bit */
|
869 |
ohci->rhport[i].ctrl |= val; |
870 |
|
871 |
return ret;
|
872 |
} |
873 |
|
874 |
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
875 |
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) |
876 |
{ |
877 |
val &= OHCI_FMI_FI; |
878 |
|
879 |
if (val != ohci->fi) {
|
880 |
dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
881 |
ohci->name, ohci->fi, ohci->fi); |
882 |
} |
883 |
|
884 |
ohci->fi = val; |
885 |
} |
886 |
|
887 |
static void ohci_port_power(OHCIState *ohci, int i, int p) |
888 |
{ |
889 |
if (p) {
|
890 |
ohci->rhport[i].ctrl |= OHCI_PORT_PPS; |
891 |
} else {
|
892 |
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| |
893 |
OHCI_PORT_CCS| |
894 |
OHCI_PORT_PSS| |
895 |
OHCI_PORT_PRS); |
896 |
} |
897 |
} |
898 |
|
899 |
/* Set HcControlRegister */
|
900 |
static void ohci_set_ctl(OHCIState *ohci, uint32_t val) |
901 |
{ |
902 |
uint32_t old_state; |
903 |
uint32_t new_state; |
904 |
|
905 |
old_state = ohci->ctl & OHCI_CTL_HCFS; |
906 |
ohci->ctl = val; |
907 |
new_state = ohci->ctl & OHCI_CTL_HCFS; |
908 |
|
909 |
/* no state change */
|
910 |
if (old_state == new_state)
|
911 |
return;
|
912 |
|
913 |
switch (new_state) {
|
914 |
case OHCI_USB_OPERATIONAL:
|
915 |
ohci_bus_start(ohci); |
916 |
break;
|
917 |
case OHCI_USB_SUSPEND:
|
918 |
ohci_bus_stop(ohci); |
919 |
dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
|
920 |
break;
|
921 |
case OHCI_USB_RESUME:
|
922 |
dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
|
923 |
break;
|
924 |
case OHCI_USB_RESET:
|
925 |
dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
|
926 |
break;
|
927 |
} |
928 |
} |
929 |
|
930 |
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
931 |
{ |
932 |
uint16_t fr; |
933 |
int64_t tks; |
934 |
|
935 |
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
936 |
return (ohci->frt << 31); |
937 |
|
938 |
/* Being in USB operational state guarnatees sof_time was
|
939 |
* set already.
|
940 |
*/
|
941 |
tks = qemu_get_clock(vm_clock) - ohci->sof_time; |
942 |
|
943 |
/* avoid muldiv if possible */
|
944 |
if (tks >= usb_frame_time)
|
945 |
return (ohci->frt << 31); |
946 |
|
947 |
tks = muldiv64(1, tks, usb_bit_time);
|
948 |
fr = (uint16_t)(ohci->fi - tks); |
949 |
|
950 |
return (ohci->frt << 31) | fr; |
951 |
} |
952 |
|
953 |
|
954 |
/* Set root hub status */
|
955 |
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) |
956 |
{ |
957 |
uint32_t old_state; |
958 |
|
959 |
old_state = ohci->rhstatus; |
960 |
|
961 |
/* write 1 to clear OCIC */
|
962 |
if (val & OHCI_RHS_OCIC)
|
963 |
ohci->rhstatus &= ~OHCI_RHS_OCIC; |
964 |
|
965 |
if (val & OHCI_RHS_LPS) {
|
966 |
int i;
|
967 |
|
968 |
for (i = 0; i < ohci->num_ports; i++) |
969 |
ohci_port_power(ohci, i, 0);
|
970 |
dprintf("usb-ohci: powered down all ports\n");
|
971 |
} |
972 |
|
973 |
if (val & OHCI_RHS_LPSC) {
|
974 |
int i;
|
975 |
|
976 |
for (i = 0; i < ohci->num_ports; i++) |
977 |
ohci_port_power(ohci, i, 1);
|
978 |
dprintf("usb-ohci: powered up all ports\n");
|
979 |
} |
980 |
|
981 |
if (val & OHCI_RHS_DRWE)
|
982 |
ohci->rhstatus |= OHCI_RHS_DRWE; |
983 |
|
984 |
if (val & OHCI_RHS_CRWE)
|
985 |
ohci->rhstatus &= ~OHCI_RHS_DRWE; |
986 |
|
987 |
if (old_state != ohci->rhstatus)
|
988 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
989 |
} |
990 |
|
991 |
/* Set root hub port status */
|
992 |
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) |
993 |
{ |
994 |
uint32_t old_state; |
995 |
OHCIPort *port; |
996 |
|
997 |
port = &ohci->rhport[portnum]; |
998 |
old_state = port->ctrl; |
999 |
|
1000 |
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
1001 |
if (val & OHCI_PORT_WTC)
|
1002 |
port->ctrl &= ~(val & OHCI_PORT_WTC); |
1003 |
|
1004 |
if (val & OHCI_PORT_CCS)
|
1005 |
port->ctrl &= ~OHCI_PORT_PES; |
1006 |
|
1007 |
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); |
1008 |
|
1009 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
|
1010 |
dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
|
1011 |
|
1012 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
1013 |
dprintf("usb-ohci: port %d: RESET\n", portnum);
|
1014 |
usb_send_msg(port->port.dev, USB_MSG_RESET); |
1015 |
port->ctrl &= ~OHCI_PORT_PRS; |
1016 |
/* ??? Should this also set OHCI_PORT_PESC. */
|
1017 |
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; |
1018 |
} |
1019 |
|
1020 |
/* Invert order here to ensure in ambiguous case, device is
|
1021 |
* powered up...
|
1022 |
*/
|
1023 |
if (val & OHCI_PORT_LSDA)
|
1024 |
ohci_port_power(ohci, portnum, 0);
|
1025 |
if (val & OHCI_PORT_PPS)
|
1026 |
ohci_port_power(ohci, portnum, 1);
|
1027 |
|
1028 |
if (old_state != port->ctrl)
|
1029 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1030 |
|
1031 |
return;
|
1032 |
} |
1033 |
|
1034 |
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) |
1035 |
{ |
1036 |
OHCIState *ohci = ptr; |
1037 |
|
1038 |
addr -= ohci->mem_base; |
1039 |
|
1040 |
/* Only aligned reads are allowed on OHCI */
|
1041 |
if (addr & 3) { |
1042 |
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
1043 |
return 0xffffffff; |
1044 |
} |
1045 |
|
1046 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1047 |
/* HcRhPortStatus */
|
1048 |
return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1049 |
} |
1050 |
|
1051 |
switch (addr >> 2) { |
1052 |
case 0: /* HcRevision */ |
1053 |
return 0x10; |
1054 |
|
1055 |
case 1: /* HcControl */ |
1056 |
return ohci->ctl;
|
1057 |
|
1058 |
case 2: /* HcCommandStatus */ |
1059 |
return ohci->status;
|
1060 |
|
1061 |
case 3: /* HcInterruptStatus */ |
1062 |
return ohci->intr_status;
|
1063 |
|
1064 |
case 4: /* HcInterruptEnable */ |
1065 |
case 5: /* HcInterruptDisable */ |
1066 |
return ohci->intr;
|
1067 |
|
1068 |
case 6: /* HcHCCA */ |
1069 |
return ohci->hcca;
|
1070 |
|
1071 |
case 7: /* HcPeriodCurrentED */ |
1072 |
return ohci->per_cur;
|
1073 |
|
1074 |
case 8: /* HcControlHeadED */ |
1075 |
return ohci->ctrl_head;
|
1076 |
|
1077 |
case 9: /* HcControlCurrentED */ |
1078 |
return ohci->ctrl_cur;
|
1079 |
|
1080 |
case 10: /* HcBulkHeadED */ |
1081 |
return ohci->bulk_head;
|
1082 |
|
1083 |
case 11: /* HcBulkCurrentED */ |
1084 |
return ohci->bulk_cur;
|
1085 |
|
1086 |
case 12: /* HcDoneHead */ |
1087 |
return ohci->done;
|
1088 |
|
1089 |
case 13: /* HcFmInterval */ |
1090 |
return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); |
1091 |
|
1092 |
case 14: /* HcFmRemaining */ |
1093 |
return ohci_get_frame_remaining(ohci);
|
1094 |
|
1095 |
case 15: /* HcFmNumber */ |
1096 |
return ohci->frame_number;
|
1097 |
|
1098 |
case 16: /* HcPeriodicStart */ |
1099 |
return ohci->pstart;
|
1100 |
|
1101 |
case 17: /* HcLSThreshold */ |
1102 |
return ohci->lst;
|
1103 |
|
1104 |
case 18: /* HcRhDescriptorA */ |
1105 |
return ohci->rhdesc_a;
|
1106 |
|
1107 |
case 19: /* HcRhDescriptorB */ |
1108 |
return ohci->rhdesc_b;
|
1109 |
|
1110 |
case 20: /* HcRhStatus */ |
1111 |
return ohci->rhstatus;
|
1112 |
|
1113 |
/* PXA27x specific registers */
|
1114 |
case 24: /* HcStatus */ |
1115 |
return ohci->hstatus & ohci->hmask;
|
1116 |
|
1117 |
case 25: /* HcHReset */ |
1118 |
return ohci->hreset;
|
1119 |
|
1120 |
case 26: /* HcHInterruptEnable */ |
1121 |
return ohci->hmask;
|
1122 |
|
1123 |
case 27: /* HcHInterruptTest */ |
1124 |
return ohci->htest;
|
1125 |
|
1126 |
default:
|
1127 |
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); |
1128 |
return 0xffffffff; |
1129 |
} |
1130 |
} |
1131 |
|
1132 |
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) |
1133 |
{ |
1134 |
OHCIState *ohci = ptr; |
1135 |
|
1136 |
addr -= ohci->mem_base; |
1137 |
|
1138 |
/* Only aligned reads are allowed on OHCI */
|
1139 |
if (addr & 3) { |
1140 |
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
1141 |
return;
|
1142 |
} |
1143 |
|
1144 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1145 |
/* HcRhPortStatus */
|
1146 |
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); |
1147 |
return;
|
1148 |
} |
1149 |
|
1150 |
switch (addr >> 2) { |
1151 |
case 1: /* HcControl */ |
1152 |
ohci_set_ctl(ohci, val); |
1153 |
break;
|
1154 |
|
1155 |
case 2: /* HcCommandStatus */ |
1156 |
/* SOC is read-only */
|
1157 |
val = (val & ~OHCI_STATUS_SOC); |
1158 |
|
1159 |
/* Bits written as '0' remain unchanged in the register */
|
1160 |
ohci->status |= val; |
1161 |
|
1162 |
if (ohci->status & OHCI_STATUS_HCR)
|
1163 |
ohci_reset(ohci); |
1164 |
break;
|
1165 |
|
1166 |
case 3: /* HcInterruptStatus */ |
1167 |
ohci->intr_status &= ~val; |
1168 |
ohci_intr_update(ohci); |
1169 |
break;
|
1170 |
|
1171 |
case 4: /* HcInterruptEnable */ |
1172 |
ohci->intr |= val; |
1173 |
ohci_intr_update(ohci); |
1174 |
break;
|
1175 |
|
1176 |
case 5: /* HcInterruptDisable */ |
1177 |
ohci->intr &= ~val; |
1178 |
ohci_intr_update(ohci); |
1179 |
break;
|
1180 |
|
1181 |
case 6: /* HcHCCA */ |
1182 |
ohci->hcca = val & OHCI_HCCA_MASK; |
1183 |
break;
|
1184 |
|
1185 |
case 8: /* HcControlHeadED */ |
1186 |
ohci->ctrl_head = val & OHCI_EDPTR_MASK; |
1187 |
break;
|
1188 |
|
1189 |
case 9: /* HcControlCurrentED */ |
1190 |
ohci->ctrl_cur = val & OHCI_EDPTR_MASK; |
1191 |
break;
|
1192 |
|
1193 |
case 10: /* HcBulkHeadED */ |
1194 |
ohci->bulk_head = val & OHCI_EDPTR_MASK; |
1195 |
break;
|
1196 |
|
1197 |
case 11: /* HcBulkCurrentED */ |
1198 |
ohci->bulk_cur = val & OHCI_EDPTR_MASK; |
1199 |
break;
|
1200 |
|
1201 |
case 13: /* HcFmInterval */ |
1202 |
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
1203 |
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
1204 |
ohci_set_frame_interval(ohci, val); |
1205 |
break;
|
1206 |
|
1207 |
case 16: /* HcPeriodicStart */ |
1208 |
ohci->pstart = val & 0xffff;
|
1209 |
break;
|
1210 |
|
1211 |
case 17: /* HcLSThreshold */ |
1212 |
ohci->lst = val & 0xffff;
|
1213 |
break;
|
1214 |
|
1215 |
case 18: /* HcRhDescriptorA */ |
1216 |
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; |
1217 |
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; |
1218 |
break;
|
1219 |
|
1220 |
case 19: /* HcRhDescriptorB */ |
1221 |
break;
|
1222 |
|
1223 |
case 20: /* HcRhStatus */ |
1224 |
ohci_set_hub_status(ohci, val); |
1225 |
break;
|
1226 |
|
1227 |
/* PXA27x specific registers */
|
1228 |
case 24: /* HcStatus */ |
1229 |
ohci->hstatus &= ~(val & ohci->hmask); |
1230 |
|
1231 |
case 25: /* HcHReset */ |
1232 |
ohci->hreset = val & ~OHCI_HRESET_FSBIR; |
1233 |
if (val & OHCI_HRESET_FSBIR)
|
1234 |
ohci_reset(ohci); |
1235 |
break;
|
1236 |
|
1237 |
case 26: /* HcHInterruptEnable */ |
1238 |
ohci->hmask = val; |
1239 |
break;
|
1240 |
|
1241 |
case 27: /* HcHInterruptTest */ |
1242 |
ohci->htest = val; |
1243 |
break;
|
1244 |
|
1245 |
default:
|
1246 |
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); |
1247 |
break;
|
1248 |
} |
1249 |
} |
1250 |
|
1251 |
/* Only dword reads are defined on OHCI register space */
|
1252 |
static CPUReadMemoryFunc *ohci_readfn[3]={ |
1253 |
ohci_mem_read, |
1254 |
ohci_mem_read, |
1255 |
ohci_mem_read |
1256 |
}; |
1257 |
|
1258 |
/* Only dword writes are defined on OHCI register space */
|
1259 |
static CPUWriteMemoryFunc *ohci_writefn[3]={ |
1260 |
ohci_mem_write, |
1261 |
ohci_mem_write, |
1262 |
ohci_mem_write |
1263 |
}; |
1264 |
|
1265 |
static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn, |
1266 |
void *pic, int irq, enum ohci_type type, const char *name) |
1267 |
{ |
1268 |
int i;
|
1269 |
|
1270 |
if (usb_frame_time == 0) { |
1271 |
#if OHCI_TIME_WARP
|
1272 |
usb_frame_time = ticks_per_sec; |
1273 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000); |
1274 |
#else
|
1275 |
usb_frame_time = muldiv64(1, ticks_per_sec, 1000); |
1276 |
if (ticks_per_sec >= USB_HZ) {
|
1277 |
usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
|
1278 |
} else {
|
1279 |
usb_bit_time = 1;
|
1280 |
} |
1281 |
#endif
|
1282 |
dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
|
1283 |
usb_frame_time, usb_bit_time); |
1284 |
} |
1285 |
|
1286 |
ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
|
1287 |
ohci->name = name; |
1288 |
|
1289 |
ohci->pic = pic; |
1290 |
ohci->irq = irq; |
1291 |
ohci->type = type; |
1292 |
|
1293 |
ohci->num_ports = num_ports; |
1294 |
for (i = 0; i < num_ports; i++) { |
1295 |
qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach); |
1296 |
} |
1297 |
|
1298 |
ohci->async_td = 0;
|
1299 |
ohci_reset(ohci); |
1300 |
} |
1301 |
|
1302 |
typedef struct { |
1303 |
PCIDevice pci_dev; |
1304 |
OHCIState state; |
1305 |
} OHCIPCIState; |
1306 |
|
1307 |
static void ohci_mapfunc(PCIDevice *pci_dev, int i, |
1308 |
uint32_t addr, uint32_t size, int type)
|
1309 |
{ |
1310 |
OHCIPCIState *ohci = (OHCIPCIState *)pci_dev; |
1311 |
ohci->state.mem_base = addr; |
1312 |
cpu_register_physical_memory(addr, size, ohci->state.mem); |
1313 |
} |
1314 |
|
1315 |
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn) |
1316 |
{ |
1317 |
OHCIPCIState *ohci; |
1318 |
int vid = 0x106b; |
1319 |
int did = 0x003f; |
1320 |
|
1321 |
ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci), |
1322 |
devfn, NULL, NULL); |
1323 |
if (ohci == NULL) { |
1324 |
fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
|
1325 |
return;
|
1326 |
} |
1327 |
|
1328 |
ohci->pci_dev.config[0x00] = vid & 0xff; |
1329 |
ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff; |
1330 |
ohci->pci_dev.config[0x02] = did & 0xff; |
1331 |
ohci->pci_dev.config[0x03] = (did >> 8) & 0xff; |
1332 |
ohci->pci_dev.config[0x09] = 0x10; /* OHCI */ |
1333 |
ohci->pci_dev.config[0x0a] = 0x3; |
1334 |
ohci->pci_dev.config[0x0b] = 0xc; |
1335 |
ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ |
1336 |
|
1337 |
usb_ohci_init(&ohci->state, num_ports, devfn, &ohci->pci_dev, |
1338 |
0, OHCI_TYPE_PCI, ohci->pci_dev.name);
|
1339 |
|
1340 |
pci_register_io_region((struct PCIDevice *)ohci, 0, 256, |
1341 |
PCI_ADDRESS_SPACE_MEM, ohci_mapfunc); |
1342 |
} |
1343 |
|
1344 |
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
1345 |
void *pic, int irq) |
1346 |
{ |
1347 |
OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
|
1348 |
|
1349 |
usb_ohci_init(ohci, num_ports, devfn, pic, irq, |
1350 |
OHCI_TYPE_PXA, "OHCI USB");
|
1351 |
ohci->mem_base = base; |
1352 |
|
1353 |
cpu_register_physical_memory(ohci->mem_base, 0xfff, ohci->mem);
|
1354 |
} |