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/*
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* QEMU System Emulator header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef VL_H
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#define VL_H
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/* we put basic includes here to avoid repeating them in device drivers */
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <limits.h> |
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#include <time.h> |
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#include <ctype.h> |
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#include <errno.h> |
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#include <unistd.h> |
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#include <fcntl.h> |
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#include <sys/stat.h> |
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#ifndef O_LARGEFILE
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#define O_LARGEFILE 0 |
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#endif
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#ifndef O_BINARY
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#define O_BINARY 0 |
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#endif
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#ifndef ENOMEDIUM
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#define ENOMEDIUM ENODEV
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#endif
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#ifdef _WIN32
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#include <windows.h> |
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#define fsync _commit
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#define lseek _lseeki64
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#define ENOTSUP 4096 |
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extern int qemu_ftruncate64(int, int64_t); |
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#define ftruncate qemu_ftruncate64
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static inline char *realpath(const char *path, char *resolved_path) |
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{ |
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_fullpath(resolved_path, path, _MAX_PATH); |
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return resolved_path;
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} |
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#define PRId64 "I64d" |
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#define PRIx64 "I64x" |
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#define PRIu64 "I64u" |
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#define PRIo64 "I64o" |
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#endif
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#ifdef QEMU_TOOL
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/* we use QEMU_TOOL in the command line tools which do not depend on
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the target CPU type */
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#include "config-host.h" |
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#include <setjmp.h> |
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#include "osdep.h" |
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#include "bswap.h" |
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#else
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#include "audio/audio.h" |
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#include "cpu.h" |
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#endif /* !defined(QEMU_TOOL) */ |
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#ifndef glue
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#define xglue(x, y) x ## y |
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#define glue(x, y) xglue(x, y)
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#define stringify(s) tostring(s)
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#define tostring(s) #s |
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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/* cutils.c */
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void pstrcpy(char *buf, int buf_size, const char *str); |
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char *pstrcat(char *buf, int buf_size, const char *s); |
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int strstart(const char *str, const char *val, const char **ptr); |
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int stristart(const char *str, const char *val, const char **ptr); |
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/* vl.c */
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uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
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void hw_error(const char *fmt, ...); |
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extern const char *bios_dir; |
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extern int vm_running; |
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extern const char *qemu_name; |
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typedef struct vm_change_state_entry VMChangeStateEntry; |
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typedef void VMChangeStateHandler(void *opaque, int running); |
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typedef void VMStopHandler(void *opaque, int reason); |
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VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
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void *opaque);
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void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
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void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); |
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void vm_start(void); |
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void vm_stop(int reason); |
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typedef void QEMUResetHandler(void *opaque); |
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void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
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void qemu_system_reset_request(void); |
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void qemu_system_shutdown_request(void); |
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void qemu_system_powerdown_request(void); |
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#if !defined(TARGET_SPARC)
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// Please implement a power failure function to signal the OS
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#define qemu_system_powerdown() do{}while(0) |
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#else
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void qemu_system_powerdown(void); |
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#endif
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void main_loop_wait(int timeout); |
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extern int ram_size; |
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extern int bios_size; |
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extern int rtc_utc; |
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extern int cirrus_vga_enabled; |
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extern int vmsvga_enabled; |
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extern int graphic_width; |
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extern int graphic_height; |
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extern int graphic_depth; |
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extern const char *keyboard_layout; |
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extern int kqemu_allowed; |
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extern int win2k_install_hack; |
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extern int usb_enabled; |
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extern int smp_cpus; |
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extern int no_quit; |
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extern int semihosting_enabled; |
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extern int autostart; |
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extern const char *bootp_filename; |
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#define MAX_OPTION_ROMS 16 |
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extern const char *option_rom[MAX_OPTION_ROMS]; |
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extern int nb_option_roms; |
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/* XXX: make it dynamic */
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#define MAX_BIOS_SIZE (4 * 1024 * 1024) |
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#if defined (TARGET_PPC) || defined (TARGET_SPARC64)
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#define BIOS_SIZE ((512 + 32) * 1024) |
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#elif defined(TARGET_MIPS)
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#define BIOS_SIZE (4 * 1024 * 1024) |
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#endif
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/* keyboard/mouse support */
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#define MOUSE_EVENT_LBUTTON 0x01 |
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#define MOUSE_EVENT_RBUTTON 0x02 |
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#define MOUSE_EVENT_MBUTTON 0x04 |
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typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
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typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
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typedef struct QEMUPutMouseEntry { |
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QEMUPutMouseEvent *qemu_put_mouse_event; |
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void *qemu_put_mouse_event_opaque;
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int qemu_put_mouse_event_absolute;
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char *qemu_put_mouse_event_name;
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/* used internally by qemu for handling mice */
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struct QEMUPutMouseEntry *next;
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} QEMUPutMouseEntry; |
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void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
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QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
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void *opaque, int absolute, |
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const char *name); |
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void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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void kbd_put_keycode(int keycode); |
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void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
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int kbd_mouse_is_absolute(void); |
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void do_info_mice(void); |
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void do_mouse_set(int index); |
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/* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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constants) */
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#define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
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#define QEMU_KEY_BACKSPACE 0x007f |
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#define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
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#define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
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#define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
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#define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
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#define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
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#define QEMU_KEY_END QEMU_KEY_ESC1(4) |
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#define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
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#define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
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#define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
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#define QEMU_KEY_CTRL_UP 0xe400 |
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#define QEMU_KEY_CTRL_DOWN 0xe401 |
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#define QEMU_KEY_CTRL_LEFT 0xe402 |
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#define QEMU_KEY_CTRL_RIGHT 0xe403 |
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#define QEMU_KEY_CTRL_HOME 0xe404 |
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#define QEMU_KEY_CTRL_END 0xe405 |
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#define QEMU_KEY_CTRL_PAGEUP 0xe406 |
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#define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
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void kbd_put_keysym(int keysym); |
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/* async I/O support */
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typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); |
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typedef int IOCanRWHandler(void *opaque); |
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typedef void IOHandler(void *opaque); |
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int qemu_set_fd_handler2(int fd, |
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IOCanRWHandler *fd_read_poll, |
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IOHandler *fd_read, |
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IOHandler *fd_write, |
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void *opaque);
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int qemu_set_fd_handler(int fd, |
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IOHandler *fd_read, |
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IOHandler *fd_write, |
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void *opaque);
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/* Polling handling */
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/* return TRUE if no sleep should be done afterwards */
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typedef int PollingFunc(void *opaque); |
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int qemu_add_polling_cb(PollingFunc *func, void *opaque); |
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void qemu_del_polling_cb(PollingFunc *func, void *opaque); |
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#ifdef _WIN32
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/* Wait objects handling */
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typedef void WaitObjectFunc(void *opaque); |
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int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
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void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
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#endif
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typedef struct QEMUBH QEMUBH; |
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/* character device */
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#define CHR_EVENT_BREAK 0 /* serial break char */ |
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#define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
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#define CHR_EVENT_RESET 2 /* new connection established */ |
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#define CHR_IOCTL_SERIAL_SET_PARAMS 1 |
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typedef struct { |
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int speed;
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int parity;
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int data_bits;
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int stop_bits;
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} QEMUSerialSetParams; |
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#define CHR_IOCTL_SERIAL_SET_BREAK 2 |
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#define CHR_IOCTL_PP_READ_DATA 3 |
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#define CHR_IOCTL_PP_WRITE_DATA 4 |
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#define CHR_IOCTL_PP_READ_CONTROL 5 |
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#define CHR_IOCTL_PP_WRITE_CONTROL 6 |
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#define CHR_IOCTL_PP_READ_STATUS 7 |
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#define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
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#define CHR_IOCTL_PP_EPP_READ 9 |
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#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
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#define CHR_IOCTL_PP_EPP_WRITE 11 |
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typedef void IOEventHandler(void *opaque, int event); |
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typedef struct CharDriverState { |
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int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); |
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void (*chr_update_read_handler)(struct CharDriverState *s); |
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int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
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IOEventHandler *chr_event; |
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IOCanRWHandler *chr_can_read; |
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IOReadHandler *chr_read; |
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void *handler_opaque;
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void (*chr_send_event)(struct CharDriverState *chr, int event); |
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void (*chr_close)(struct CharDriverState *chr); |
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void *opaque;
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int focus;
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QEMUBH *bh; |
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} CharDriverState; |
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CharDriverState *qemu_chr_open(const char *filename); |
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void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
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int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); |
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void qemu_chr_send_event(CharDriverState *s, int event); |
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void qemu_chr_add_handlers(CharDriverState *s,
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IOCanRWHandler *fd_can_read, |
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IOReadHandler *fd_read, |
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IOEventHandler *fd_event, |
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void *opaque);
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int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
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void qemu_chr_reset(CharDriverState *s);
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int qemu_chr_can_read(CharDriverState *s);
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void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); |
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/* consoles */
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typedef struct DisplayState DisplayState; |
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typedef struct TextConsole TextConsole; |
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typedef void (*vga_hw_update_ptr)(void *); |
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typedef void (*vga_hw_invalidate_ptr)(void *); |
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typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
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TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
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vga_hw_invalidate_ptr invalidate, |
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vga_hw_screen_dump_ptr screen_dump, |
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void *opaque);
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void vga_hw_update(void); |
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void vga_hw_invalidate(void); |
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void vga_hw_screen_dump(const char *filename); |
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int is_graphic_console(void); |
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CharDriverState *text_console_init(DisplayState *ds); |
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void console_select(unsigned int index); |
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/* serial ports */
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#define MAX_SERIAL_PORTS 4 |
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extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
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/* parallel ports */
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#define MAX_PARALLEL_PORTS 3 |
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extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
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struct ParallelIOArg {
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void *buffer;
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int count;
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}; |
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/* VLANs support */
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typedef struct VLANClientState VLANClientState; |
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struct VLANClientState {
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IOReadHandler *fd_read; |
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/* Packets may still be sent if this returns zero. It's used to
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rate-limit the slirp code. */
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IOCanRWHandler *fd_can_read; |
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void *opaque;
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struct VLANClientState *next;
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struct VLANState *vlan;
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char info_str[256]; |
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}; |
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typedef struct VLANState { |
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int id;
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VLANClientState *first_client; |
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struct VLANState *next;
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} VLANState; |
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VLANState *qemu_find_vlan(int id);
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VLANClientState *qemu_new_vlan_client(VLANState *vlan, |
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IOReadHandler *fd_read, |
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IOCanRWHandler *fd_can_read, |
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void *opaque);
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int qemu_can_send_packet(VLANClientState *vc);
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void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
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void qemu_handler_true(void *opaque); |
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void do_info_network(void); |
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/* TAP win32 */
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int tap_win32_init(VLANState *vlan, const char *ifname); |
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/* NIC info */
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#define MAX_NICS 8 |
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typedef struct NICInfo { |
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uint8_t macaddr[6];
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const char *model; |
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VLANState *vlan; |
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} NICInfo; |
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extern int nb_nics; |
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extern NICInfo nd_table[MAX_NICS];
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/* timers */
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typedef struct QEMUClock QEMUClock; |
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typedef struct QEMUTimer QEMUTimer; |
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typedef void QEMUTimerCB(void *opaque); |
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/* The real time clock should be used only for stuff which does not
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change the virtual machine state, as it is run even if the virtual
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machine is stopped. The real time clock has a frequency of 1000
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Hz. */
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extern QEMUClock *rt_clock;
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/* The virtual clock is only run during the emulation. It is stopped
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when the virtual machine is stopped. Virtual timers use a high
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precision clock, usually cpu cycles (use ticks_per_sec). */
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extern QEMUClock *vm_clock;
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int64_t qemu_get_clock(QEMUClock *clock); |
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QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
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void qemu_free_timer(QEMUTimer *ts);
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void qemu_del_timer(QEMUTimer *ts);
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void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
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int qemu_timer_pending(QEMUTimer *ts);
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extern int64_t ticks_per_sec;
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extern int pit_min_timer_count; |
440 |
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int64_t cpu_get_ticks(void);
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void cpu_enable_ticks(void); |
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void cpu_disable_ticks(void); |
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/* VM Load/Save */
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typedef struct QEMUFile QEMUFile; |
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QEMUFile *qemu_fopen(const char *filename, const char *mode); |
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void qemu_fflush(QEMUFile *f);
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void qemu_fclose(QEMUFile *f);
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void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
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void qemu_put_byte(QEMUFile *f, int v); |
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void qemu_put_be16(QEMUFile *f, unsigned int v); |
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void qemu_put_be32(QEMUFile *f, unsigned int v); |
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void qemu_put_be64(QEMUFile *f, uint64_t v);
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int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
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int qemu_get_byte(QEMUFile *f);
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unsigned int qemu_get_be16(QEMUFile *f); |
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unsigned int qemu_get_be32(QEMUFile *f); |
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uint64_t qemu_get_be64(QEMUFile *f); |
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static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
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{ |
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qemu_put_be64(f, *pv); |
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} |
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|
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static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
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{ |
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qemu_put_be32(f, *pv); |
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} |
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|
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static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
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{ |
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qemu_put_be16(f, *pv); |
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} |
477 |
|
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static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
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{ |
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qemu_put_byte(f, *pv); |
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} |
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|
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static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
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{ |
485 |
*pv = qemu_get_be64(f); |
486 |
} |
487 |
|
488 |
static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
489 |
{ |
490 |
*pv = qemu_get_be32(f); |
491 |
} |
492 |
|
493 |
static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
494 |
{ |
495 |
*pv = qemu_get_be16(f); |
496 |
} |
497 |
|
498 |
static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
499 |
{ |
500 |
*pv = qemu_get_byte(f); |
501 |
} |
502 |
|
503 |
#if TARGET_LONG_BITS == 64 |
504 |
#define qemu_put_betl qemu_put_be64
|
505 |
#define qemu_get_betl qemu_get_be64
|
506 |
#define qemu_put_betls qemu_put_be64s
|
507 |
#define qemu_get_betls qemu_get_be64s
|
508 |
#else
|
509 |
#define qemu_put_betl qemu_put_be32
|
510 |
#define qemu_get_betl qemu_get_be32
|
511 |
#define qemu_put_betls qemu_put_be32s
|
512 |
#define qemu_get_betls qemu_get_be32s
|
513 |
#endif
|
514 |
|
515 |
int64_t qemu_ftell(QEMUFile *f); |
516 |
int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
|
517 |
|
518 |
typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
519 |
typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
520 |
|
521 |
int register_savevm(const char *idstr, |
522 |
int instance_id,
|
523 |
int version_id,
|
524 |
SaveStateHandler *save_state, |
525 |
LoadStateHandler *load_state, |
526 |
void *opaque);
|
527 |
void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
|
528 |
void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
|
529 |
|
530 |
void cpu_save(QEMUFile *f, void *opaque); |
531 |
int cpu_load(QEMUFile *f, void *opaque, int version_id); |
532 |
|
533 |
void do_savevm(const char *name); |
534 |
void do_loadvm(const char *name); |
535 |
void do_delvm(const char *name); |
536 |
void do_info_snapshots(void); |
537 |
|
538 |
/* bottom halves */
|
539 |
typedef void QEMUBHFunc(void *opaque); |
540 |
|
541 |
QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
|
542 |
void qemu_bh_schedule(QEMUBH *bh);
|
543 |
void qemu_bh_cancel(QEMUBH *bh);
|
544 |
void qemu_bh_delete(QEMUBH *bh);
|
545 |
int qemu_bh_poll(void); |
546 |
|
547 |
/* block.c */
|
548 |
typedef struct BlockDriverState BlockDriverState; |
549 |
typedef struct BlockDriver BlockDriver; |
550 |
|
551 |
extern BlockDriver bdrv_raw;
|
552 |
extern BlockDriver bdrv_host_device;
|
553 |
extern BlockDriver bdrv_cow;
|
554 |
extern BlockDriver bdrv_qcow;
|
555 |
extern BlockDriver bdrv_vmdk;
|
556 |
extern BlockDriver bdrv_cloop;
|
557 |
extern BlockDriver bdrv_dmg;
|
558 |
extern BlockDriver bdrv_bochs;
|
559 |
extern BlockDriver bdrv_vpc;
|
560 |
extern BlockDriver bdrv_vvfat;
|
561 |
extern BlockDriver bdrv_qcow2;
|
562 |
|
563 |
typedef struct BlockDriverInfo { |
564 |
/* in bytes, 0 if irrelevant */
|
565 |
int cluster_size;
|
566 |
/* offset at which the VM state can be saved (0 if not possible) */
|
567 |
int64_t vm_state_offset; |
568 |
} BlockDriverInfo; |
569 |
|
570 |
typedef struct QEMUSnapshotInfo { |
571 |
char id_str[128]; /* unique snapshot id */ |
572 |
/* the following fields are informative. They are not needed for
|
573 |
the consistency of the snapshot */
|
574 |
char name[256]; /* user choosen name */ |
575 |
uint32_t vm_state_size; /* VM state info size */
|
576 |
uint32_t date_sec; /* UTC date of the snapshot */
|
577 |
uint32_t date_nsec; |
578 |
uint64_t vm_clock_nsec; /* VM clock relative to boot */
|
579 |
} QEMUSnapshotInfo; |
580 |
|
581 |
#define BDRV_O_RDONLY 0x0000 |
582 |
#define BDRV_O_RDWR 0x0002 |
583 |
#define BDRV_O_ACCESS 0x0003 |
584 |
#define BDRV_O_CREAT 0x0004 /* create an empty file */ |
585 |
#define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */ |
586 |
#define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to |
587 |
use a disk image format on top of
|
588 |
it (default for
|
589 |
bdrv_file_open()) */
|
590 |
|
591 |
void bdrv_init(void); |
592 |
BlockDriver *bdrv_find_format(const char *format_name); |
593 |
int bdrv_create(BlockDriver *drv,
|
594 |
const char *filename, int64_t size_in_sectors, |
595 |
const char *backing_file, int flags); |
596 |
BlockDriverState *bdrv_new(const char *device_name); |
597 |
void bdrv_delete(BlockDriverState *bs);
|
598 |
int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags); |
599 |
int bdrv_open(BlockDriverState *bs, const char *filename, int flags); |
600 |
int bdrv_open2(BlockDriverState *bs, const char *filename, int flags, |
601 |
BlockDriver *drv); |
602 |
void bdrv_close(BlockDriverState *bs);
|
603 |
int bdrv_read(BlockDriverState *bs, int64_t sector_num,
|
604 |
uint8_t *buf, int nb_sectors);
|
605 |
int bdrv_write(BlockDriverState *bs, int64_t sector_num,
|
606 |
const uint8_t *buf, int nb_sectors); |
607 |
int bdrv_pread(BlockDriverState *bs, int64_t offset,
|
608 |
void *buf, int count); |
609 |
int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
|
610 |
const void *buf, int count); |
611 |
int bdrv_truncate(BlockDriverState *bs, int64_t offset);
|
612 |
int64_t bdrv_getlength(BlockDriverState *bs); |
613 |
void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
|
614 |
int bdrv_commit(BlockDriverState *bs);
|
615 |
void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size); |
616 |
/* async block I/O */
|
617 |
typedef struct BlockDriverAIOCB BlockDriverAIOCB; |
618 |
typedef void BlockDriverCompletionFunc(void *opaque, int ret); |
619 |
|
620 |
BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num, |
621 |
uint8_t *buf, int nb_sectors,
|
622 |
BlockDriverCompletionFunc *cb, void *opaque);
|
623 |
BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num, |
624 |
const uint8_t *buf, int nb_sectors, |
625 |
BlockDriverCompletionFunc *cb, void *opaque);
|
626 |
void bdrv_aio_cancel(BlockDriverAIOCB *acb);
|
627 |
|
628 |
void qemu_aio_init(void); |
629 |
void qemu_aio_poll(void); |
630 |
void qemu_aio_flush(void); |
631 |
void qemu_aio_wait_start(void); |
632 |
void qemu_aio_wait(void); |
633 |
void qemu_aio_wait_end(void); |
634 |
|
635 |
/* Ensure contents are flushed to disk. */
|
636 |
void bdrv_flush(BlockDriverState *bs);
|
637 |
|
638 |
#define BDRV_TYPE_HD 0 |
639 |
#define BDRV_TYPE_CDROM 1 |
640 |
#define BDRV_TYPE_FLOPPY 2 |
641 |
#define BIOS_ATA_TRANSLATION_AUTO 0 |
642 |
#define BIOS_ATA_TRANSLATION_NONE 1 |
643 |
#define BIOS_ATA_TRANSLATION_LBA 2 |
644 |
#define BIOS_ATA_TRANSLATION_LARGE 3 |
645 |
#define BIOS_ATA_TRANSLATION_RECHS 4 |
646 |
|
647 |
void bdrv_set_geometry_hint(BlockDriverState *bs,
|
648 |
int cyls, int heads, int secs); |
649 |
void bdrv_set_type_hint(BlockDriverState *bs, int type); |
650 |
void bdrv_set_translation_hint(BlockDriverState *bs, int translation); |
651 |
void bdrv_get_geometry_hint(BlockDriverState *bs,
|
652 |
int *pcyls, int *pheads, int *psecs); |
653 |
int bdrv_get_type_hint(BlockDriverState *bs);
|
654 |
int bdrv_get_translation_hint(BlockDriverState *bs);
|
655 |
int bdrv_is_removable(BlockDriverState *bs);
|
656 |
int bdrv_is_read_only(BlockDriverState *bs);
|
657 |
int bdrv_is_inserted(BlockDriverState *bs);
|
658 |
int bdrv_media_changed(BlockDriverState *bs);
|
659 |
int bdrv_is_locked(BlockDriverState *bs);
|
660 |
void bdrv_set_locked(BlockDriverState *bs, int locked); |
661 |
void bdrv_eject(BlockDriverState *bs, int eject_flag); |
662 |
void bdrv_set_change_cb(BlockDriverState *bs,
|
663 |
void (*change_cb)(void *opaque), void *opaque); |
664 |
void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size); |
665 |
void bdrv_info(void); |
666 |
BlockDriverState *bdrv_find(const char *name); |
667 |
void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque); |
668 |
int bdrv_is_encrypted(BlockDriverState *bs);
|
669 |
int bdrv_set_key(BlockDriverState *bs, const char *key); |
670 |
void bdrv_iterate_format(void (*it)(void *opaque, const char *name), |
671 |
void *opaque);
|
672 |
const char *bdrv_get_device_name(BlockDriverState *bs); |
673 |
int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
|
674 |
const uint8_t *buf, int nb_sectors); |
675 |
int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
|
676 |
|
677 |
void bdrv_get_backing_filename(BlockDriverState *bs,
|
678 |
char *filename, int filename_size); |
679 |
int bdrv_snapshot_create(BlockDriverState *bs,
|
680 |
QEMUSnapshotInfo *sn_info); |
681 |
int bdrv_snapshot_goto(BlockDriverState *bs,
|
682 |
const char *snapshot_id); |
683 |
int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id); |
684 |
int bdrv_snapshot_list(BlockDriverState *bs,
|
685 |
QEMUSnapshotInfo **psn_info); |
686 |
char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn); |
687 |
|
688 |
char *get_human_readable_size(char *buf, int buf_size, int64_t size); |
689 |
int path_is_absolute(const char *path); |
690 |
void path_combine(char *dest, int dest_size, |
691 |
const char *base_path, |
692 |
const char *filename); |
693 |
|
694 |
#ifndef QEMU_TOOL
|
695 |
|
696 |
typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
697 |
int boot_device,
|
698 |
DisplayState *ds, const char **fd_filename, int snapshot, |
699 |
const char *kernel_filename, const char *kernel_cmdline, |
700 |
const char *initrd_filename, const char *cpu_model); |
701 |
|
702 |
typedef struct QEMUMachine { |
703 |
const char *name; |
704 |
const char *desc; |
705 |
QEMUMachineInitFunc *init; |
706 |
struct QEMUMachine *next;
|
707 |
} QEMUMachine; |
708 |
|
709 |
int qemu_register_machine(QEMUMachine *m);
|
710 |
|
711 |
typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
712 |
typedef void IRQRequestFunc(void *opaque, int level); |
713 |
|
714 |
#if defined(TARGET_PPC)
|
715 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
716 |
#endif
|
717 |
|
718 |
#if defined(TARGET_MIPS)
|
719 |
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
720 |
#endif
|
721 |
|
722 |
/* ISA bus */
|
723 |
|
724 |
extern target_phys_addr_t isa_mem_base;
|
725 |
|
726 |
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
727 |
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
728 |
|
729 |
int register_ioport_read(int start, int length, int size, |
730 |
IOPortReadFunc *func, void *opaque);
|
731 |
int register_ioport_write(int start, int length, int size, |
732 |
IOPortWriteFunc *func, void *opaque);
|
733 |
void isa_unassign_ioport(int start, int length); |
734 |
|
735 |
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
|
736 |
|
737 |
/* PCI bus */
|
738 |
|
739 |
extern target_phys_addr_t pci_mem_base;
|
740 |
|
741 |
typedef struct PCIBus PCIBus; |
742 |
typedef struct PCIDevice PCIDevice; |
743 |
|
744 |
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
745 |
uint32_t address, uint32_t data, int len);
|
746 |
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
747 |
uint32_t address, int len);
|
748 |
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
749 |
uint32_t addr, uint32_t size, int type);
|
750 |
|
751 |
#define PCI_ADDRESS_SPACE_MEM 0x00 |
752 |
#define PCI_ADDRESS_SPACE_IO 0x01 |
753 |
#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
754 |
|
755 |
typedef struct PCIIORegion { |
756 |
uint32_t addr; /* current PCI mapping address. -1 means not mapped */
|
757 |
uint32_t size; |
758 |
uint8_t type; |
759 |
PCIMapIORegionFunc *map_func; |
760 |
} PCIIORegion; |
761 |
|
762 |
#define PCI_ROM_SLOT 6 |
763 |
#define PCI_NUM_REGIONS 7 |
764 |
|
765 |
#define PCI_DEVICES_MAX 64 |
766 |
|
767 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
768 |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
769 |
#define PCI_COMMAND 0x04 /* 16 bits */ |
770 |
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
771 |
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
772 |
#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
773 |
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
774 |
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
775 |
#define PCI_MIN_GNT 0x3e /* 8 bits */ |
776 |
#define PCI_MAX_LAT 0x3f /* 8 bits */ |
777 |
|
778 |
struct PCIDevice {
|
779 |
/* PCI config space */
|
780 |
uint8_t config[256];
|
781 |
|
782 |
/* the following fields are read only */
|
783 |
PCIBus *bus; |
784 |
int devfn;
|
785 |
char name[64]; |
786 |
PCIIORegion io_regions[PCI_NUM_REGIONS]; |
787 |
|
788 |
/* do not access the following fields */
|
789 |
PCIConfigReadFunc *config_read; |
790 |
PCIConfigWriteFunc *config_write; |
791 |
/* ??? This is a PC-specific hack, and should be removed. */
|
792 |
int irq_index;
|
793 |
|
794 |
/* Current IRQ levels. Used internally by the generic PCI code. */
|
795 |
int irq_state[4]; |
796 |
}; |
797 |
|
798 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
799 |
int instance_size, int devfn, |
800 |
PCIConfigReadFunc *config_read, |
801 |
PCIConfigWriteFunc *config_write); |
802 |
|
803 |
void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
804 |
uint32_t size, int type,
|
805 |
PCIMapIORegionFunc *map_func); |
806 |
|
807 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
808 |
|
809 |
uint32_t pci_default_read_config(PCIDevice *d, |
810 |
uint32_t address, int len);
|
811 |
void pci_default_write_config(PCIDevice *d,
|
812 |
uint32_t address, uint32_t val, int len);
|
813 |
void pci_device_save(PCIDevice *s, QEMUFile *f);
|
814 |
int pci_device_load(PCIDevice *s, QEMUFile *f);
|
815 |
|
816 |
typedef void (*pci_set_irq_fn)(void *pic, int irq_num, int level); |
817 |
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
818 |
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
819 |
void *pic, int devfn_min, int nirq); |
820 |
|
821 |
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
822 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
823 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
824 |
int pci_bus_num(PCIBus *s);
|
825 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
826 |
|
827 |
void pci_info(void); |
828 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
829 |
pci_map_irq_fn map_irq, const char *name); |
830 |
|
831 |
/* prep_pci.c */
|
832 |
PCIBus *pci_prep_init(void);
|
833 |
|
834 |
/* grackle_pci.c */
|
835 |
PCIBus *pci_grackle_init(uint32_t base, void *pic);
|
836 |
|
837 |
/* unin_pci.c */
|
838 |
PCIBus *pci_pmac_init(void *pic);
|
839 |
|
840 |
/* apb_pci.c */
|
841 |
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base, |
842 |
void *pic);
|
843 |
|
844 |
PCIBus *pci_vpb_init(void *pic, int irq, int realview); |
845 |
|
846 |
/* piix_pci.c */
|
847 |
PCIBus *i440fx_init(PCIDevice **pi440fx_state); |
848 |
void i440fx_set_smm(PCIDevice *d, int val); |
849 |
int piix3_init(PCIBus *bus, int devfn); |
850 |
void i440fx_init_memory_mappings(PCIDevice *d);
|
851 |
|
852 |
int piix4_init(PCIBus *bus, int devfn); |
853 |
|
854 |
/* openpic.c */
|
855 |
typedef struct openpic_t openpic_t; |
856 |
enum {
|
857 |
OPENPIC_EVT_INT = 0, /* IRQ */ |
858 |
OPENPIC_EVT_CINT, /* critical IRQ */
|
859 |
OPENPIC_EVT_MCK, /* Machine check event */
|
860 |
OPENPIC_EVT_DEBUG, /* Inconditional debug event */
|
861 |
OPENPIC_EVT_RESET, /* Core reset event */
|
862 |
}; |
863 |
void openpic_set_irq(void *opaque, int n_IRQ, int level); |
864 |
openpic_t *openpic_init (PCIBus *bus, SetIRQFunc *set_irq, |
865 |
int *pmem_index, int nb_cpus, |
866 |
struct CPUState **envp);
|
867 |
|
868 |
/* heathrow_pic.c */
|
869 |
typedef struct HeathrowPICS HeathrowPICS; |
870 |
void heathrow_pic_set_irq(void *opaque, int num, int level); |
871 |
HeathrowPICS *heathrow_pic_init(int *pmem_index);
|
872 |
|
873 |
/* gt64xxx.c */
|
874 |
PCIBus *pci_gt64120_init(void *pic);
|
875 |
|
876 |
#ifdef HAS_AUDIO
|
877 |
struct soundhw {
|
878 |
const char *name; |
879 |
const char *descr; |
880 |
int enabled;
|
881 |
int isa;
|
882 |
union {
|
883 |
int (*init_isa) (AudioState *s);
|
884 |
int (*init_pci) (PCIBus *bus, AudioState *s);
|
885 |
} init; |
886 |
}; |
887 |
|
888 |
extern struct soundhw soundhw[]; |
889 |
#endif
|
890 |
|
891 |
/* vga.c */
|
892 |
|
893 |
#define VGA_RAM_SIZE (8192 * 1024) |
894 |
|
895 |
struct DisplayState {
|
896 |
uint8_t *data; |
897 |
int linesize;
|
898 |
int depth;
|
899 |
int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
900 |
int width;
|
901 |
int height;
|
902 |
void *opaque;
|
903 |
|
904 |
void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
905 |
void (*dpy_resize)(struct DisplayState *s, int w, int h); |
906 |
void (*dpy_refresh)(struct DisplayState *s); |
907 |
void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
908 |
int dst_x, int dst_y, int w, int h); |
909 |
void (*dpy_fill)(struct DisplayState *s, int x, int y, |
910 |
int w, int h, uint32_t c); |
911 |
void (*mouse_set)(int x, int y, int on); |
912 |
void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
913 |
uint8_t *image, uint8_t *mask); |
914 |
}; |
915 |
|
916 |
static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
917 |
{ |
918 |
s->dpy_update(s, x, y, w, h); |
919 |
} |
920 |
|
921 |
static inline void dpy_resize(DisplayState *s, int w, int h) |
922 |
{ |
923 |
s->dpy_resize(s, w, h); |
924 |
} |
925 |
|
926 |
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
927 |
unsigned long vga_ram_offset, int vga_ram_size); |
928 |
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
929 |
unsigned long vga_ram_offset, int vga_ram_size, |
930 |
unsigned long vga_bios_offset, int vga_bios_size); |
931 |
|
932 |
/* cirrus_vga.c */
|
933 |
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
934 |
unsigned long vga_ram_offset, int vga_ram_size); |
935 |
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
936 |
unsigned long vga_ram_offset, int vga_ram_size); |
937 |
|
938 |
/* vmware_vga.c */
|
939 |
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
940 |
unsigned long vga_ram_offset, int vga_ram_size); |
941 |
|
942 |
/* sdl.c */
|
943 |
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
944 |
|
945 |
/* cocoa.m */
|
946 |
void cocoa_display_init(DisplayState *ds, int full_screen); |
947 |
|
948 |
/* vnc.c */
|
949 |
void vnc_display_init(DisplayState *ds, const char *display); |
950 |
void do_info_vnc(void); |
951 |
|
952 |
/* x_keymap.c */
|
953 |
extern uint8_t _translate_keycode(const int key); |
954 |
|
955 |
/* ide.c */
|
956 |
#define MAX_DISKS 4 |
957 |
|
958 |
extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
959 |
extern BlockDriverState *sd_bdrv;
|
960 |
|
961 |
void isa_ide_init(int iobase, int iobase2, int irq, |
962 |
BlockDriverState *hd0, BlockDriverState *hd1); |
963 |
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
964 |
int secondary_ide_enabled);
|
965 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn); |
966 |
int pmac_ide_init (BlockDriverState **hd_table,
|
967 |
SetIRQFunc *set_irq, void *irq_opaque, int irq); |
968 |
|
969 |
/* cdrom.c */
|
970 |
int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); |
971 |
int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); |
972 |
|
973 |
/* ds1225y.c */
|
974 |
typedef struct ds1225y_t ds1225y_t; |
975 |
ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename); |
976 |
|
977 |
/* es1370.c */
|
978 |
int es1370_init (PCIBus *bus, AudioState *s);
|
979 |
|
980 |
/* sb16.c */
|
981 |
int SB16_init (AudioState *s);
|
982 |
|
983 |
/* adlib.c */
|
984 |
int Adlib_init (AudioState *s);
|
985 |
|
986 |
/* gus.c */
|
987 |
int GUS_init (AudioState *s);
|
988 |
|
989 |
/* dma.c */
|
990 |
typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
991 |
int DMA_get_channel_mode (int nchan); |
992 |
int DMA_read_memory (int nchan, void *buf, int pos, int size); |
993 |
int DMA_write_memory (int nchan, void *buf, int pos, int size); |
994 |
void DMA_hold_DREQ (int nchan); |
995 |
void DMA_release_DREQ (int nchan); |
996 |
void DMA_schedule(int nchan); |
997 |
void DMA_run (void); |
998 |
void DMA_init (int high_page_enable); |
999 |
void DMA_register_channel (int nchan, |
1000 |
DMA_transfer_handler transfer_handler, |
1001 |
void *opaque);
|
1002 |
/* fdc.c */
|
1003 |
#define MAX_FD 2 |
1004 |
extern BlockDriverState *fd_table[MAX_FD];
|
1005 |
|
1006 |
typedef struct fdctrl_t fdctrl_t; |
1007 |
|
1008 |
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, |
1009 |
uint32_t io_base, |
1010 |
BlockDriverState **fds); |
1011 |
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
1012 |
|
1013 |
/* eepro100.c */
|
1014 |
|
1015 |
void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
1016 |
void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
1017 |
void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
1018 |
|
1019 |
/* ne2000.c */
|
1020 |
|
1021 |
void isa_ne2000_init(int base, int irq, NICInfo *nd); |
1022 |
void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
1023 |
|
1024 |
/* rtl8139.c */
|
1025 |
|
1026 |
void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
1027 |
|
1028 |
/* pcnet.c */
|
1029 |
|
1030 |
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
1031 |
void pcnet_h_reset(void *opaque); |
1032 |
void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque); |
1033 |
|
1034 |
/* vmmouse.c */
|
1035 |
void *vmmouse_init(void *m); |
1036 |
|
1037 |
/* pckbd.c */
|
1038 |
|
1039 |
void kbd_init(void); |
1040 |
|
1041 |
/* mc146818rtc.c */
|
1042 |
|
1043 |
typedef struct RTCState RTCState; |
1044 |
|
1045 |
RTCState *rtc_init(int base, int irq); |
1046 |
void rtc_set_memory(RTCState *s, int addr, int val); |
1047 |
void rtc_set_date(RTCState *s, const struct tm *tm); |
1048 |
|
1049 |
/* serial.c */
|
1050 |
|
1051 |
typedef struct SerialState SerialState; |
1052 |
SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
|
1053 |
int base, int irq, CharDriverState *chr); |
1054 |
SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
|
1055 |
target_ulong base, int it_shift,
|
1056 |
int irq, CharDriverState *chr,
|
1057 |
int ioregister);
|
1058 |
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
|
1059 |
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); |
1060 |
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
|
1061 |
void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); |
1062 |
uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
|
1063 |
void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); |
1064 |
|
1065 |
/* parallel.c */
|
1066 |
|
1067 |
typedef struct ParallelState ParallelState; |
1068 |
ParallelState *parallel_init(int base, int irq, CharDriverState *chr); |
1069 |
|
1070 |
/* i8259.c */
|
1071 |
|
1072 |
typedef struct PicState2 PicState2; |
1073 |
extern PicState2 *isa_pic;
|
1074 |
void pic_set_irq(int irq, int level); |
1075 |
void pic_set_irq_new(void *opaque, int irq, int level); |
1076 |
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque);
|
1077 |
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
1078 |
void *alt_irq_opaque);
|
1079 |
int pic_read_irq(PicState2 *s);
|
1080 |
void pic_update_irq(PicState2 *s);
|
1081 |
uint32_t pic_intack_read(PicState2 *s); |
1082 |
void pic_info(void); |
1083 |
void irq_info(void); |
1084 |
|
1085 |
/* APIC */
|
1086 |
typedef struct IOAPICState IOAPICState; |
1087 |
|
1088 |
int apic_init(CPUState *env);
|
1089 |
int apic_get_interrupt(CPUState *env);
|
1090 |
IOAPICState *ioapic_init(void);
|
1091 |
void ioapic_set_irq(void *opaque, int vector, int level); |
1092 |
|
1093 |
/* i8254.c */
|
1094 |
|
1095 |
#define PIT_FREQ 1193182 |
1096 |
|
1097 |
typedef struct PITState PITState; |
1098 |
|
1099 |
PITState *pit_init(int base, int irq); |
1100 |
void pit_set_gate(PITState *pit, int channel, int val); |
1101 |
int pit_get_gate(PITState *pit, int channel); |
1102 |
int pit_get_initial_count(PITState *pit, int channel); |
1103 |
int pit_get_mode(PITState *pit, int channel); |
1104 |
int pit_get_out(PITState *pit, int channel, int64_t current_time); |
1105 |
|
1106 |
/* pcspk.c */
|
1107 |
void pcspk_init(PITState *);
|
1108 |
int pcspk_audio_init(AudioState *);
|
1109 |
|
1110 |
#include "hw/smbus.h" |
1111 |
|
1112 |
/* acpi.c */
|
1113 |
extern int acpi_enabled; |
1114 |
void piix4_pm_init(PCIBus *bus, int devfn); |
1115 |
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
1116 |
void acpi_bios_init(void); |
1117 |
|
1118 |
/* smbus_eeprom.c */
|
1119 |
SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf); |
1120 |
|
1121 |
/* pc.c */
|
1122 |
extern QEMUMachine pc_machine;
|
1123 |
extern QEMUMachine isapc_machine;
|
1124 |
extern int fd_bootchk; |
1125 |
|
1126 |
void ioport_set_a20(int enable); |
1127 |
int ioport_get_a20(void); |
1128 |
|
1129 |
/* ppc.c */
|
1130 |
extern QEMUMachine prep_machine;
|
1131 |
extern QEMUMachine core99_machine;
|
1132 |
extern QEMUMachine heathrow_machine;
|
1133 |
|
1134 |
/* mips_r4k.c */
|
1135 |
extern QEMUMachine mips_machine;
|
1136 |
|
1137 |
/* mips_malta.c */
|
1138 |
extern QEMUMachine mips_malta_machine;
|
1139 |
|
1140 |
/* mips_int */
|
1141 |
extern void cpu_mips_irq_request(void *opaque, int irq, int level); |
1142 |
|
1143 |
/* mips_timer.c */
|
1144 |
extern void cpu_mips_clock_init(CPUState *); |
1145 |
extern void cpu_mips_irqctrl_init (void); |
1146 |
|
1147 |
/* shix.c */
|
1148 |
extern QEMUMachine shix_machine;
|
1149 |
|
1150 |
#ifdef TARGET_PPC
|
1151 |
/* PowerPC hardware exceptions management helpers */
|
1152 |
void ppc_set_irq (void *opaque, int n_IRQ, int level); |
1153 |
void ppc_openpic_irq (void *opaque, int n_IRQ, int level); |
1154 |
int ppc_hw_interrupt (CPUState *env);
|
1155 |
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
1156 |
#endif
|
1157 |
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1158 |
|
1159 |
extern CPUWriteMemoryFunc *PPC_io_write[];
|
1160 |
extern CPUReadMemoryFunc *PPC_io_read[];
|
1161 |
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1162 |
|
1163 |
/* sun4m.c */
|
1164 |
extern QEMUMachine ss5_machine, ss10_machine;
|
1165 |
|
1166 |
/* iommu.c */
|
1167 |
void *iommu_init(uint32_t addr);
|
1168 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
1169 |
uint8_t *buf, int len, int is_write); |
1170 |
static inline void sparc_iommu_memory_read(void *opaque, |
1171 |
target_phys_addr_t addr, |
1172 |
uint8_t *buf, int len)
|
1173 |
{ |
1174 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
|
1175 |
} |
1176 |
|
1177 |
static inline void sparc_iommu_memory_write(void *opaque, |
1178 |
target_phys_addr_t addr, |
1179 |
uint8_t *buf, int len)
|
1180 |
{ |
1181 |
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
|
1182 |
} |
1183 |
|
1184 |
/* tcx.c */
|
1185 |
void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
|
1186 |
unsigned long vram_offset, int vram_size, int width, int height); |
1187 |
|
1188 |
/* slavio_intctl.c */
|
1189 |
void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu); |
1190 |
void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
|
1191 |
const uint32_t *intbit_to_level);
|
1192 |
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env); |
1193 |
void slavio_pic_info(void *opaque); |
1194 |
void slavio_irq_info(void *opaque); |
1195 |
void slavio_pic_set_irq(void *opaque, int irq, int level); |
1196 |
void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu); |
1197 |
|
1198 |
/* loader.c */
|
1199 |
int get_image_size(const char *filename); |
1200 |
int load_image(const char *filename, uint8_t *addr); |
1201 |
int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1202 |
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); |
1203 |
int load_aout(const char *filename, uint8_t *addr); |
1204 |
int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
1205 |
|
1206 |
/* slavio_timer.c */
|
1207 |
void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu, |
1208 |
void *intctl);
|
1209 |
|
1210 |
/* slavio_serial.c */
|
1211 |
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, |
1212 |
CharDriverState *chr2, void *intctl);
|
1213 |
void slavio_serial_ms_kbd_init(int base, int irq, void *intctl); |
1214 |
|
1215 |
/* slavio_misc.c */
|
1216 |
void *slavio_misc_init(uint32_t base, int irq, void *intctl); |
1217 |
void slavio_set_power_fail(void *opaque, int power_failing); |
1218 |
|
1219 |
/* esp.c */
|
1220 |
void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1221 |
void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque); |
1222 |
void esp_reset(void *opaque); |
1223 |
|
1224 |
/* sparc32_dma.c */
|
1225 |
void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, |
1226 |
void *intctl);
|
1227 |
void ledma_set_irq(void *opaque, int isr); |
1228 |
void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
1229 |
uint8_t *buf, int len, int do_bswap); |
1230 |
void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
1231 |
uint8_t *buf, int len, int do_bswap); |
1232 |
void espdma_raise_irq(void *opaque); |
1233 |
void espdma_clear_irq(void *opaque); |
1234 |
void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1235 |
void espdma_memory_write(void *opaque, uint8_t *buf, int len); |
1236 |
void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque, |
1237 |
void *lance_opaque);
|
1238 |
|
1239 |
/* cs4231.c */
|
1240 |
void cs_init(target_phys_addr_t base, int irq, void *intctl); |
1241 |
|
1242 |
/* sun4u.c */
|
1243 |
extern QEMUMachine sun4u_machine;
|
1244 |
|
1245 |
/* NVRAM helpers */
|
1246 |
#include "hw/m48t59.h" |
1247 |
|
1248 |
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
|
1249 |
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr); |
1250 |
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
|
1251 |
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr); |
1252 |
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
|
1253 |
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr); |
1254 |
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
1255 |
const unsigned char *str, uint32_t max); |
1256 |
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max); |
1257 |
void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
|
1258 |
uint32_t start, uint32_t count); |
1259 |
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
1260 |
const unsigned char *arch, |
1261 |
uint32_t RAM_size, int boot_device,
|
1262 |
uint32_t kernel_image, uint32_t kernel_size, |
1263 |
const char *cmdline, |
1264 |
uint32_t initrd_image, uint32_t initrd_size, |
1265 |
uint32_t NVRAM_image, |
1266 |
int width, int height, int depth); |
1267 |
|
1268 |
/* adb.c */
|
1269 |
|
1270 |
#define MAX_ADB_DEVICES 16 |
1271 |
|
1272 |
#define ADB_MAX_OUT_LEN 16 |
1273 |
|
1274 |
typedef struct ADBDevice ADBDevice; |
1275 |
|
1276 |
/* buf = NULL means polling */
|
1277 |
typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, |
1278 |
const uint8_t *buf, int len); |
1279 |
typedef int ADBDeviceReset(ADBDevice *d); |
1280 |
|
1281 |
struct ADBDevice {
|
1282 |
struct ADBBusState *bus;
|
1283 |
int devaddr;
|
1284 |
int handler;
|
1285 |
ADBDeviceRequest *devreq; |
1286 |
ADBDeviceReset *devreset; |
1287 |
void *opaque;
|
1288 |
}; |
1289 |
|
1290 |
typedef struct ADBBusState { |
1291 |
ADBDevice devices[MAX_ADB_DEVICES]; |
1292 |
int nb_devices;
|
1293 |
int poll_index;
|
1294 |
} ADBBusState; |
1295 |
|
1296 |
int adb_request(ADBBusState *s, uint8_t *buf_out,
|
1297 |
const uint8_t *buf, int len); |
1298 |
int adb_poll(ADBBusState *s, uint8_t *buf_out);
|
1299 |
|
1300 |
ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
|
1301 |
ADBDeviceRequest *devreq, |
1302 |
ADBDeviceReset *devreset, |
1303 |
void *opaque);
|
1304 |
void adb_kbd_init(ADBBusState *bus);
|
1305 |
void adb_mouse_init(ADBBusState *bus);
|
1306 |
|
1307 |
/* cuda.c */
|
1308 |
|
1309 |
extern ADBBusState adb_bus;
|
1310 |
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq); |
1311 |
|
1312 |
#include "hw/usb.h" |
1313 |
|
1314 |
/* usb ports of the VM */
|
1315 |
|
1316 |
void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1317 |
usb_attachfn attach); |
1318 |
|
1319 |
#define VM_USB_HUB_SIZE 8 |
1320 |
|
1321 |
void do_usb_add(const char *devname); |
1322 |
void do_usb_del(const char *devname); |
1323 |
void usb_info(void); |
1324 |
|
1325 |
/* scsi-disk.c */
|
1326 |
enum scsi_reason {
|
1327 |
SCSI_REASON_DONE, /* Command complete. */
|
1328 |
SCSI_REASON_DATA /* Transfer complete, more data required. */
|
1329 |
}; |
1330 |
|
1331 |
typedef struct SCSIDevice SCSIDevice; |
1332 |
typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1333 |
uint32_t arg); |
1334 |
|
1335 |
SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, |
1336 |
int tcq,
|
1337 |
scsi_completionfn completion, |
1338 |
void *opaque);
|
1339 |
void scsi_disk_destroy(SCSIDevice *s);
|
1340 |
|
1341 |
int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
|
1342 |
/* SCSI data transfers are asynchrnonous. However, unlike the block IO
|
1343 |
layer the completion routine may be called directly by
|
1344 |
scsi_{read,write}_data. */
|
1345 |
void scsi_read_data(SCSIDevice *s, uint32_t tag);
|
1346 |
int scsi_write_data(SCSIDevice *s, uint32_t tag);
|
1347 |
void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
|
1348 |
uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); |
1349 |
|
1350 |
/* lsi53c895a.c */
|
1351 |
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1352 |
void *lsi_scsi_init(PCIBus *bus, int devfn); |
1353 |
|
1354 |
/* integratorcp.c */
|
1355 |
extern QEMUMachine integratorcp_machine;
|
1356 |
|
1357 |
/* versatilepb.c */
|
1358 |
extern QEMUMachine versatilepb_machine;
|
1359 |
extern QEMUMachine versatileab_machine;
|
1360 |
|
1361 |
/* realview.c */
|
1362 |
extern QEMUMachine realview_machine;
|
1363 |
|
1364 |
/* ps2.c */
|
1365 |
void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); |
1366 |
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); |
1367 |
void ps2_write_mouse(void *, int val); |
1368 |
void ps2_write_keyboard(void *, int val); |
1369 |
uint32_t ps2_read_data(void *);
|
1370 |
void ps2_queue(void *, int b); |
1371 |
void ps2_keyboard_set_translation(void *opaque, int mode); |
1372 |
void ps2_mouse_fake_event(void *opaque); |
1373 |
|
1374 |
/* smc91c111.c */
|
1375 |
void smc91c111_init(NICInfo *, uint32_t, void *, int); |
1376 |
|
1377 |
/* pl110.c */
|
1378 |
void *pl110_init(DisplayState *ds, uint32_t base, void *pic, int irq, int); |
1379 |
|
1380 |
/* pl011.c */
|
1381 |
void pl011_init(uint32_t base, void *pic, int irq, CharDriverState *chr); |
1382 |
|
1383 |
/* pl050.c */
|
1384 |
void pl050_init(uint32_t base, void *pic, int irq, int is_mouse); |
1385 |
|
1386 |
/* pl080.c */
|
1387 |
void *pl080_init(uint32_t base, void *pic, int irq, int nchannels); |
1388 |
|
1389 |
/* pl181.c */
|
1390 |
void pl181_init(uint32_t base, BlockDriverState *bd,
|
1391 |
void *pic, int irq0, int irq1); |
1392 |
|
1393 |
/* pl190.c */
|
1394 |
void *pl190_init(uint32_t base, void *parent, int irq, int fiq); |
1395 |
|
1396 |
/* arm-timer.c */
|
1397 |
void sp804_init(uint32_t base, void *pic, int irq); |
1398 |
void icp_pit_init(uint32_t base, void *pic, int irq); |
1399 |
|
1400 |
/* arm_sysctl.c */
|
1401 |
void arm_sysctl_init(uint32_t base, uint32_t sys_id);
|
1402 |
|
1403 |
/* arm_gic.c */
|
1404 |
void *arm_gic_init(uint32_t base, void *parent, int parent_irq); |
1405 |
|
1406 |
/* arm_boot.c */
|
1407 |
|
1408 |
void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
1409 |
const char *kernel_cmdline, const char *initrd_filename, |
1410 |
int board_id);
|
1411 |
|
1412 |
/* sh7750.c */
|
1413 |
struct SH7750State;
|
1414 |
|
1415 |
struct SH7750State *sh7750_init(CPUState * cpu);
|
1416 |
|
1417 |
typedef struct { |
1418 |
/* The callback will be triggered if any of the designated lines change */
|
1419 |
uint16_t portamask_trigger; |
1420 |
uint16_t portbmask_trigger; |
1421 |
/* Return 0 if no action was taken */
|
1422 |
int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
1423 |
uint16_t * periph_pdtra, |
1424 |
uint16_t * periph_portdira, |
1425 |
uint16_t * periph_pdtrb, |
1426 |
uint16_t * periph_portdirb); |
1427 |
} sh7750_io_device; |
1428 |
|
1429 |
int sh7750_register_io_device(struct SH7750State *s, |
1430 |
sh7750_io_device * device); |
1431 |
/* tc58128.c */
|
1432 |
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
1433 |
|
1434 |
/* NOR flash devices */
|
1435 |
typedef struct pflash_t pflash_t; |
1436 |
|
1437 |
pflash_t *pflash_register (target_ulong base, ram_addr_t off, |
1438 |
BlockDriverState *bs, |
1439 |
target_ulong sector_len, int nb_blocs, int width, |
1440 |
uint16_t id0, uint16_t id1, |
1441 |
uint16_t id2, uint16_t id3); |
1442 |
|
1443 |
#include "gdbstub.h" |
1444 |
|
1445 |
#endif /* defined(QEMU_TOOL) */ |
1446 |
|
1447 |
/* monitor.c */
|
1448 |
void monitor_init(CharDriverState *hd, int show_banner); |
1449 |
void term_puts(const char *str); |
1450 |
void term_vprintf(const char *fmt, va_list ap); |
1451 |
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
1452 |
void term_print_filename(const char *filename); |
1453 |
void term_flush(void); |
1454 |
void term_print_help(void); |
1455 |
void monitor_readline(const char *prompt, int is_password, |
1456 |
char *buf, int buf_size); |
1457 |
|
1458 |
/* readline.c */
|
1459 |
typedef void ReadLineFunc(void *opaque, const char *str); |
1460 |
|
1461 |
extern int completion_index; |
1462 |
void add_completion(const char *str); |
1463 |
void readline_handle_byte(int ch); |
1464 |
void readline_find_completion(const char *cmdline); |
1465 |
const char *readline_get_history(unsigned int index); |
1466 |
void readline_start(const char *prompt, int is_password, |
1467 |
ReadLineFunc *readline_func, void *opaque);
|
1468 |
|
1469 |
void kqemu_record_dump(void); |
1470 |
|
1471 |
#endif /* VL_H */ |