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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
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3 | 7e7c5e4c | balrog | * Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
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4 | 7e7c5e4c | balrog | * Based on reverse-engineering of a linux driver.
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5 | 7e7c5e4c | balrog | *
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6 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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7 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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8 | 7e7c5e4c | balrog | *
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9 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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10 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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11 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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12 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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13 | 7e7c5e4c | balrog | *
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14 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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15 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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18 | 7e7c5e4c | balrog | *
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19 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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20 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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21 | 7e7c5e4c | balrog | */
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22 | 7e7c5e4c | balrog | |
23 | 7e7c5e4c | balrog | #include "qemu-common.h" |
24 | 7e7c5e4c | balrog | #include "irq.h" |
25 | 7e7c5e4c | balrog | #include "devices.h" |
26 | 7e7c5e4c | balrog | #include "sysemu.h" |
27 | 7e7c5e4c | balrog | |
28 | 7e7c5e4c | balrog | //#define DEBUG
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29 | 7e7c5e4c | balrog | |
30 | bc24a225 | Paul Brook | typedef struct { |
31 | bc24a225 | Paul Brook | void *opaque;
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32 | bc24a225 | Paul Brook | void (*io)(void *opaque, int rw, int reg, uint16_t *val); |
33 | bc24a225 | Paul Brook | int addr;
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34 | bc24a225 | Paul Brook | } CBusSlave; |
35 | bc24a225 | Paul Brook | |
36 | bc24a225 | Paul Brook | typedef struct { |
37 | bc24a225 | Paul Brook | CBus cbus; |
38 | 7e7c5e4c | balrog | |
39 | 7e7c5e4c | balrog | int sel;
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40 | 7e7c5e4c | balrog | int dat;
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41 | 7e7c5e4c | balrog | int clk;
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42 | 7e7c5e4c | balrog | int bit;
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43 | 7e7c5e4c | balrog | int dir;
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44 | 7e7c5e4c | balrog | uint16_t val; |
45 | 7e7c5e4c | balrog | qemu_irq dat_out; |
46 | 7e7c5e4c | balrog | |
47 | 7e7c5e4c | balrog | int addr;
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48 | 7e7c5e4c | balrog | int reg;
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49 | 7e7c5e4c | balrog | int rw;
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50 | 7e7c5e4c | balrog | enum {
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51 | 7e7c5e4c | balrog | cbus_address, |
52 | 7e7c5e4c | balrog | cbus_value, |
53 | 7e7c5e4c | balrog | } cycle; |
54 | 7e7c5e4c | balrog | |
55 | bc24a225 | Paul Brook | CBusSlave *slave[8];
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56 | bc24a225 | Paul Brook | } CBusPriv; |
57 | 7e7c5e4c | balrog | |
58 | bc24a225 | Paul Brook | static void cbus_io(CBusPriv *s) |
59 | 7e7c5e4c | balrog | { |
60 | 7e7c5e4c | balrog | if (s->slave[s->addr])
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61 | 7e7c5e4c | balrog | s->slave[s->addr]->io(s->slave[s->addr]->opaque, |
62 | 7e7c5e4c | balrog | s->rw, s->reg, &s->val); |
63 | 7e7c5e4c | balrog | else
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64 | 2ac71179 | Paul Brook | hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
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65 | 7e7c5e4c | balrog | } |
66 | 7e7c5e4c | balrog | |
67 | bc24a225 | Paul Brook | static void cbus_cycle(CBusPriv *s) |
68 | 7e7c5e4c | balrog | { |
69 | 7e7c5e4c | balrog | switch (s->cycle) {
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70 | 7e7c5e4c | balrog | case cbus_address:
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71 | 7e7c5e4c | balrog | s->addr = (s->val >> 6) & 7; |
72 | 7e7c5e4c | balrog | s->rw = (s->val >> 5) & 1; |
73 | 7e7c5e4c | balrog | s->reg = (s->val >> 0) & 0x1f; |
74 | 7e7c5e4c | balrog | |
75 | 7e7c5e4c | balrog | s->cycle = cbus_value; |
76 | 7e7c5e4c | balrog | s->bit = 15;
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77 | 7e7c5e4c | balrog | s->dir = !s->rw; |
78 | 7e7c5e4c | balrog | s->val = 0;
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79 | 7e7c5e4c | balrog | |
80 | 7e7c5e4c | balrog | if (s->rw)
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81 | 7e7c5e4c | balrog | cbus_io(s); |
82 | 7e7c5e4c | balrog | break;
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83 | 7e7c5e4c | balrog | |
84 | 7e7c5e4c | balrog | case cbus_value:
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85 | 7e7c5e4c | balrog | if (!s->rw)
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86 | 7e7c5e4c | balrog | cbus_io(s); |
87 | 7e7c5e4c | balrog | |
88 | 7e7c5e4c | balrog | s->cycle = cbus_address; |
89 | 7e7c5e4c | balrog | s->bit = 8;
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90 | 7e7c5e4c | balrog | s->dir = 1;
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91 | 7e7c5e4c | balrog | s->val = 0;
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92 | 7e7c5e4c | balrog | break;
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93 | 7e7c5e4c | balrog | } |
94 | 7e7c5e4c | balrog | } |
95 | 7e7c5e4c | balrog | |
96 | 7e7c5e4c | balrog | static void cbus_clk(void *opaque, int line, int level) |
97 | 7e7c5e4c | balrog | { |
98 | bc24a225 | Paul Brook | CBusPriv *s = (CBusPriv *) opaque; |
99 | 7e7c5e4c | balrog | |
100 | 7e7c5e4c | balrog | if (!s->sel && level && !s->clk) {
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101 | 7e7c5e4c | balrog | if (s->dir)
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102 | 7e7c5e4c | balrog | s->val |= s->dat << (s->bit --); |
103 | 7e7c5e4c | balrog | else
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104 | 7e7c5e4c | balrog | qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1);
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105 | 7e7c5e4c | balrog | |
106 | 7e7c5e4c | balrog | if (s->bit < 0) |
107 | 7e7c5e4c | balrog | cbus_cycle(s); |
108 | 7e7c5e4c | balrog | } |
109 | 7e7c5e4c | balrog | |
110 | 7e7c5e4c | balrog | s->clk = level; |
111 | 7e7c5e4c | balrog | } |
112 | 7e7c5e4c | balrog | |
113 | 7e7c5e4c | balrog | static void cbus_dat(void *opaque, int line, int level) |
114 | 7e7c5e4c | balrog | { |
115 | bc24a225 | Paul Brook | CBusPriv *s = (CBusPriv *) opaque; |
116 | 7e7c5e4c | balrog | |
117 | 7e7c5e4c | balrog | s->dat = level; |
118 | 7e7c5e4c | balrog | } |
119 | 7e7c5e4c | balrog | |
120 | 7e7c5e4c | balrog | static void cbus_sel(void *opaque, int line, int level) |
121 | 7e7c5e4c | balrog | { |
122 | bc24a225 | Paul Brook | CBusPriv *s = (CBusPriv *) opaque; |
123 | 7e7c5e4c | balrog | |
124 | 7e7c5e4c | balrog | if (!level) {
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125 | 7e7c5e4c | balrog | s->dir = 1;
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126 | 7e7c5e4c | balrog | s->bit = 8;
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127 | 7e7c5e4c | balrog | s->val = 0;
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128 | 7e7c5e4c | balrog | } |
129 | 7e7c5e4c | balrog | |
130 | 7e7c5e4c | balrog | s->sel = level; |
131 | 7e7c5e4c | balrog | } |
132 | 7e7c5e4c | balrog | |
133 | bc24a225 | Paul Brook | CBus *cbus_init(qemu_irq dat) |
134 | 7e7c5e4c | balrog | { |
135 | bc24a225 | Paul Brook | CBusPriv *s = (CBusPriv *) qemu_mallocz(sizeof(*s));
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136 | 7e7c5e4c | balrog | |
137 | 7e7c5e4c | balrog | s->dat_out = dat; |
138 | 7e7c5e4c | balrog | s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0]; |
139 | 7e7c5e4c | balrog | s->cbus.dat = qemu_allocate_irqs(cbus_dat, s, 1)[0]; |
140 | 7e7c5e4c | balrog | s->cbus.sel = qemu_allocate_irqs(cbus_sel, s, 1)[0]; |
141 | 7e7c5e4c | balrog | |
142 | 7e7c5e4c | balrog | s->sel = 1;
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143 | 7e7c5e4c | balrog | s->clk = 0;
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144 | 7e7c5e4c | balrog | s->dat = 0;
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145 | 7e7c5e4c | balrog | |
146 | 7e7c5e4c | balrog | return &s->cbus;
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147 | 7e7c5e4c | balrog | } |
148 | 7e7c5e4c | balrog | |
149 | bc24a225 | Paul Brook | void cbus_attach(CBus *bus, void *slave_opaque) |
150 | 7e7c5e4c | balrog | { |
151 | bc24a225 | Paul Brook | CBusSlave *slave = (CBusSlave *) slave_opaque; |
152 | bc24a225 | Paul Brook | CBusPriv *s = (CBusPriv *) bus; |
153 | 7e7c5e4c | balrog | |
154 | 7e7c5e4c | balrog | s->slave[slave->addr] = slave; |
155 | 7e7c5e4c | balrog | } |
156 | 7e7c5e4c | balrog | |
157 | 7e7c5e4c | balrog | /* Retu/Vilma */
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158 | bc24a225 | Paul Brook | typedef struct { |
159 | 7e7c5e4c | balrog | uint16_t irqst; |
160 | 7e7c5e4c | balrog | uint16_t irqen; |
161 | 7e7c5e4c | balrog | uint16_t cc[2];
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162 | 7e7c5e4c | balrog | int channel;
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163 | 7e7c5e4c | balrog | uint16_t result[16];
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164 | 7e7c5e4c | balrog | uint16_t sample; |
165 | 7e7c5e4c | balrog | uint16_t status; |
166 | 7e7c5e4c | balrog | |
167 | 7e7c5e4c | balrog | struct {
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168 | 7e7c5e4c | balrog | uint16_t cal; |
169 | 7e7c5e4c | balrog | } rtc; |
170 | 7e7c5e4c | balrog | |
171 | 7e7c5e4c | balrog | int is_vilma;
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172 | 7e7c5e4c | balrog | qemu_irq irq; |
173 | bc24a225 | Paul Brook | CBusSlave cbus; |
174 | bc24a225 | Paul Brook | } CBusRetu; |
175 | 7e7c5e4c | balrog | |
176 | bc24a225 | Paul Brook | static void retu_interrupt_update(CBusRetu *s) |
177 | 7e7c5e4c | balrog | { |
178 | 7e7c5e4c | balrog | qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
179 | 7e7c5e4c | balrog | } |
180 | 7e7c5e4c | balrog | |
181 | 7e7c5e4c | balrog | #define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
182 | 7e7c5e4c | balrog | #define RETU_REG_IDR 0x01 /* (T) Interrupt ID */ |
183 | 7e7c5e4c | balrog | #define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */ |
184 | 7e7c5e4c | balrog | #define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */ |
185 | 7e7c5e4c | balrog | #define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */ |
186 | 7e7c5e4c | balrog | #define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */ |
187 | 7e7c5e4c | balrog | #define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */ |
188 | 7e7c5e4c | balrog | #define RETU_REG_ADCR 0x08 /* (RW) ADC result register */ |
189 | 7e7c5e4c | balrog | #define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */ |
190 | 7e7c5e4c | balrog | #define RETU_REG_AFCR 0x0a /* (RW) AFC register */ |
191 | 7e7c5e4c | balrog | #define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */ |
192 | 7e7c5e4c | balrog | #define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/ |
193 | 7e7c5e4c | balrog | #define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */ |
194 | 7e7c5e4c | balrog | #define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */ |
195 | 7e7c5e4c | balrog | #define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */ |
196 | 7e7c5e4c | balrog | #define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */ |
197 | 7e7c5e4c | balrog | #define RETU_REG_TXCR 0x11 /* (RW) TxC register */ |
198 | 7e7c5e4c | balrog | #define RETU_REG_STATUS 0x16 /* (RO) Status register */ |
199 | 7e7c5e4c | balrog | #define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */ |
200 | 7e7c5e4c | balrog | #define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */ |
201 | 7e7c5e4c | balrog | #define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */ |
202 | 7e7c5e4c | balrog | #define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */ |
203 | 7e7c5e4c | balrog | #define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */ |
204 | 7e7c5e4c | balrog | #define RETU_REG_SGR1 0x1c /* (RW) */ |
205 | 7e7c5e4c | balrog | #define RETU_REG_SCR1 0x1d /* (RW) */ |
206 | 7e7c5e4c | balrog | #define RETU_REG_SGR2 0x1e /* (RW) */ |
207 | 7e7c5e4c | balrog | #define RETU_REG_SCR2 0x1f /* (RW) */ |
208 | 7e7c5e4c | balrog | |
209 | 7e7c5e4c | balrog | /* Retu Interrupt sources */
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210 | 7e7c5e4c | balrog | enum {
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211 | 7e7c5e4c | balrog | retu_int_pwr = 0, /* Power button */ |
212 | 7e7c5e4c | balrog | retu_int_char = 1, /* Charger */ |
213 | 7e7c5e4c | balrog | retu_int_rtcs = 2, /* Seconds */ |
214 | 7e7c5e4c | balrog | retu_int_rtcm = 3, /* Minutes */ |
215 | 7e7c5e4c | balrog | retu_int_rtcd = 4, /* Days */ |
216 | 7e7c5e4c | balrog | retu_int_rtca = 5, /* Alarm */ |
217 | 7e7c5e4c | balrog | retu_int_hook = 6, /* Hook */ |
218 | 7e7c5e4c | balrog | retu_int_head = 7, /* Headset */ |
219 | 7e7c5e4c | balrog | retu_int_adcs = 8, /* ADC sample */ |
220 | 7e7c5e4c | balrog | }; |
221 | 7e7c5e4c | balrog | |
222 | 7e7c5e4c | balrog | /* Retu ADC channel wiring */
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223 | 7e7c5e4c | balrog | enum {
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224 | 7e7c5e4c | balrog | retu_adc_bsi = 1, /* BSI */ |
225 | 7e7c5e4c | balrog | retu_adc_batt_temp = 2, /* Battery temperature */ |
226 | 7e7c5e4c | balrog | retu_adc_chg_volt = 3, /* Charger voltage */ |
227 | 7e7c5e4c | balrog | retu_adc_head_det = 4, /* Headset detection */ |
228 | 7e7c5e4c | balrog | retu_adc_hook_det = 5, /* Hook detection */ |
229 | 7e7c5e4c | balrog | retu_adc_rf_gp = 6, /* RF GP */ |
230 | 7e7c5e4c | balrog | retu_adc_tx_det = 7, /* Wideband Tx detection */ |
231 | 7e7c5e4c | balrog | retu_adc_batt_volt = 8, /* Battery voltage */ |
232 | 7e7c5e4c | balrog | retu_adc_sens = 10, /* Light sensor */ |
233 | 7e7c5e4c | balrog | retu_adc_sens_temp = 11, /* Light sensor temperature */ |
234 | 7e7c5e4c | balrog | retu_adc_bbatt_volt = 12, /* Backup battery voltage */ |
235 | 7e7c5e4c | balrog | retu_adc_self_temp = 13, /* RETU temperature */ |
236 | 7e7c5e4c | balrog | }; |
237 | 7e7c5e4c | balrog | |
238 | bc24a225 | Paul Brook | static inline uint16_t retu_read(CBusRetu *s, int reg) |
239 | 7e7c5e4c | balrog | { |
240 | 7e7c5e4c | balrog | #ifdef DEBUG
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241 | 7e7c5e4c | balrog | printf("RETU read at %02x\n", reg);
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242 | 7e7c5e4c | balrog | #endif
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243 | 7e7c5e4c | balrog | |
244 | 7e7c5e4c | balrog | switch (reg) {
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245 | 7e7c5e4c | balrog | case RETU_REG_ASICR:
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246 | 7e7c5e4c | balrog | return 0x0215 | (s->is_vilma << 7); |
247 | 7e7c5e4c | balrog | |
248 | 7e7c5e4c | balrog | case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */ |
249 | 7e7c5e4c | balrog | return s->irqst;
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250 | 7e7c5e4c | balrog | |
251 | 7e7c5e4c | balrog | case RETU_REG_IMR:
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252 | 7e7c5e4c | balrog | return s->irqen;
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253 | 7e7c5e4c | balrog | |
254 | 7e7c5e4c | balrog | case RETU_REG_RTCDSR:
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255 | 7e7c5e4c | balrog | case RETU_REG_RTCHMR:
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256 | 7e7c5e4c | balrog | case RETU_REG_RTCHMAR:
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257 | 7e7c5e4c | balrog | /* TODO */
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258 | 7e7c5e4c | balrog | return 0x0000; |
259 | 7e7c5e4c | balrog | |
260 | 7e7c5e4c | balrog | case RETU_REG_RTCCALR:
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261 | 7e7c5e4c | balrog | return s->rtc.cal;
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262 | 7e7c5e4c | balrog | |
263 | 7e7c5e4c | balrog | case RETU_REG_ADCR:
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264 | 7e7c5e4c | balrog | return (s->channel << 10) | s->result[s->channel]; |
265 | 7e7c5e4c | balrog | case RETU_REG_ADCSCR:
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266 | 7e7c5e4c | balrog | return s->sample;
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267 | 7e7c5e4c | balrog | |
268 | 7e7c5e4c | balrog | case RETU_REG_AFCR:
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269 | 7e7c5e4c | balrog | case RETU_REG_ANTIFR:
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270 | 7e7c5e4c | balrog | case RETU_REG_CALIBR:
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271 | 7e7c5e4c | balrog | /* TODO */
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272 | 7e7c5e4c | balrog | return 0x0000; |
273 | 7e7c5e4c | balrog | |
274 | 7e7c5e4c | balrog | case RETU_REG_CCR1:
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275 | 7e7c5e4c | balrog | return s->cc[0]; |
276 | 7e7c5e4c | balrog | case RETU_REG_CCR2:
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277 | 7e7c5e4c | balrog | return s->cc[1]; |
278 | 7e7c5e4c | balrog | |
279 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_CLR:
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280 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_SET:
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281 | 7e7c5e4c | balrog | case RETU_REG_TXCR:
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282 | 7e7c5e4c | balrog | /* TODO */
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283 | 7e7c5e4c | balrog | return 0x0000; |
284 | 7e7c5e4c | balrog | |
285 | 7e7c5e4c | balrog | case RETU_REG_STATUS:
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286 | 7e7c5e4c | balrog | return s->status;
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287 | 7e7c5e4c | balrog | |
288 | 7e7c5e4c | balrog | case RETU_REG_WATCHDOG:
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289 | 7e7c5e4c | balrog | case RETU_REG_AUDTXR:
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290 | 7e7c5e4c | balrog | case RETU_REG_AUDPAR:
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291 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR1:
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292 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR2:
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293 | 7e7c5e4c | balrog | case RETU_REG_SGR1:
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294 | 7e7c5e4c | balrog | case RETU_REG_SCR1:
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295 | 7e7c5e4c | balrog | case RETU_REG_SGR2:
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296 | 7e7c5e4c | balrog | case RETU_REG_SCR2:
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297 | 7e7c5e4c | balrog | /* TODO */
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298 | 7e7c5e4c | balrog | return 0x0000; |
299 | 7e7c5e4c | balrog | |
300 | 7e7c5e4c | balrog | default:
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301 | 2ac71179 | Paul Brook | hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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302 | 7e7c5e4c | balrog | } |
303 | 7e7c5e4c | balrog | } |
304 | 7e7c5e4c | balrog | |
305 | bc24a225 | Paul Brook | static inline void retu_write(CBusRetu *s, int reg, uint16_t val) |
306 | 7e7c5e4c | balrog | { |
307 | 7e7c5e4c | balrog | #ifdef DEBUG
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308 | 7e7c5e4c | balrog | printf("RETU write of %04x at %02x\n", val, reg);
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309 | 7e7c5e4c | balrog | #endif
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310 | 7e7c5e4c | balrog | |
311 | 7e7c5e4c | balrog | switch (reg) {
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312 | 7e7c5e4c | balrog | case RETU_REG_IDR:
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313 | 7e7c5e4c | balrog | s->irqst ^= val; |
314 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
315 | 7e7c5e4c | balrog | break;
|
316 | 7e7c5e4c | balrog | |
317 | 7e7c5e4c | balrog | case RETU_REG_IMR:
|
318 | 7e7c5e4c | balrog | s->irqen = val; |
319 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
320 | 7e7c5e4c | balrog | break;
|
321 | 7e7c5e4c | balrog | |
322 | 7e7c5e4c | balrog | case RETU_REG_RTCDSR:
|
323 | 7e7c5e4c | balrog | case RETU_REG_RTCHMAR:
|
324 | 7e7c5e4c | balrog | /* TODO */
|
325 | 7e7c5e4c | balrog | break;
|
326 | 7e7c5e4c | balrog | |
327 | 7e7c5e4c | balrog | case RETU_REG_RTCCALR:
|
328 | 7e7c5e4c | balrog | s->rtc.cal = val; |
329 | 7e7c5e4c | balrog | break;
|
330 | 7e7c5e4c | balrog | |
331 | 7e7c5e4c | balrog | case RETU_REG_ADCR:
|
332 | 7e7c5e4c | balrog | s->channel = (val >> 10) & 0xf; |
333 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_adcs;
|
334 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
335 | 7e7c5e4c | balrog | break;
|
336 | 7e7c5e4c | balrog | case RETU_REG_ADCSCR:
|
337 | 7e7c5e4c | balrog | s->sample &= ~val; |
338 | 7e7c5e4c | balrog | break;
|
339 | 7e7c5e4c | balrog | |
340 | 7e7c5e4c | balrog | case RETU_REG_AFCR:
|
341 | 7e7c5e4c | balrog | case RETU_REG_ANTIFR:
|
342 | 7e7c5e4c | balrog | case RETU_REG_CALIBR:
|
343 | 7e7c5e4c | balrog | |
344 | 7e7c5e4c | balrog | case RETU_REG_CCR1:
|
345 | 7e7c5e4c | balrog | s->cc[0] = val;
|
346 | 7e7c5e4c | balrog | break;
|
347 | 7e7c5e4c | balrog | case RETU_REG_CCR2:
|
348 | 7e7c5e4c | balrog | s->cc[1] = val;
|
349 | 7e7c5e4c | balrog | break;
|
350 | 7e7c5e4c | balrog | |
351 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_CLR:
|
352 | 7e7c5e4c | balrog | case RETU_REG_RCTRL_SET:
|
353 | 7e7c5e4c | balrog | /* TODO */
|
354 | 7e7c5e4c | balrog | break;
|
355 | 7e7c5e4c | balrog | |
356 | 7e7c5e4c | balrog | case RETU_REG_WATCHDOG:
|
357 | 7e7c5e4c | balrog | if (val == 0 && (s->cc[0] & 2)) |
358 | 7e7c5e4c | balrog | qemu_system_shutdown_request(); |
359 | 7e7c5e4c | balrog | break;
|
360 | 7e7c5e4c | balrog | |
361 | 7e7c5e4c | balrog | case RETU_REG_TXCR:
|
362 | 7e7c5e4c | balrog | case RETU_REG_AUDTXR:
|
363 | 7e7c5e4c | balrog | case RETU_REG_AUDPAR:
|
364 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR1:
|
365 | 7e7c5e4c | balrog | case RETU_REG_AUDRXR2:
|
366 | 7e7c5e4c | balrog | case RETU_REG_SGR1:
|
367 | 7e7c5e4c | balrog | case RETU_REG_SCR1:
|
368 | 7e7c5e4c | balrog | case RETU_REG_SGR2:
|
369 | 7e7c5e4c | balrog | case RETU_REG_SCR2:
|
370 | 7e7c5e4c | balrog | /* TODO */
|
371 | 7e7c5e4c | balrog | break;
|
372 | 7e7c5e4c | balrog | |
373 | 7e7c5e4c | balrog | default:
|
374 | 2ac71179 | Paul Brook | hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
|
375 | 7e7c5e4c | balrog | } |
376 | 7e7c5e4c | balrog | } |
377 | 7e7c5e4c | balrog | |
378 | 7e7c5e4c | balrog | static void retu_io(void *opaque, int rw, int reg, uint16_t *val) |
379 | 7e7c5e4c | balrog | { |
380 | bc24a225 | Paul Brook | CBusRetu *s = (CBusRetu *) opaque; |
381 | 7e7c5e4c | balrog | |
382 | 7e7c5e4c | balrog | if (rw)
|
383 | 7e7c5e4c | balrog | *val = retu_read(s, reg); |
384 | 7e7c5e4c | balrog | else
|
385 | 7e7c5e4c | balrog | retu_write(s, reg, *val); |
386 | 7e7c5e4c | balrog | } |
387 | 7e7c5e4c | balrog | |
388 | 7e7c5e4c | balrog | void *retu_init(qemu_irq irq, int vilma) |
389 | 7e7c5e4c | balrog | { |
390 | bc24a225 | Paul Brook | CBusRetu *s = (CBusRetu *) qemu_mallocz(sizeof(*s));
|
391 | 7e7c5e4c | balrog | |
392 | 7e7c5e4c | balrog | s->irq = irq; |
393 | 7e7c5e4c | balrog | s->irqen = 0xffff;
|
394 | 7e7c5e4c | balrog | s->irqst = 0x0000;
|
395 | 7e7c5e4c | balrog | s->status = 0x0020;
|
396 | 7e7c5e4c | balrog | s->is_vilma = !!vilma; |
397 | 7e7c5e4c | balrog | s->rtc.cal = 0x01;
|
398 | 7e7c5e4c | balrog | s->result[retu_adc_bsi] = 0x3c2;
|
399 | 7e7c5e4c | balrog | s->result[retu_adc_batt_temp] = 0x0fc;
|
400 | 7e7c5e4c | balrog | s->result[retu_adc_chg_volt] = 0x165;
|
401 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 123;
|
402 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 1023;
|
403 | 7e7c5e4c | balrog | s->result[retu_adc_rf_gp] = 0x11;
|
404 | 7e7c5e4c | balrog | s->result[retu_adc_tx_det] = 0x11;
|
405 | 7e7c5e4c | balrog | s->result[retu_adc_batt_volt] = 0x250;
|
406 | 7e7c5e4c | balrog | s->result[retu_adc_sens] = 2;
|
407 | 7e7c5e4c | balrog | s->result[retu_adc_sens_temp] = 0x11;
|
408 | 7e7c5e4c | balrog | s->result[retu_adc_bbatt_volt] = 0x3d0;
|
409 | 7e7c5e4c | balrog | s->result[retu_adc_self_temp] = 0x330;
|
410 | 7e7c5e4c | balrog | |
411 | 7e7c5e4c | balrog | s->cbus.opaque = s; |
412 | 7e7c5e4c | balrog | s->cbus.io = retu_io; |
413 | 7e7c5e4c | balrog | s->cbus.addr = 1;
|
414 | 7e7c5e4c | balrog | |
415 | 7e7c5e4c | balrog | return &s->cbus;
|
416 | 7e7c5e4c | balrog | } |
417 | 7e7c5e4c | balrog | |
418 | 7e7c5e4c | balrog | void retu_key_event(void *retu, int state) |
419 | 7e7c5e4c | balrog | { |
420 | bc24a225 | Paul Brook | CBusSlave *slave = (CBusSlave *) retu; |
421 | bc24a225 | Paul Brook | CBusRetu *s = (CBusRetu *) slave->opaque; |
422 | 7e7c5e4c | balrog | |
423 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_pwr;
|
424 | 7e7c5e4c | balrog | retu_interrupt_update(s); |
425 | 7e7c5e4c | balrog | |
426 | 7e7c5e4c | balrog | if (state)
|
427 | 7e7c5e4c | balrog | s->status &= ~(1 << 5); |
428 | 7e7c5e4c | balrog | else
|
429 | 7e7c5e4c | balrog | s->status |= 1 << 5; |
430 | 7e7c5e4c | balrog | } |
431 | 7e7c5e4c | balrog | |
432 | b1d8e52e | blueswir1 | #if 0
|
433 | b1d8e52e | blueswir1 | static void retu_head_event(void *retu, int state)
|
434 | 7e7c5e4c | balrog | {
|
435 | bc24a225 | Paul Brook | CBusSlave *slave = (CBusSlave *) retu;
|
436 | bc24a225 | Paul Brook | CBusRetu *s = (CBusRetu *) slave->opaque;
|
437 | 7e7c5e4c | balrog | |
438 | 7e7c5e4c | balrog | if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
|
439 | 7e7c5e4c | balrog | /* TODO: reissue the interrupt every 100ms or so. */
|
440 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_head;
|
441 | 7e7c5e4c | balrog | retu_interrupt_update(s);
|
442 | 7e7c5e4c | balrog | }
|
443 | 7e7c5e4c | balrog | |
444 | 7e7c5e4c | balrog | if (state)
|
445 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 50;
|
446 | 7e7c5e4c | balrog | else
|
447 | 7e7c5e4c | balrog | s->result[retu_adc_head_det] = 123;
|
448 | 7e7c5e4c | balrog | }
|
449 | 7e7c5e4c | balrog | |
450 | b1d8e52e | blueswir1 | static void retu_hook_event(void *retu, int state)
|
451 | 7e7c5e4c | balrog | {
|
452 | bc24a225 | Paul Brook | CBusSlave *slave = (CBusSlave *) retu;
|
453 | bc24a225 | Paul Brook | CBusRetu *s = (CBusRetu *) slave->opaque;
|
454 | 7e7c5e4c | balrog | |
455 | 7e7c5e4c | balrog | if ((s->cc[0] & 0x500) == 0x500) {
|
456 | 7e7c5e4c | balrog | /* TODO: reissue the interrupt every 100ms or so. */
|
457 | 7e7c5e4c | balrog | s->irqst |= 1 << retu_int_hook;
|
458 | 7e7c5e4c | balrog | retu_interrupt_update(s);
|
459 | 7e7c5e4c | balrog | }
|
460 | 7e7c5e4c | balrog | |
461 | 7e7c5e4c | balrog | if (state)
|
462 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 50;
|
463 | 7e7c5e4c | balrog | else
|
464 | 7e7c5e4c | balrog | s->result[retu_adc_hook_det] = 123;
|
465 | 7e7c5e4c | balrog | }
|
466 | b1d8e52e | blueswir1 | #endif
|
467 | 7e7c5e4c | balrog | |
468 | 7e7c5e4c | balrog | /* Tahvo/Betty */
|
469 | bc24a225 | Paul Brook | typedef struct { |
470 | 7e7c5e4c | balrog | uint16_t irqst; |
471 | 7e7c5e4c | balrog | uint16_t irqen; |
472 | 7e7c5e4c | balrog | uint8_t charger; |
473 | 7e7c5e4c | balrog | uint8_t backlight; |
474 | 7e7c5e4c | balrog | uint16_t usbr; |
475 | 7e7c5e4c | balrog | uint16_t power; |
476 | 7e7c5e4c | balrog | |
477 | 7e7c5e4c | balrog | int is_betty;
|
478 | 7e7c5e4c | balrog | qemu_irq irq; |
479 | bc24a225 | Paul Brook | CBusSlave cbus; |
480 | bc24a225 | Paul Brook | } CBusTahvo; |
481 | 7e7c5e4c | balrog | |
482 | bc24a225 | Paul Brook | static void tahvo_interrupt_update(CBusTahvo *s) |
483 | 7e7c5e4c | balrog | { |
484 | 7e7c5e4c | balrog | qemu_set_irq(s->irq, s->irqst & ~s->irqen); |
485 | 7e7c5e4c | balrog | } |
486 | 7e7c5e4c | balrog | |
487 | 7e7c5e4c | balrog | #define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */ |
488 | 7e7c5e4c | balrog | #define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */ |
489 | 7e7c5e4c | balrog | #define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */ |
490 | 7e7c5e4c | balrog | #define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */ |
491 | 7e7c5e4c | balrog | #define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */ |
492 | 7e7c5e4c | balrog | #define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */ |
493 | 7e7c5e4c | balrog | #define TAHVO_REG_USBR 0x06 /* (RW) USB control */ |
494 | 7e7c5e4c | balrog | #define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */ |
495 | 7e7c5e4c | balrog | #define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */ |
496 | 7e7c5e4c | balrog | #define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */ |
497 | 7e7c5e4c | balrog | #define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */ |
498 | 7e7c5e4c | balrog | #define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */ |
499 | 7e7c5e4c | balrog | #define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */ |
500 | 7e7c5e4c | balrog | #define TAHVO_REG_FRR 0x0d /* (RO) FR */ |
501 | 7e7c5e4c | balrog | |
502 | bc24a225 | Paul Brook | static inline uint16_t tahvo_read(CBusTahvo *s, int reg) |
503 | 7e7c5e4c | balrog | { |
504 | 7e7c5e4c | balrog | #ifdef DEBUG
|
505 | 7e7c5e4c | balrog | printf("TAHVO read at %02x\n", reg);
|
506 | 7e7c5e4c | balrog | #endif
|
507 | 7e7c5e4c | balrog | |
508 | 7e7c5e4c | balrog | switch (reg) {
|
509 | 7e7c5e4c | balrog | case TAHVO_REG_ASICR:
|
510 | 7e7c5e4c | balrog | return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */ |
511 | 7e7c5e4c | balrog | |
512 | 7e7c5e4c | balrog | case TAHVO_REG_IDR:
|
513 | 7e7c5e4c | balrog | case TAHVO_REG_IDSR: /* XXX: what does this do? */ |
514 | 7e7c5e4c | balrog | return s->irqst;
|
515 | 7e7c5e4c | balrog | |
516 | 7e7c5e4c | balrog | case TAHVO_REG_IMR:
|
517 | 7e7c5e4c | balrog | return s->irqen;
|
518 | 7e7c5e4c | balrog | |
519 | 7e7c5e4c | balrog | case TAHVO_REG_CHAPWMR:
|
520 | 7e7c5e4c | balrog | return s->charger;
|
521 | 7e7c5e4c | balrog | |
522 | 7e7c5e4c | balrog | case TAHVO_REG_LEDPWMR:
|
523 | 7e7c5e4c | balrog | return s->backlight;
|
524 | 7e7c5e4c | balrog | |
525 | 7e7c5e4c | balrog | case TAHVO_REG_USBR:
|
526 | 7e7c5e4c | balrog | return s->usbr;
|
527 | 7e7c5e4c | balrog | |
528 | 7e7c5e4c | balrog | case TAHVO_REG_RCR:
|
529 | 7e7c5e4c | balrog | return s->power;
|
530 | 7e7c5e4c | balrog | |
531 | 7e7c5e4c | balrog | case TAHVO_REG_CCR1:
|
532 | 7e7c5e4c | balrog | case TAHVO_REG_CCR2:
|
533 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR1:
|
534 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR2:
|
535 | 7e7c5e4c | balrog | case TAHVO_REG_NOPR:
|
536 | 7e7c5e4c | balrog | case TAHVO_REG_FRR:
|
537 | 7e7c5e4c | balrog | return 0x0000; |
538 | 7e7c5e4c | balrog | |
539 | 7e7c5e4c | balrog | default:
|
540 | 2ac71179 | Paul Brook | hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
|
541 | 7e7c5e4c | balrog | } |
542 | 7e7c5e4c | balrog | } |
543 | 7e7c5e4c | balrog | |
544 | bc24a225 | Paul Brook | static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val) |
545 | 7e7c5e4c | balrog | { |
546 | 7e7c5e4c | balrog | #ifdef DEBUG
|
547 | 7e7c5e4c | balrog | printf("TAHVO write of %04x at %02x\n", val, reg);
|
548 | 7e7c5e4c | balrog | #endif
|
549 | 7e7c5e4c | balrog | |
550 | 7e7c5e4c | balrog | switch (reg) {
|
551 | 7e7c5e4c | balrog | case TAHVO_REG_IDR:
|
552 | 7e7c5e4c | balrog | s->irqst ^= val; |
553 | 7e7c5e4c | balrog | tahvo_interrupt_update(s); |
554 | 7e7c5e4c | balrog | break;
|
555 | 7e7c5e4c | balrog | |
556 | 7e7c5e4c | balrog | case TAHVO_REG_IMR:
|
557 | 7e7c5e4c | balrog | s->irqen = val; |
558 | 7e7c5e4c | balrog | tahvo_interrupt_update(s); |
559 | 7e7c5e4c | balrog | break;
|
560 | 7e7c5e4c | balrog | |
561 | 7e7c5e4c | balrog | case TAHVO_REG_CHAPWMR:
|
562 | 7e7c5e4c | balrog | s->charger = val; |
563 | 7e7c5e4c | balrog | break;
|
564 | 7e7c5e4c | balrog | |
565 | 7e7c5e4c | balrog | case TAHVO_REG_LEDPWMR:
|
566 | 7e7c5e4c | balrog | if (s->backlight != (val & 0x7f)) { |
567 | 7e7c5e4c | balrog | s->backlight = val & 0x7f;
|
568 | 7e7c5e4c | balrog | printf("%s: LCD backlight now at %i / 127\n",
|
569 | 7e7c5e4c | balrog | __FUNCTION__, s->backlight); |
570 | 7e7c5e4c | balrog | } |
571 | 7e7c5e4c | balrog | break;
|
572 | 7e7c5e4c | balrog | |
573 | 7e7c5e4c | balrog | case TAHVO_REG_USBR:
|
574 | 7e7c5e4c | balrog | s->usbr = val; |
575 | 7e7c5e4c | balrog | break;
|
576 | 7e7c5e4c | balrog | |
577 | 7e7c5e4c | balrog | case TAHVO_REG_RCR:
|
578 | 7e7c5e4c | balrog | s->power = val; |
579 | 7e7c5e4c | balrog | break;
|
580 | 7e7c5e4c | balrog | |
581 | 7e7c5e4c | balrog | case TAHVO_REG_CCR1:
|
582 | 7e7c5e4c | balrog | case TAHVO_REG_CCR2:
|
583 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR1:
|
584 | 7e7c5e4c | balrog | case TAHVO_REG_TESTR2:
|
585 | 7e7c5e4c | balrog | case TAHVO_REG_NOPR:
|
586 | 7e7c5e4c | balrog | case TAHVO_REG_FRR:
|
587 | 7e7c5e4c | balrog | break;
|
588 | 7e7c5e4c | balrog | |
589 | 7e7c5e4c | balrog | default:
|
590 | 2ac71179 | Paul Brook | hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
|
591 | 7e7c5e4c | balrog | } |
592 | 7e7c5e4c | balrog | } |
593 | 7e7c5e4c | balrog | |
594 | 7e7c5e4c | balrog | static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val) |
595 | 7e7c5e4c | balrog | { |
596 | bc24a225 | Paul Brook | CBusTahvo *s = (CBusTahvo *) opaque; |
597 | 7e7c5e4c | balrog | |
598 | 7e7c5e4c | balrog | if (rw)
|
599 | 7e7c5e4c | balrog | *val = tahvo_read(s, reg); |
600 | 7e7c5e4c | balrog | else
|
601 | 7e7c5e4c | balrog | tahvo_write(s, reg, *val); |
602 | 7e7c5e4c | balrog | } |
603 | 7e7c5e4c | balrog | |
604 | 7e7c5e4c | balrog | void *tahvo_init(qemu_irq irq, int betty) |
605 | 7e7c5e4c | balrog | { |
606 | bc24a225 | Paul Brook | CBusTahvo *s = (CBusTahvo *) qemu_mallocz(sizeof(*s));
|
607 | 7e7c5e4c | balrog | |
608 | 7e7c5e4c | balrog | s->irq = irq; |
609 | 7e7c5e4c | balrog | s->irqen = 0xffff;
|
610 | 7e7c5e4c | balrog | s->irqst = 0x0000;
|
611 | 7e7c5e4c | balrog | s->is_betty = !!betty; |
612 | 7e7c5e4c | balrog | |
613 | 7e7c5e4c | balrog | s->cbus.opaque = s; |
614 | 7e7c5e4c | balrog | s->cbus.io = tahvo_io; |
615 | 7e7c5e4c | balrog | s->cbus.addr = 2;
|
616 | 7e7c5e4c | balrog | |
617 | 7e7c5e4c | balrog | return &s->cbus;
|
618 | 7e7c5e4c | balrog | } |