root / hw / gpio / puv3_gpio.c @ bf0da4df
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/*
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* GPIO device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/hw.h" |
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#include "hw/sysbus.h" |
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h" |
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#define TYPE_PUV3_GPIO "puv3_gpio" |
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#define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
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typedef struct PUV3GPIOState { |
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SysBusDevice parent_obj; |
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MemoryRegion iomem; |
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qemu_irq irq[9];
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uint32_t reg_GPLR; |
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uint32_t reg_GPDR; |
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uint32_t reg_GPIR; |
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} PUV3GPIOState; |
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static uint64_t puv3_gpio_read(void *opaque, hwaddr offset, |
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unsigned size)
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{ |
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PUV3GPIOState *s = opaque; |
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uint32_t ret = 0;
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switch (offset) {
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case 0x00: |
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ret = s->reg_GPLR; |
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break;
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case 0x04: |
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ret = s->reg_GPDR; |
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break;
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case 0x20: |
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ret = s->reg_GPIR; |
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break;
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default:
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DPRINTF("Bad offset 0x%x\n", offset);
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} |
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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} |
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static void puv3_gpio_write(void *opaque, hwaddr offset, |
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uint64_t value, unsigned size)
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{ |
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PUV3GPIOState *s = opaque; |
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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switch (offset) {
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case 0x04: |
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s->reg_GPDR = value; |
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break;
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case 0x08: |
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if (s->reg_GPDR & value) {
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s->reg_GPLR |= value; |
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} else {
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DPRINTF("Write gpio input port error!");
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} |
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break;
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case 0x0c: |
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if (s->reg_GPDR & value) {
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s->reg_GPLR &= ~value; |
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} else {
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DPRINTF("Write gpio input port error!");
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} |
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break;
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case 0x10: /* GRER */ |
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case 0x14: /* GFER */ |
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case 0x18: /* GEDR */ |
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break;
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case 0x20: /* GPIR */ |
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s->reg_GPIR = value; |
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break;
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default:
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DPRINTF("Bad offset 0x%x\n", offset);
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} |
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} |
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static const MemoryRegionOps puv3_gpio_ops = { |
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.read = puv3_gpio_read, |
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.write = puv3_gpio_write, |
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.impl = { |
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.min_access_size = 4,
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.max_access_size = 4,
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static int puv3_gpio_init(SysBusDevice *dev) |
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{ |
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PUV3GPIOState *s = PUV3_GPIO(dev); |
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s->reg_GPLR = 0;
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s->reg_GPDR = 0;
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/* FIXME: these irqs not handled yet */
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]); |
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sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]); |
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memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
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PUV3_REGS_OFFSET); |
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sysbus_init_mmio(dev, &s->iomem); |
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return 0; |
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} |
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static void puv3_gpio_class_init(ObjectClass *klass, void *data) |
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{ |
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
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sdc->init = puv3_gpio_init; |
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} |
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static const TypeInfo puv3_gpio_info = { |
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.name = TYPE_PUV3_GPIO, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(PUV3GPIOState),
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.class_init = puv3_gpio_class_init, |
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}; |
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static void puv3_gpio_register_type(void) |
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{ |
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type_register_static(&puv3_gpio_info); |
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} |
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type_init(puv3_gpio_register_type) |