root / hw / openrisc_pic.c @ bf3bc4c4
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1 | dd29c7fb | Jia Liu | /*
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2 | dd29c7fb | Jia Liu | * OpenRISC Programmable Interrupt Controller support.
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3 | dd29c7fb | Jia Liu | *
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4 | dd29c7fb | Jia Liu | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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5 | dd29c7fb | Jia Liu | * Feng Gao <gf91597@gmail.com>
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6 | dd29c7fb | Jia Liu | *
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7 | dd29c7fb | Jia Liu | * This library is free software; you can redistribute it and/or
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8 | dd29c7fb | Jia Liu | * modify it under the terms of the GNU Lesser General Public
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9 | dd29c7fb | Jia Liu | * License as published by the Free Software Foundation; either
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10 | dd29c7fb | Jia Liu | * version 2 of the License, or (at your option) any later version.
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11 | dd29c7fb | Jia Liu | *
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12 | dd29c7fb | Jia Liu | * This library is distributed in the hope that it will be useful,
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13 | dd29c7fb | Jia Liu | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | dd29c7fb | Jia Liu | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | dd29c7fb | Jia Liu | * Lesser General Public License for more details.
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16 | dd29c7fb | Jia Liu | *
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17 | dd29c7fb | Jia Liu | * You should have received a copy of the GNU Lesser General Public
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18 | dd29c7fb | Jia Liu | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | dd29c7fb | Jia Liu | */
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20 | dd29c7fb | Jia Liu | |
21 | dd29c7fb | Jia Liu | #include "hw.h" |
22 | dd29c7fb | Jia Liu | #include "cpu.h" |
23 | dd29c7fb | Jia Liu | |
24 | dd29c7fb | Jia Liu | /* OpenRISC pic handler */
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25 | dd29c7fb | Jia Liu | static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) |
26 | dd29c7fb | Jia Liu | { |
27 | dd29c7fb | Jia Liu | OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; |
28 | dd29c7fb | Jia Liu | int i;
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29 | dd29c7fb | Jia Liu | uint32_t irq_bit = 1 << irq;
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30 | dd29c7fb | Jia Liu | |
31 | dd29c7fb | Jia Liu | if (irq > 31 || irq < 0) { |
32 | dd29c7fb | Jia Liu | return;
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33 | dd29c7fb | Jia Liu | } |
34 | dd29c7fb | Jia Liu | |
35 | dd29c7fb | Jia Liu | if (level) {
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36 | dd29c7fb | Jia Liu | cpu->env.picsr |= irq_bit; |
37 | dd29c7fb | Jia Liu | } else {
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38 | dd29c7fb | Jia Liu | cpu->env.picsr &= ~irq_bit; |
39 | dd29c7fb | Jia Liu | } |
40 | dd29c7fb | Jia Liu | |
41 | dd29c7fb | Jia Liu | for (i = 0; i < 32; i++) { |
42 | dd29c7fb | Jia Liu | if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) { |
43 | dd29c7fb | Jia Liu | cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD); |
44 | dd29c7fb | Jia Liu | } else {
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45 | dd29c7fb | Jia Liu | cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD); |
46 | dd29c7fb | Jia Liu | cpu->env.picsr &= ~(1 << i);
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47 | dd29c7fb | Jia Liu | } |
48 | dd29c7fb | Jia Liu | } |
49 | dd29c7fb | Jia Liu | } |
50 | dd29c7fb | Jia Liu | |
51 | dd29c7fb | Jia Liu | void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
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52 | dd29c7fb | Jia Liu | { |
53 | dd29c7fb | Jia Liu | int i;
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54 | dd29c7fb | Jia Liu | qemu_irq *qi; |
55 | dd29c7fb | Jia Liu | qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS); |
56 | dd29c7fb | Jia Liu | |
57 | dd29c7fb | Jia Liu | for (i = 0; i < NR_IRQS; i++) { |
58 | dd29c7fb | Jia Liu | cpu->env.irq[i] = qi[i]; |
59 | dd29c7fb | Jia Liu | } |
60 | dd29c7fb | Jia Liu | } |