Revision bf4120ad
| b/target-mips/translate.c | ||
|---|---|---|
| 354 | 354 |
/* Coprocessor 1 (rs field) */ |
| 355 | 355 |
#define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) |
| 356 | 356 |
|
| 357 |
/* Values for the fmt field in FP instructions */ |
|
| 358 |
enum {
|
|
| 359 |
/* 0 - 15 are reserved */ |
|
| 360 |
FMT_S = 16, |
|
| 361 |
FMT_D = 17, |
|
| 362 |
FMT_E = 18, |
|
| 363 |
FMT_Q = 19, |
|
| 364 |
FMT_W = 20, |
|
| 365 |
FMT_L = 21, |
|
| 366 |
FMT_PS = 22, |
|
| 367 |
/* 23 - 31 are reserved */ |
|
| 368 |
}; |
|
| 369 |
|
|
| 357 | 370 |
enum {
|
| 358 | 371 |
OPC_MFC1 = (0x00 << 21) | OPC_CP1, |
| 359 | 372 |
OPC_DMFC1 = (0x01 << 21) | OPC_CP1, |
| ... | ... | |
| 366 | 379 |
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ |
| 367 | 380 |
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, |
| 368 | 381 |
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, |
| 369 |
OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
|
|
| 370 |
OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
|
|
| 371 |
OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
|
|
| 372 |
OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
|
|
| 373 |
OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
|
|
| 374 |
OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
|
|
| 375 |
OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */
|
|
| 382 |
OPC_S_FMT = (FMT_S << 21) | OPC_CP1, /* 16: fmt=single fp */
|
|
| 383 |
OPC_D_FMT = (FMT_D << 21) | OPC_CP1, /* 17: fmt=double fp */
|
|
| 384 |
OPC_E_FMT = (FMT_E << 21) | OPC_CP1, /* 18: fmt=extended fp */
|
|
| 385 |
OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1, /* 19: fmt=quad fp */
|
|
| 386 |
OPC_W_FMT = (FMT_W << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
|
|
| 387 |
OPC_L_FMT = (FMT_L << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
|
|
| 388 |
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1, /* 22: fmt=paired single fp */
|
|
| 376 | 389 |
}; |
| 377 | 390 |
|
| 378 | 391 |
#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) |
| ... | ... | |
| 5714 | 5727 |
|
| 5715 | 5728 |
#define FOP(func, fmt) (((fmt) << 21) | (func)) |
| 5716 | 5729 |
|
| 5730 |
enum fopcode {
|
|
| 5731 |
OPC_ADD_S = FOP(0, FMT_S), |
|
| 5732 |
OPC_SUB_S = FOP(1, FMT_S), |
|
| 5733 |
OPC_MUL_S = FOP(2, FMT_S), |
|
| 5734 |
OPC_DIV_S = FOP(3, FMT_S), |
|
| 5735 |
OPC_SQRT_S = FOP(4, FMT_S), |
|
| 5736 |
OPC_ABS_S = FOP(5, FMT_S), |
|
| 5737 |
OPC_MOV_S = FOP(6, FMT_S), |
|
| 5738 |
OPC_NEG_S = FOP(7, FMT_S), |
|
| 5739 |
OPC_ROUND_L_S = FOP(8, FMT_S), |
|
| 5740 |
OPC_TRUNC_L_S = FOP(9, FMT_S), |
|
| 5741 |
OPC_CEIL_L_S = FOP(10, FMT_S), |
|
| 5742 |
OPC_FLOOR_L_S = FOP(11, FMT_S), |
|
| 5743 |
OPC_ROUND_W_S = FOP(12, FMT_S), |
|
| 5744 |
OPC_TRUNC_W_S = FOP(13, FMT_S), |
|
| 5745 |
OPC_CEIL_W_S = FOP(14, FMT_S), |
|
| 5746 |
OPC_FLOOR_W_S = FOP(15, FMT_S), |
|
| 5747 |
OPC_MOVCF_S = FOP(17, FMT_S), |
|
| 5748 |
OPC_MOVZ_S = FOP(18, FMT_S), |
|
| 5749 |
OPC_MOVN_S = FOP(19, FMT_S), |
|
| 5750 |
OPC_RECIP_S = FOP(21, FMT_S), |
|
| 5751 |
OPC_RSQRT_S = FOP(22, FMT_S), |
|
| 5752 |
OPC_RECIP2_S = FOP(28, FMT_S), |
|
| 5753 |
OPC_RECIP1_S = FOP(29, FMT_S), |
|
| 5754 |
OPC_RSQRT1_S = FOP(30, FMT_S), |
|
| 5755 |
OPC_RSQRT2_S = FOP(31, FMT_S), |
|
| 5756 |
OPC_CVT_D_S = FOP(33, FMT_S), |
|
| 5757 |
OPC_CVT_W_S = FOP(36, FMT_S), |
|
| 5758 |
OPC_CVT_L_S = FOP(37, FMT_S), |
|
| 5759 |
OPC_CVT_PS_S = FOP(38, FMT_S), |
|
| 5760 |
OPC_CMP_F_S = FOP (48, FMT_S), |
|
| 5761 |
OPC_CMP_UN_S = FOP (49, FMT_S), |
|
| 5762 |
OPC_CMP_EQ_S = FOP (50, FMT_S), |
|
| 5763 |
OPC_CMP_UEQ_S = FOP (51, FMT_S), |
|
| 5764 |
OPC_CMP_OLT_S = FOP (52, FMT_S), |
|
| 5765 |
OPC_CMP_ULT_S = FOP (53, FMT_S), |
|
| 5766 |
OPC_CMP_OLE_S = FOP (54, FMT_S), |
|
| 5767 |
OPC_CMP_ULE_S = FOP (55, FMT_S), |
|
| 5768 |
OPC_CMP_SF_S = FOP (56, FMT_S), |
|
| 5769 |
OPC_CMP_NGLE_S = FOP (57, FMT_S), |
|
| 5770 |
OPC_CMP_SEQ_S = FOP (58, FMT_S), |
|
| 5771 |
OPC_CMP_NGL_S = FOP (59, FMT_S), |
|
| 5772 |
OPC_CMP_LT_S = FOP (60, FMT_S), |
|
| 5773 |
OPC_CMP_NGE_S = FOP (61, FMT_S), |
|
| 5774 |
OPC_CMP_LE_S = FOP (62, FMT_S), |
|
| 5775 |
OPC_CMP_NGT_S = FOP (63, FMT_S), |
|
| 5776 |
|
|
| 5777 |
OPC_ADD_D = FOP(0, FMT_D), |
|
| 5778 |
OPC_SUB_D = FOP(1, FMT_D), |
|
| 5779 |
OPC_MUL_D = FOP(2, FMT_D), |
|
| 5780 |
OPC_DIV_D = FOP(3, FMT_D), |
|
| 5781 |
OPC_SQRT_D = FOP(4, FMT_D), |
|
| 5782 |
OPC_ABS_D = FOP(5, FMT_D), |
|
| 5783 |
OPC_MOV_D = FOP(6, FMT_D), |
|
| 5784 |
OPC_NEG_D = FOP(7, FMT_D), |
|
| 5785 |
OPC_ROUND_L_D = FOP(8, FMT_D), |
|
| 5786 |
OPC_TRUNC_L_D = FOP(9, FMT_D), |
|
| 5787 |
OPC_CEIL_L_D = FOP(10, FMT_D), |
|
| 5788 |
OPC_FLOOR_L_D = FOP(11, FMT_D), |
|
| 5789 |
OPC_ROUND_W_D = FOP(12, FMT_D), |
|
| 5790 |
OPC_TRUNC_W_D = FOP(13, FMT_D), |
|
| 5791 |
OPC_CEIL_W_D = FOP(14, FMT_D), |
|
| 5792 |
OPC_FLOOR_W_D = FOP(15, FMT_D), |
|
| 5793 |
OPC_MOVCF_D = FOP(17, FMT_D), |
|
| 5794 |
OPC_MOVZ_D = FOP(18, FMT_D), |
|
| 5795 |
OPC_MOVN_D = FOP(19, FMT_D), |
|
| 5796 |
OPC_RECIP_D = FOP(21, FMT_D), |
|
| 5797 |
OPC_RSQRT_D = FOP(22, FMT_D), |
|
| 5798 |
OPC_RECIP2_D = FOP(28, FMT_D), |
|
| 5799 |
OPC_RECIP1_D = FOP(29, FMT_D), |
|
| 5800 |
OPC_RSQRT1_D = FOP(30, FMT_D), |
|
| 5801 |
OPC_RSQRT2_D = FOP(31, FMT_D), |
|
| 5802 |
OPC_CVT_S_D = FOP(32, FMT_D), |
|
| 5803 |
OPC_CVT_W_D = FOP(36, FMT_D), |
|
| 5804 |
OPC_CVT_L_D = FOP(37, FMT_D), |
|
| 5805 |
OPC_CMP_F_D = FOP (48, FMT_D), |
|
| 5806 |
OPC_CMP_UN_D = FOP (49, FMT_D), |
|
| 5807 |
OPC_CMP_EQ_D = FOP (50, FMT_D), |
|
| 5808 |
OPC_CMP_UEQ_D = FOP (51, FMT_D), |
|
| 5809 |
OPC_CMP_OLT_D = FOP (52, FMT_D), |
|
| 5810 |
OPC_CMP_ULT_D = FOP (53, FMT_D), |
|
| 5811 |
OPC_CMP_OLE_D = FOP (54, FMT_D), |
|
| 5812 |
OPC_CMP_ULE_D = FOP (55, FMT_D), |
|
| 5813 |
OPC_CMP_SF_D = FOP (56, FMT_D), |
|
| 5814 |
OPC_CMP_NGLE_D = FOP (57, FMT_D), |
|
| 5815 |
OPC_CMP_SEQ_D = FOP (58, FMT_D), |
|
| 5816 |
OPC_CMP_NGL_D = FOP (59, FMT_D), |
|
| 5817 |
OPC_CMP_LT_D = FOP (60, FMT_D), |
|
| 5818 |
OPC_CMP_NGE_D = FOP (61, FMT_D), |
|
| 5819 |
OPC_CMP_LE_D = FOP (62, FMT_D), |
|
| 5820 |
OPC_CMP_NGT_D = FOP (63, FMT_D), |
|
| 5821 |
|
|
| 5822 |
OPC_CVT_S_W = FOP(32, FMT_W), |
|
| 5823 |
OPC_CVT_D_W = FOP(33, FMT_W), |
|
| 5824 |
OPC_CVT_S_L = FOP(32, FMT_L), |
|
| 5825 |
OPC_CVT_D_L = FOP(33, FMT_L), |
|
| 5826 |
OPC_CVT_PS_PW = FOP(38, FMT_W), |
|
| 5827 |
|
|
| 5828 |
OPC_ADD_PS = FOP(0, FMT_PS), |
|
| 5829 |
OPC_SUB_PS = FOP(1, FMT_PS), |
|
| 5830 |
OPC_MUL_PS = FOP(2, FMT_PS), |
|
| 5831 |
OPC_DIV_PS = FOP(3, FMT_PS), |
|
| 5832 |
OPC_ABS_PS = FOP(5, FMT_PS), |
|
| 5833 |
OPC_MOV_PS = FOP(6, FMT_PS), |
|
| 5834 |
OPC_NEG_PS = FOP(7, FMT_PS), |
|
| 5835 |
OPC_MOVCF_PS = FOP(17, FMT_PS), |
|
| 5836 |
OPC_MOVZ_PS = FOP(18, FMT_PS), |
|
| 5837 |
OPC_MOVN_PS = FOP(19, FMT_PS), |
|
| 5838 |
OPC_ADDR_PS = FOP(24, FMT_PS), |
|
| 5839 |
OPC_MULR_PS = FOP(26, FMT_PS), |
|
| 5840 |
OPC_RECIP2_PS = FOP(28, FMT_PS), |
|
| 5841 |
OPC_RECIP1_PS = FOP(29, FMT_PS), |
|
| 5842 |
OPC_RSQRT1_PS = FOP(30, FMT_PS), |
|
| 5843 |
OPC_RSQRT2_PS = FOP(31, FMT_PS), |
|
| 5844 |
|
|
| 5845 |
OPC_CVT_S_PU = FOP(32, FMT_PS), |
|
| 5846 |
OPC_CVT_PW_PS = FOP(36, FMT_PS), |
|
| 5847 |
OPC_CVT_S_PL = FOP(40, FMT_PS), |
|
| 5848 |
OPC_PLL_PS = FOP(44, FMT_PS), |
|
| 5849 |
OPC_PLU_PS = FOP(45, FMT_PS), |
|
| 5850 |
OPC_PUL_PS = FOP(46, FMT_PS), |
|
| 5851 |
OPC_PUU_PS = FOP(47, FMT_PS), |
|
| 5852 |
OPC_CMP_F_PS = FOP (48, FMT_PS), |
|
| 5853 |
OPC_CMP_UN_PS = FOP (49, FMT_PS), |
|
| 5854 |
OPC_CMP_EQ_PS = FOP (50, FMT_PS), |
|
| 5855 |
OPC_CMP_UEQ_PS = FOP (51, FMT_PS), |
|
| 5856 |
OPC_CMP_OLT_PS = FOP (52, FMT_PS), |
|
| 5857 |
OPC_CMP_ULT_PS = FOP (53, FMT_PS), |
|
| 5858 |
OPC_CMP_OLE_PS = FOP (54, FMT_PS), |
|
| 5859 |
OPC_CMP_ULE_PS = FOP (55, FMT_PS), |
|
| 5860 |
OPC_CMP_SF_PS = FOP (56, FMT_PS), |
|
| 5861 |
OPC_CMP_NGLE_PS = FOP (57, FMT_PS), |
|
| 5862 |
OPC_CMP_SEQ_PS = FOP (58, FMT_PS), |
|
| 5863 |
OPC_CMP_NGL_PS = FOP (59, FMT_PS), |
|
| 5864 |
OPC_CMP_LT_PS = FOP (60, FMT_PS), |
|
| 5865 |
OPC_CMP_NGE_PS = FOP (61, FMT_PS), |
|
| 5866 |
OPC_CMP_LE_PS = FOP (62, FMT_PS), |
|
| 5867 |
OPC_CMP_NGT_PS = FOP (63, FMT_PS), |
|
| 5868 |
}; |
|
| 5869 |
|
|
| 5717 | 5870 |
static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) |
| 5718 | 5871 |
{
|
| 5719 | 5872 |
const char *opn = "cp1 move"; |
| ... | ... | |
| 5894 | 6047 |
} |
| 5895 | 6048 |
|
| 5896 | 6049 |
|
| 5897 |
static void gen_farith (DisasContext *ctx, uint32_t op1,
|
|
| 6050 |
static void gen_farith (DisasContext *ctx, enum fopcode op1,
|
|
| 5898 | 6051 |
int ft, int fs, int fd, int cc) |
| 5899 | 6052 |
{
|
| 5900 | 6053 |
const char *opn = "farith"; |
| ... | ... | |
| 5937 | 6090 |
enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
|
| 5938 | 6091 |
uint32_t func = ctx->opcode & 0x3f; |
| 5939 | 6092 |
|
| 5940 |
switch (ctx->opcode & FOP(0x3f, 0x1f)) {
|
|
| 5941 |
case FOP(0, 16):
|
|
| 6093 |
switch (op1) {
|
|
| 6094 |
case OPC_ADD_S:
|
|
| 5942 | 6095 |
{
|
| 5943 | 6096 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 5944 | 6097 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| ... | ... | |
| 5953 | 6106 |
opn = "add.s"; |
| 5954 | 6107 |
optype = BINOP; |
| 5955 | 6108 |
break; |
| 5956 |
case FOP(1, 16):
|
|
| 6109 |
case OPC_SUB_S:
|
|
| 5957 | 6110 |
{
|
| 5958 | 6111 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 5959 | 6112 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| ... | ... | |
| 5968 | 6121 |
opn = "sub.s"; |
| 5969 | 6122 |
optype = BINOP; |
| 5970 | 6123 |
break; |
| 5971 |
case FOP(2, 16):
|
|
| 6124 |
case OPC_MUL_S:
|
|
| 5972 | 6125 |
{
|
| 5973 | 6126 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 5974 | 6127 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| ... | ... | |
| 5983 | 6136 |
opn = "mul.s"; |
| 5984 | 6137 |
optype = BINOP; |
| 5985 | 6138 |
break; |
| 5986 |
case FOP(3, 16):
|
|
| 6139 |
case OPC_DIV_S:
|
|
| 5987 | 6140 |
{
|
| 5988 | 6141 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 5989 | 6142 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| ... | ... | |
| 5998 | 6151 |
opn = "div.s"; |
| 5999 | 6152 |
optype = BINOP; |
| 6000 | 6153 |
break; |
| 6001 |
case FOP(4, 16):
|
|
| 6154 |
case OPC_SQRT_S:
|
|
| 6002 | 6155 |
{
|
| 6003 | 6156 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6004 | 6157 |
|
| ... | ... | |
| 6009 | 6162 |
} |
| 6010 | 6163 |
opn = "sqrt.s"; |
| 6011 | 6164 |
break; |
| 6012 |
case FOP(5, 16):
|
|
| 6165 |
case OPC_ABS_S:
|
|
| 6013 | 6166 |
{
|
| 6014 | 6167 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6015 | 6168 |
|
| ... | ... | |
| 6020 | 6173 |
} |
| 6021 | 6174 |
opn = "abs.s"; |
| 6022 | 6175 |
break; |
| 6023 |
case FOP(6, 16):
|
|
| 6176 |
case OPC_MOV_S:
|
|
| 6024 | 6177 |
{
|
| 6025 | 6178 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6026 | 6179 |
|
| ... | ... | |
| 6030 | 6183 |
} |
| 6031 | 6184 |
opn = "mov.s"; |
| 6032 | 6185 |
break; |
| 6033 |
case FOP(7, 16):
|
|
| 6186 |
case OPC_NEG_S:
|
|
| 6034 | 6187 |
{
|
| 6035 | 6188 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6036 | 6189 |
|
| ... | ... | |
| 6041 | 6194 |
} |
| 6042 | 6195 |
opn = "neg.s"; |
| 6043 | 6196 |
break; |
| 6044 |
case FOP(8, 16):
|
|
| 6197 |
case OPC_ROUND_L_S:
|
|
| 6045 | 6198 |
check_cp1_64bitmode(ctx); |
| 6046 | 6199 |
{
|
| 6047 | 6200 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6055 | 6208 |
} |
| 6056 | 6209 |
opn = "round.l.s"; |
| 6057 | 6210 |
break; |
| 6058 |
case FOP(9, 16):
|
|
| 6211 |
case OPC_TRUNC_L_S:
|
|
| 6059 | 6212 |
check_cp1_64bitmode(ctx); |
| 6060 | 6213 |
{
|
| 6061 | 6214 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6069 | 6222 |
} |
| 6070 | 6223 |
opn = "trunc.l.s"; |
| 6071 | 6224 |
break; |
| 6072 |
case FOP(10, 16):
|
|
| 6225 |
case OPC_CEIL_L_S:
|
|
| 6073 | 6226 |
check_cp1_64bitmode(ctx); |
| 6074 | 6227 |
{
|
| 6075 | 6228 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6083 | 6236 |
} |
| 6084 | 6237 |
opn = "ceil.l.s"; |
| 6085 | 6238 |
break; |
| 6086 |
case FOP(11, 16):
|
|
| 6239 |
case OPC_FLOOR_L_S:
|
|
| 6087 | 6240 |
check_cp1_64bitmode(ctx); |
| 6088 | 6241 |
{
|
| 6089 | 6242 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6097 | 6250 |
} |
| 6098 | 6251 |
opn = "floor.l.s"; |
| 6099 | 6252 |
break; |
| 6100 |
case FOP(12, 16):
|
|
| 6253 |
case OPC_ROUND_W_S:
|
|
| 6101 | 6254 |
{
|
| 6102 | 6255 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6103 | 6256 |
|
| ... | ... | |
| 6108 | 6261 |
} |
| 6109 | 6262 |
opn = "round.w.s"; |
| 6110 | 6263 |
break; |
| 6111 |
case FOP(13, 16):
|
|
| 6264 |
case OPC_TRUNC_W_S:
|
|
| 6112 | 6265 |
{
|
| 6113 | 6266 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6114 | 6267 |
|
| ... | ... | |
| 6119 | 6272 |
} |
| 6120 | 6273 |
opn = "trunc.w.s"; |
| 6121 | 6274 |
break; |
| 6122 |
case FOP(14, 16):
|
|
| 6275 |
case OPC_CEIL_W_S:
|
|
| 6123 | 6276 |
{
|
| 6124 | 6277 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6125 | 6278 |
|
| ... | ... | |
| 6130 | 6283 |
} |
| 6131 | 6284 |
opn = "ceil.w.s"; |
| 6132 | 6285 |
break; |
| 6133 |
case FOP(15, 16):
|
|
| 6286 |
case OPC_FLOOR_W_S:
|
|
| 6134 | 6287 |
{
|
| 6135 | 6288 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6136 | 6289 |
|
| ... | ... | |
| 6141 | 6294 |
} |
| 6142 | 6295 |
opn = "floor.w.s"; |
| 6143 | 6296 |
break; |
| 6144 |
case FOP(17, 16):
|
|
| 6297 |
case OPC_MOVCF_S:
|
|
| 6145 | 6298 |
gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
| 6146 | 6299 |
opn = "movcf.s"; |
| 6147 | 6300 |
break; |
| 6148 |
case FOP(18, 16):
|
|
| 6301 |
case OPC_MOVZ_S:
|
|
| 6149 | 6302 |
{
|
| 6150 | 6303 |
int l1 = gen_new_label(); |
| 6151 | 6304 |
TCGv_i32 fp0; |
| ... | ... | |
| 6161 | 6314 |
} |
| 6162 | 6315 |
opn = "movz.s"; |
| 6163 | 6316 |
break; |
| 6164 |
case FOP(19, 16):
|
|
| 6317 |
case OPC_MOVN_S:
|
|
| 6165 | 6318 |
{
|
| 6166 | 6319 |
int l1 = gen_new_label(); |
| 6167 | 6320 |
TCGv_i32 fp0; |
| ... | ... | |
| 6177 | 6330 |
} |
| 6178 | 6331 |
opn = "movn.s"; |
| 6179 | 6332 |
break; |
| 6180 |
case FOP(21, 16):
|
|
| 6333 |
case OPC_RECIP_S:
|
|
| 6181 | 6334 |
check_cop1x(ctx); |
| 6182 | 6335 |
{
|
| 6183 | 6336 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6189 | 6342 |
} |
| 6190 | 6343 |
opn = "recip.s"; |
| 6191 | 6344 |
break; |
| 6192 |
case FOP(22, 16):
|
|
| 6345 |
case OPC_RSQRT_S:
|
|
| 6193 | 6346 |
check_cop1x(ctx); |
| 6194 | 6347 |
{
|
| 6195 | 6348 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6201 | 6354 |
} |
| 6202 | 6355 |
opn = "rsqrt.s"; |
| 6203 | 6356 |
break; |
| 6204 |
case FOP(28, 16):
|
|
| 6357 |
case OPC_RECIP2_S:
|
|
| 6205 | 6358 |
check_cp1_64bitmode(ctx); |
| 6206 | 6359 |
{
|
| 6207 | 6360 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6216 | 6369 |
} |
| 6217 | 6370 |
opn = "recip2.s"; |
| 6218 | 6371 |
break; |
| 6219 |
case FOP(29, 16):
|
|
| 6372 |
case OPC_RECIP1_S:
|
|
| 6220 | 6373 |
check_cp1_64bitmode(ctx); |
| 6221 | 6374 |
{
|
| 6222 | 6375 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6228 | 6381 |
} |
| 6229 | 6382 |
opn = "recip1.s"; |
| 6230 | 6383 |
break; |
| 6231 |
case FOP(30, 16):
|
|
| 6384 |
case OPC_RSQRT1_S:
|
|
| 6232 | 6385 |
check_cp1_64bitmode(ctx); |
| 6233 | 6386 |
{
|
| 6234 | 6387 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6240 | 6393 |
} |
| 6241 | 6394 |
opn = "rsqrt1.s"; |
| 6242 | 6395 |
break; |
| 6243 |
case FOP(31, 16):
|
|
| 6396 |
case OPC_RSQRT2_S:
|
|
| 6244 | 6397 |
check_cp1_64bitmode(ctx); |
| 6245 | 6398 |
{
|
| 6246 | 6399 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 6255 | 6408 |
} |
| 6256 | 6409 |
opn = "rsqrt2.s"; |
| 6257 | 6410 |
break; |
| 6258 |
case FOP(33, 16):
|
|
| 6411 |
case OPC_CVT_D_S:
|
|
| 6259 | 6412 |
check_cp1_registers(ctx, fd); |
| 6260 | 6413 |
{
|
| 6261 | 6414 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6269 | 6422 |
} |
| 6270 | 6423 |
opn = "cvt.d.s"; |
| 6271 | 6424 |
break; |
| 6272 |
case FOP(36, 16):
|
|
| 6425 |
case OPC_CVT_W_S:
|
|
| 6273 | 6426 |
{
|
| 6274 | 6427 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6275 | 6428 |
|
| ... | ... | |
| 6280 | 6433 |
} |
| 6281 | 6434 |
opn = "cvt.w.s"; |
| 6282 | 6435 |
break; |
| 6283 |
case FOP(37, 16):
|
|
| 6436 |
case OPC_CVT_L_S:
|
|
| 6284 | 6437 |
check_cp1_64bitmode(ctx); |
| 6285 | 6438 |
{
|
| 6286 | 6439 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6294 | 6447 |
} |
| 6295 | 6448 |
opn = "cvt.l.s"; |
| 6296 | 6449 |
break; |
| 6297 |
case FOP(38, 16):
|
|
| 6450 |
case OPC_CVT_PS_S:
|
|
| 6298 | 6451 |
check_cp1_64bitmode(ctx); |
| 6299 | 6452 |
{
|
| 6300 | 6453 |
TCGv_i64 fp64 = tcg_temp_new_i64(); |
| ... | ... | |
| 6311 | 6464 |
} |
| 6312 | 6465 |
opn = "cvt.ps.s"; |
| 6313 | 6466 |
break; |
| 6314 |
case FOP(48, 16):
|
|
| 6315 |
case FOP(49, 16):
|
|
| 6316 |
case FOP(50, 16):
|
|
| 6317 |
case FOP(51, 16):
|
|
| 6318 |
case FOP(52, 16):
|
|
| 6319 |
case FOP(53, 16):
|
|
| 6320 |
case FOP(54, 16):
|
|
| 6321 |
case FOP(55, 16):
|
|
| 6322 |
case FOP(56, 16):
|
|
| 6323 |
case FOP(57, 16):
|
|
| 6324 |
case FOP(58, 16):
|
|
| 6325 |
case FOP(59, 16):
|
|
| 6326 |
case FOP(60, 16):
|
|
| 6327 |
case FOP(61, 16):
|
|
| 6328 |
case FOP(62, 16):
|
|
| 6329 |
case FOP(63, 16):
|
|
| 6467 |
case OPC_CMP_F_S:
|
|
| 6468 |
case OPC_CMP_UN_S:
|
|
| 6469 |
case OPC_CMP_EQ_S:
|
|
| 6470 |
case OPC_CMP_UEQ_S:
|
|
| 6471 |
case OPC_CMP_OLT_S:
|
|
| 6472 |
case OPC_CMP_ULT_S:
|
|
| 6473 |
case OPC_CMP_OLE_S:
|
|
| 6474 |
case OPC_CMP_ULE_S:
|
|
| 6475 |
case OPC_CMP_SF_S:
|
|
| 6476 |
case OPC_CMP_NGLE_S:
|
|
| 6477 |
case OPC_CMP_SEQ_S:
|
|
| 6478 |
case OPC_CMP_NGL_S:
|
|
| 6479 |
case OPC_CMP_LT_S:
|
|
| 6480 |
case OPC_CMP_NGE_S:
|
|
| 6481 |
case OPC_CMP_LE_S:
|
|
| 6482 |
case OPC_CMP_NGT_S:
|
|
| 6330 | 6483 |
{
|
| 6331 | 6484 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6332 | 6485 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| ... | ... | |
| 6345 | 6498 |
tcg_temp_free_i32(fp1); |
| 6346 | 6499 |
} |
| 6347 | 6500 |
break; |
| 6348 |
case FOP(0, 17):
|
|
| 6501 |
case OPC_ADD_D:
|
|
| 6349 | 6502 |
check_cp1_registers(ctx, fs | ft | fd); |
| 6350 | 6503 |
{
|
| 6351 | 6504 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6361 | 6514 |
opn = "add.d"; |
| 6362 | 6515 |
optype = BINOP; |
| 6363 | 6516 |
break; |
| 6364 |
case FOP(1, 17):
|
|
| 6517 |
case OPC_SUB_D:
|
|
| 6365 | 6518 |
check_cp1_registers(ctx, fs | ft | fd); |
| 6366 | 6519 |
{
|
| 6367 | 6520 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6377 | 6530 |
opn = "sub.d"; |
| 6378 | 6531 |
optype = BINOP; |
| 6379 | 6532 |
break; |
| 6380 |
case FOP(2, 17):
|
|
| 6533 |
case OPC_MUL_D:
|
|
| 6381 | 6534 |
check_cp1_registers(ctx, fs | ft | fd); |
| 6382 | 6535 |
{
|
| 6383 | 6536 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6393 | 6546 |
opn = "mul.d"; |
| 6394 | 6547 |
optype = BINOP; |
| 6395 | 6548 |
break; |
| 6396 |
case FOP(3, 17):
|
|
| 6549 |
case OPC_DIV_D:
|
|
| 6397 | 6550 |
check_cp1_registers(ctx, fs | ft | fd); |
| 6398 | 6551 |
{
|
| 6399 | 6552 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6409 | 6562 |
opn = "div.d"; |
| 6410 | 6563 |
optype = BINOP; |
| 6411 | 6564 |
break; |
| 6412 |
case FOP(4, 17):
|
|
| 6565 |
case OPC_SQRT_D:
|
|
| 6413 | 6566 |
check_cp1_registers(ctx, fs | fd); |
| 6414 | 6567 |
{
|
| 6415 | 6568 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6421 | 6574 |
} |
| 6422 | 6575 |
opn = "sqrt.d"; |
| 6423 | 6576 |
break; |
| 6424 |
case FOP(5, 17):
|
|
| 6577 |
case OPC_ABS_D:
|
|
| 6425 | 6578 |
check_cp1_registers(ctx, fs | fd); |
| 6426 | 6579 |
{
|
| 6427 | 6580 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6433 | 6586 |
} |
| 6434 | 6587 |
opn = "abs.d"; |
| 6435 | 6588 |
break; |
| 6436 |
case FOP(6, 17):
|
|
| 6589 |
case OPC_MOV_D:
|
|
| 6437 | 6590 |
check_cp1_registers(ctx, fs | fd); |
| 6438 | 6591 |
{
|
| 6439 | 6592 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6444 | 6597 |
} |
| 6445 | 6598 |
opn = "mov.d"; |
| 6446 | 6599 |
break; |
| 6447 |
case FOP(7, 17):
|
|
| 6600 |
case OPC_NEG_D:
|
|
| 6448 | 6601 |
check_cp1_registers(ctx, fs | fd); |
| 6449 | 6602 |
{
|
| 6450 | 6603 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6456 | 6609 |
} |
| 6457 | 6610 |
opn = "neg.d"; |
| 6458 | 6611 |
break; |
| 6459 |
case FOP(8, 17):
|
|
| 6612 |
case OPC_ROUND_L_D:
|
|
| 6460 | 6613 |
check_cp1_64bitmode(ctx); |
| 6461 | 6614 |
{
|
| 6462 | 6615 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6468 | 6621 |
} |
| 6469 | 6622 |
opn = "round.l.d"; |
| 6470 | 6623 |
break; |
| 6471 |
case FOP(9, 17):
|
|
| 6624 |
case OPC_TRUNC_L_D:
|
|
| 6472 | 6625 |
check_cp1_64bitmode(ctx); |
| 6473 | 6626 |
{
|
| 6474 | 6627 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6480 | 6633 |
} |
| 6481 | 6634 |
opn = "trunc.l.d"; |
| 6482 | 6635 |
break; |
| 6483 |
case FOP(10, 17):
|
|
| 6636 |
case OPC_CEIL_L_D:
|
|
| 6484 | 6637 |
check_cp1_64bitmode(ctx); |
| 6485 | 6638 |
{
|
| 6486 | 6639 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6492 | 6645 |
} |
| 6493 | 6646 |
opn = "ceil.l.d"; |
| 6494 | 6647 |
break; |
| 6495 |
case FOP(11, 17):
|
|
| 6648 |
case OPC_FLOOR_L_D:
|
|
| 6496 | 6649 |
check_cp1_64bitmode(ctx); |
| 6497 | 6650 |
{
|
| 6498 | 6651 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6504 | 6657 |
} |
| 6505 | 6658 |
opn = "floor.l.d"; |
| 6506 | 6659 |
break; |
| 6507 |
case FOP(12, 17):
|
|
| 6660 |
case OPC_ROUND_W_D:
|
|
| 6508 | 6661 |
check_cp1_registers(ctx, fs); |
| 6509 | 6662 |
{
|
| 6510 | 6663 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6518 | 6671 |
} |
| 6519 | 6672 |
opn = "round.w.d"; |
| 6520 | 6673 |
break; |
| 6521 |
case FOP(13, 17):
|
|
| 6674 |
case OPC_TRUNC_W_D:
|
|
| 6522 | 6675 |
check_cp1_registers(ctx, fs); |
| 6523 | 6676 |
{
|
| 6524 | 6677 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6532 | 6685 |
} |
| 6533 | 6686 |
opn = "trunc.w.d"; |
| 6534 | 6687 |
break; |
| 6535 |
case FOP(14, 17):
|
|
| 6688 |
case OPC_CEIL_W_D:
|
|
| 6536 | 6689 |
check_cp1_registers(ctx, fs); |
| 6537 | 6690 |
{
|
| 6538 | 6691 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6546 | 6699 |
} |
| 6547 | 6700 |
opn = "ceil.w.d"; |
| 6548 | 6701 |
break; |
| 6549 |
case FOP(15, 17):
|
|
| 6702 |
case OPC_FLOOR_W_D:
|
|
| 6550 | 6703 |
check_cp1_registers(ctx, fs); |
| 6551 | 6704 |
{
|
| 6552 | 6705 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6560 | 6713 |
} |
| 6561 | 6714 |
opn = "floor.w.d"; |
| 6562 | 6715 |
break; |
| 6563 |
case FOP(17, 17):
|
|
| 6716 |
case OPC_MOVCF_D:
|
|
| 6564 | 6717 |
gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
| 6565 | 6718 |
opn = "movcf.d"; |
| 6566 | 6719 |
break; |
| 6567 |
case FOP(18, 17):
|
|
| 6720 |
case OPC_MOVZ_D:
|
|
| 6568 | 6721 |
{
|
| 6569 | 6722 |
int l1 = gen_new_label(); |
| 6570 | 6723 |
TCGv_i64 fp0; |
| ... | ... | |
| 6580 | 6733 |
} |
| 6581 | 6734 |
opn = "movz.d"; |
| 6582 | 6735 |
break; |
| 6583 |
case FOP(19, 17):
|
|
| 6736 |
case OPC_MOVN_D:
|
|
| 6584 | 6737 |
{
|
| 6585 | 6738 |
int l1 = gen_new_label(); |
| 6586 | 6739 |
TCGv_i64 fp0; |
| ... | ... | |
| 6596 | 6749 |
} |
| 6597 | 6750 |
opn = "movn.d"; |
| 6598 | 6751 |
break; |
| 6599 |
case FOP(21, 17):
|
|
| 6752 |
case OPC_RECIP_D:
|
|
| 6600 | 6753 |
check_cp1_64bitmode(ctx); |
| 6601 | 6754 |
{
|
| 6602 | 6755 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6608 | 6761 |
} |
| 6609 | 6762 |
opn = "recip.d"; |
| 6610 | 6763 |
break; |
| 6611 |
case FOP(22, 17):
|
|
| 6764 |
case OPC_RSQRT_D:
|
|
| 6612 | 6765 |
check_cp1_64bitmode(ctx); |
| 6613 | 6766 |
{
|
| 6614 | 6767 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6620 | 6773 |
} |
| 6621 | 6774 |
opn = "rsqrt.d"; |
| 6622 | 6775 |
break; |
| 6623 |
case FOP(28, 17):
|
|
| 6776 |
case OPC_RECIP2_D:
|
|
| 6624 | 6777 |
check_cp1_64bitmode(ctx); |
| 6625 | 6778 |
{
|
| 6626 | 6779 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6635 | 6788 |
} |
| 6636 | 6789 |
opn = "recip2.d"; |
| 6637 | 6790 |
break; |
| 6638 |
case FOP(29, 17):
|
|
| 6791 |
case OPC_RECIP1_D:
|
|
| 6639 | 6792 |
check_cp1_64bitmode(ctx); |
| 6640 | 6793 |
{
|
| 6641 | 6794 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6647 | 6800 |
} |
| 6648 | 6801 |
opn = "recip1.d"; |
| 6649 | 6802 |
break; |
| 6650 |
case FOP(30, 17):
|
|
| 6803 |
case OPC_RSQRT1_D:
|
|
| 6651 | 6804 |
check_cp1_64bitmode(ctx); |
| 6652 | 6805 |
{
|
| 6653 | 6806 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6659 | 6812 |
} |
| 6660 | 6813 |
opn = "rsqrt1.d"; |
| 6661 | 6814 |
break; |
| 6662 |
case FOP(31, 17):
|
|
| 6815 |
case OPC_RSQRT2_D:
|
|
| 6663 | 6816 |
check_cp1_64bitmode(ctx); |
| 6664 | 6817 |
{
|
| 6665 | 6818 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6674 | 6827 |
} |
| 6675 | 6828 |
opn = "rsqrt2.d"; |
| 6676 | 6829 |
break; |
| 6677 |
case FOP(48, 17):
|
|
| 6678 |
case FOP(49, 17):
|
|
| 6679 |
case FOP(50, 17):
|
|
| 6680 |
case FOP(51, 17):
|
|
| 6681 |
case FOP(52, 17):
|
|
| 6682 |
case FOP(53, 17):
|
|
| 6683 |
case FOP(54, 17):
|
|
| 6684 |
case FOP(55, 17):
|
|
| 6685 |
case FOP(56, 17):
|
|
| 6686 |
case FOP(57, 17):
|
|
| 6687 |
case FOP(58, 17):
|
|
| 6688 |
case FOP(59, 17):
|
|
| 6689 |
case FOP(60, 17):
|
|
| 6690 |
case FOP(61, 17):
|
|
| 6691 |
case FOP(62, 17):
|
|
| 6692 |
case FOP(63, 17):
|
|
| 6830 |
case OPC_CMP_F_D:
|
|
| 6831 |
case OPC_CMP_UN_D:
|
|
| 6832 |
case OPC_CMP_EQ_D:
|
|
| 6833 |
case OPC_CMP_UEQ_D:
|
|
| 6834 |
case OPC_CMP_OLT_D:
|
|
| 6835 |
case OPC_CMP_ULT_D:
|
|
| 6836 |
case OPC_CMP_OLE_D:
|
|
| 6837 |
case OPC_CMP_ULE_D:
|
|
| 6838 |
case OPC_CMP_SF_D:
|
|
| 6839 |
case OPC_CMP_NGLE_D:
|
|
| 6840 |
case OPC_CMP_SEQ_D:
|
|
| 6841 |
case OPC_CMP_NGL_D:
|
|
| 6842 |
case OPC_CMP_LT_D:
|
|
| 6843 |
case OPC_CMP_NGE_D:
|
|
| 6844 |
case OPC_CMP_LE_D:
|
|
| 6845 |
case OPC_CMP_NGT_D:
|
|
| 6693 | 6846 |
{
|
| 6694 | 6847 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 6695 | 6848 |
TCGv_i64 fp1 = tcg_temp_new_i64(); |
| ... | ... | |
| 6710 | 6863 |
tcg_temp_free_i64(fp1); |
| 6711 | 6864 |
} |
| 6712 | 6865 |
break; |
| 6713 |
case FOP(32, 17):
|
|
| 6866 |
case OPC_CVT_S_D:
|
|
| 6714 | 6867 |
check_cp1_registers(ctx, fs); |
| 6715 | 6868 |
{
|
| 6716 | 6869 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6724 | 6877 |
} |
| 6725 | 6878 |
opn = "cvt.s.d"; |
| 6726 | 6879 |
break; |
| 6727 |
case FOP(36, 17):
|
|
| 6880 |
case OPC_CVT_W_D:
|
|
| 6728 | 6881 |
check_cp1_registers(ctx, fs); |
| 6729 | 6882 |
{
|
| 6730 | 6883 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6738 | 6891 |
} |
| 6739 | 6892 |
opn = "cvt.w.d"; |
| 6740 | 6893 |
break; |
| 6741 |
case FOP(37, 17):
|
|
| 6894 |
case OPC_CVT_L_D:
|
|
| 6742 | 6895 |
check_cp1_64bitmode(ctx); |
| 6743 | 6896 |
{
|
| 6744 | 6897 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6750 | 6903 |
} |
| 6751 | 6904 |
opn = "cvt.l.d"; |
| 6752 | 6905 |
break; |
| 6753 |
case FOP(32, 20):
|
|
| 6906 |
case OPC_CVT_S_W:
|
|
| 6754 | 6907 |
{
|
| 6755 | 6908 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6756 | 6909 |
|
| ... | ... | |
| 6761 | 6914 |
} |
| 6762 | 6915 |
opn = "cvt.s.w"; |
| 6763 | 6916 |
break; |
| 6764 |
case FOP(33, 20):
|
|
| 6917 |
case OPC_CVT_D_W:
|
|
| 6765 | 6918 |
check_cp1_registers(ctx, fd); |
| 6766 | 6919 |
{
|
| 6767 | 6920 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6775 | 6928 |
} |
| 6776 | 6929 |
opn = "cvt.d.w"; |
| 6777 | 6930 |
break; |
| 6778 |
case FOP(32, 21):
|
|
| 6931 |
case OPC_CVT_S_L:
|
|
| 6779 | 6932 |
check_cp1_64bitmode(ctx); |
| 6780 | 6933 |
{
|
| 6781 | 6934 |
TCGv_i32 fp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 6789 | 6942 |
} |
| 6790 | 6943 |
opn = "cvt.s.l"; |
| 6791 | 6944 |
break; |
| 6792 |
case FOP(33, 21):
|
|
| 6945 |
case OPC_CVT_D_L:
|
|
| 6793 | 6946 |
check_cp1_64bitmode(ctx); |
| 6794 | 6947 |
{
|
| 6795 | 6948 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6801 | 6954 |
} |
| 6802 | 6955 |
opn = "cvt.d.l"; |
| 6803 | 6956 |
break; |
| 6804 |
case FOP(38, 20):
|
|
| 6957 |
case OPC_CVT_PS_PW:
|
|
| 6805 | 6958 |
check_cp1_64bitmode(ctx); |
| 6806 | 6959 |
{
|
| 6807 | 6960 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6813 | 6966 |
} |
| 6814 | 6967 |
opn = "cvt.ps.pw"; |
| 6815 | 6968 |
break; |
| 6816 |
case FOP(0, 22):
|
|
| 6969 |
case OPC_ADD_PS:
|
|
| 6817 | 6970 |
check_cp1_64bitmode(ctx); |
| 6818 | 6971 |
{
|
| 6819 | 6972 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6828 | 6981 |
} |
| 6829 | 6982 |
opn = "add.ps"; |
| 6830 | 6983 |
break; |
| 6831 |
case FOP(1, 22):
|
|
| 6984 |
case OPC_SUB_PS:
|
|
| 6832 | 6985 |
check_cp1_64bitmode(ctx); |
| 6833 | 6986 |
{
|
| 6834 | 6987 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6843 | 6996 |
} |
| 6844 | 6997 |
opn = "sub.ps"; |
| 6845 | 6998 |
break; |
| 6846 |
case FOP(2, 22):
|
|
| 6999 |
case OPC_MUL_PS:
|
|
| 6847 | 7000 |
check_cp1_64bitmode(ctx); |
| 6848 | 7001 |
{
|
| 6849 | 7002 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6858 | 7011 |
} |
| 6859 | 7012 |
opn = "mul.ps"; |
| 6860 | 7013 |
break; |
| 6861 |
case FOP(5, 22):
|
|
| 7014 |
case OPC_ABS_PS:
|
|
| 6862 | 7015 |
check_cp1_64bitmode(ctx); |
| 6863 | 7016 |
{
|
| 6864 | 7017 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6870 | 7023 |
} |
| 6871 | 7024 |
opn = "abs.ps"; |
| 6872 | 7025 |
break; |
| 6873 |
case FOP(6, 22):
|
|
| 7026 |
case OPC_MOV_PS:
|
|
| 6874 | 7027 |
check_cp1_64bitmode(ctx); |
| 6875 | 7028 |
{
|
| 6876 | 7029 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6881 | 7034 |
} |
| 6882 | 7035 |
opn = "mov.ps"; |
| 6883 | 7036 |
break; |
| 6884 |
case FOP(7, 22):
|
|
| 7037 |
case OPC_NEG_PS:
|
|
| 6885 | 7038 |
check_cp1_64bitmode(ctx); |
| 6886 | 7039 |
{
|
| 6887 | 7040 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6893 | 7046 |
} |
| 6894 | 7047 |
opn = "neg.ps"; |
| 6895 | 7048 |
break; |
| 6896 |
case FOP(17, 22):
|
|
| 7049 |
case OPC_MOVCF_PS:
|
|
| 6897 | 7050 |
check_cp1_64bitmode(ctx); |
| 6898 | 7051 |
gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
| 6899 | 7052 |
opn = "movcf.ps"; |
| 6900 | 7053 |
break; |
| 6901 |
case FOP(18, 22):
|
|
| 7054 |
case OPC_MOVZ_PS:
|
|
| 6902 | 7055 |
check_cp1_64bitmode(ctx); |
| 6903 | 7056 |
{
|
| 6904 | 7057 |
int l1 = gen_new_label(); |
| ... | ... | |
| 6914 | 7067 |
} |
| 6915 | 7068 |
opn = "movz.ps"; |
| 6916 | 7069 |
break; |
| 6917 |
case FOP(19, 22):
|
|
| 7070 |
case OPC_MOVN_PS:
|
|
| 6918 | 7071 |
check_cp1_64bitmode(ctx); |
| 6919 | 7072 |
{
|
| 6920 | 7073 |
int l1 = gen_new_label(); |
| ... | ... | |
| 6931 | 7084 |
} |
| 6932 | 7085 |
opn = "movn.ps"; |
| 6933 | 7086 |
break; |
| 6934 |
case FOP(24, 22):
|
|
| 7087 |
case OPC_ADDR_PS:
|
|
| 6935 | 7088 |
check_cp1_64bitmode(ctx); |
| 6936 | 7089 |
{
|
| 6937 | 7090 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6946 | 7099 |
} |
| 6947 | 7100 |
opn = "addr.ps"; |
| 6948 | 7101 |
break; |
| 6949 |
case FOP(26, 22):
|
|
| 7102 |
case OPC_MULR_PS:
|
|
| 6950 | 7103 |
check_cp1_64bitmode(ctx); |
| 6951 | 7104 |
{
|
| 6952 | 7105 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6961 | 7114 |
} |
| 6962 | 7115 |
opn = "mulr.ps"; |
| 6963 | 7116 |
break; |
| 6964 |
case FOP(28, 22):
|
|
| 7117 |
case OPC_RECIP2_PS:
|
|
| 6965 | 7118 |
check_cp1_64bitmode(ctx); |
| 6966 | 7119 |
{
|
| 6967 | 7120 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6976 | 7129 |
} |
| 6977 | 7130 |
opn = "recip2.ps"; |
| 6978 | 7131 |
break; |
| 6979 |
case FOP(29, 22):
|
|
| 7132 |
case OPC_RECIP1_PS:
|
|
| 6980 | 7133 |
check_cp1_64bitmode(ctx); |
| 6981 | 7134 |
{
|
| 6982 | 7135 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 6988 | 7141 |
} |
| 6989 | 7142 |
opn = "recip1.ps"; |
| 6990 | 7143 |
break; |
| 6991 |
case FOP(30, 22):
|
|
| 7144 |
case OPC_RSQRT1_PS:
|
|
| 6992 | 7145 |
check_cp1_64bitmode(ctx); |
| 6993 | 7146 |
{
|
| 6994 | 7147 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 7000 | 7153 |
} |
| 7001 | 7154 |
opn = "rsqrt1.ps"; |
| 7002 | 7155 |
break; |
| 7003 |
case FOP(31, 22):
|
|
| 7156 |
case OPC_RSQRT2_PS:
|
|
| 7004 | 7157 |
check_cp1_64bitmode(ctx); |
| 7005 | 7158 |
{
|
| 7006 | 7159 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 7015 | 7168 |
} |
| 7016 | 7169 |
opn = "rsqrt2.ps"; |
| 7017 | 7170 |
break; |
| 7018 |
case FOP(32, 22):
|
|
| 7171 |
case OPC_CVT_S_PU:
|
|
| 7019 | 7172 |
check_cp1_64bitmode(ctx); |
| 7020 | 7173 |
{
|
| 7021 | 7174 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7027 | 7180 |
} |
| 7028 | 7181 |
opn = "cvt.s.pu"; |
| 7029 | 7182 |
break; |
| 7030 |
case FOP(36, 22):
|
|
| 7183 |
case OPC_CVT_PW_PS:
|
|
| 7031 | 7184 |
check_cp1_64bitmode(ctx); |
| 7032 | 7185 |
{
|
| 7033 | 7186 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 7039 | 7192 |
} |
| 7040 | 7193 |
opn = "cvt.pw.ps"; |
| 7041 | 7194 |
break; |
| 7042 |
case FOP(40, 22):
|
|
| 7195 |
case OPC_CVT_S_PL:
|
|
| 7043 | 7196 |
check_cp1_64bitmode(ctx); |
| 7044 | 7197 |
{
|
| 7045 | 7198 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7051 | 7204 |
} |
| 7052 | 7205 |
opn = "cvt.s.pl"; |
| 7053 | 7206 |
break; |
| 7054 |
case FOP(44, 22):
|
|
| 7207 |
case OPC_PLL_PS:
|
|
| 7055 | 7208 |
check_cp1_64bitmode(ctx); |
| 7056 | 7209 |
{
|
| 7057 | 7210 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7066 | 7219 |
} |
| 7067 | 7220 |
opn = "pll.ps"; |
| 7068 | 7221 |
break; |
| 7069 |
case FOP(45, 22):
|
|
| 7222 |
case OPC_PLU_PS:
|
|
| 7070 | 7223 |
check_cp1_64bitmode(ctx); |
| 7071 | 7224 |
{
|
| 7072 | 7225 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7081 | 7234 |
} |
| 7082 | 7235 |
opn = "plu.ps"; |
| 7083 | 7236 |
break; |
| 7084 |
case FOP(46, 22):
|
|
| 7237 |
case OPC_PUL_PS:
|
|
| 7085 | 7238 |
check_cp1_64bitmode(ctx); |
| 7086 | 7239 |
{
|
| 7087 | 7240 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7096 | 7249 |
} |
| 7097 | 7250 |
opn = "pul.ps"; |
| 7098 | 7251 |
break; |
| 7099 |
case FOP(47, 22):
|
|
| 7252 |
case OPC_PUU_PS:
|
|
| 7100 | 7253 |
check_cp1_64bitmode(ctx); |
| 7101 | 7254 |
{
|
| 7102 | 7255 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| ... | ... | |
| 7111 | 7264 |
} |
| 7112 | 7265 |
opn = "puu.ps"; |
| 7113 | 7266 |
break; |
| 7114 |
case FOP(48, 22):
|
|
| 7115 |
case FOP(49, 22):
|
|
| 7116 |
case FOP(50, 22):
|
|
| 7117 |
case FOP(51, 22):
|
|
| 7118 |
case FOP(52, 22):
|
|
| 7119 |
case FOP(53, 22):
|
|
| 7120 |
case FOP(54, 22):
|
|
| 7121 |
case FOP(55, 22):
|
|
| 7122 |
case FOP(56, 22):
|
|
| 7123 |
case FOP(57, 22):
|
|
| 7124 |
case FOP(58, 22):
|
|
| 7125 |
case FOP(59, 22):
|
|
| 7126 |
case FOP(60, 22):
|
|
| 7127 |
case FOP(61, 22):
|
|
| 7128 |
case FOP(62, 22):
|
|
| 7129 |
case FOP(63, 22):
|
|
| 7267 |
case OPC_CMP_F_PS:
|
|
| 7268 |
case OPC_CMP_UN_PS:
|
|
| 7269 |
case OPC_CMP_EQ_PS:
|
|
| 7270 |
case OPC_CMP_UEQ_PS:
|
|
| 7271 |
case OPC_CMP_OLT_PS:
|
|
| 7272 |
case OPC_CMP_ULT_PS:
|
|
| 7273 |
case OPC_CMP_OLE_PS:
|
|
| 7274 |
case OPC_CMP_ULE_PS:
|
|
| 7275 |
case OPC_CMP_SF_PS:
|
|
| 7276 |
case OPC_CMP_NGLE_PS:
|
|
| 7277 |
case OPC_CMP_SEQ_PS:
|
|
| 7278 |
case OPC_CMP_NGL_PS:
|
|
| 7279 |
case OPC_CMP_LT_PS:
|
|
| 7280 |
case OPC_CMP_NGE_PS:
|
|
| 7281 |
case OPC_CMP_LE_PS:
|
|
| 7282 |
case OPC_CMP_NGT_PS:
|
|
| 7130 | 7283 |
check_cp1_64bitmode(ctx); |
| 7131 | 7284 |
{
|
| 7132 | 7285 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 9298 | 9451 |
case OPC_W_FMT: |
| 9299 | 9452 |
case OPC_L_FMT: |
| 9300 | 9453 |
case OPC_PS_FMT: |
| 9301 |
gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
|
|
| 9454 |
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
|
|
| 9302 | 9455 |
(imm >> 8) & 0x7); |
| 9303 | 9456 |
break; |
| 9304 | 9457 |
default: |
Also available in: Unified diff