Statistics
| Branch: | Revision:

root / hw / pc.c @ bf4e5d92

History | View | Annotate | Download (45 kB)

1 80cabfad bellard
/*
2 80cabfad bellard
 * QEMU PC System Emulator
3 5fafdf24 ths
 *
4 80cabfad bellard
 * Copyright (c) 2003-2004 Fabrice Bellard
5 5fafdf24 ths
 *
6 80cabfad bellard
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 80cabfad bellard
 * of this software and associated documentation files (the "Software"), to deal
8 80cabfad bellard
 * in the Software without restriction, including without limitation the rights
9 80cabfad bellard
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 80cabfad bellard
 * copies of the Software, and to permit persons to whom the Software is
11 80cabfad bellard
 * furnished to do so, subject to the following conditions:
12 80cabfad bellard
 *
13 80cabfad bellard
 * The above copyright notice and this permission notice shall be included in
14 80cabfad bellard
 * all copies or substantial portions of the Software.
15 80cabfad bellard
 *
16 80cabfad bellard
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 80cabfad bellard
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 80cabfad bellard
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 80cabfad bellard
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 80cabfad bellard
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 80cabfad bellard
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 80cabfad bellard
 * THE SOFTWARE.
23 80cabfad bellard
 */
24 87ecb68b pbrook
#include "hw.h"
25 87ecb68b pbrook
#include "pc.h"
26 87ecb68b pbrook
#include "fdc.h"
27 87ecb68b pbrook
#include "pci.h"
28 87ecb68b pbrook
#include "block.h"
29 87ecb68b pbrook
#include "sysemu.h"
30 87ecb68b pbrook
#include "audio/audio.h"
31 87ecb68b pbrook
#include "net.h"
32 87ecb68b pbrook
#include "smbus.h"
33 87ecb68b pbrook
#include "boards.h"
34 376253ec aliguori
#include "monitor.h"
35 3cce6243 blueswir1
#include "fw_cfg.h"
36 16b29ae1 aliguori
#include "hpet_emul.h"
37 9dd986cc Richard W.M. Jones
#include "watchdog.h"
38 b6f6e3d3 aliguori
#include "smbios.h"
39 80cabfad bellard
40 b41a2cd1 bellard
/* output Bochs bios info messages */
41 b41a2cd1 bellard
//#define DEBUG_BIOS
42 b41a2cd1 bellard
43 f16408df Alexander Graf
/* Show multiboot debug output */
44 f16408df Alexander Graf
//#define DEBUG_MULTIBOOT
45 f16408df Alexander Graf
46 80cabfad bellard
#define BIOS_FILENAME "bios.bin"
47 80cabfad bellard
#define VGABIOS_FILENAME "vgabios.bin"
48 de9258a8 bellard
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
49 80cabfad bellard
50 7fb4fdcf balrog
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
51 7fb4fdcf balrog
52 a80274c3 pbrook
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
53 a80274c3 pbrook
#define ACPI_DATA_SIZE       0x10000
54 3cce6243 blueswir1
#define BIOS_CFG_IOPORT 0x510
55 8a92ea2f aliguori
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
56 b6f6e3d3 aliguori
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
57 80cabfad bellard
58 e4bcb14c ths
#define MAX_IDE_BUS 2
59 e4bcb14c ths
60 baca51fa bellard
static fdctrl_t *floppy_controller;
61 b0a21b53 bellard
static RTCState *rtc_state;
62 ec844b96 bellard
static PITState *pit;
63 d592d303 bellard
static IOAPICState *ioapic;
64 a5954d5c bellard
static PCIDevice *i440fx_state;
65 80cabfad bellard
66 e28f9884 Glauber Costa
typedef struct rom_reset_data {
67 e28f9884 Glauber Costa
    uint8_t *data;
68 e28f9884 Glauber Costa
    target_phys_addr_t addr;
69 e28f9884 Glauber Costa
    unsigned size;
70 e28f9884 Glauber Costa
} RomResetData;
71 e28f9884 Glauber Costa
72 e28f9884 Glauber Costa
static void option_rom_reset(void *_rrd)
73 e28f9884 Glauber Costa
{
74 e28f9884 Glauber Costa
    RomResetData *rrd = _rrd;
75 e28f9884 Glauber Costa
76 e28f9884 Glauber Costa
    cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
77 e28f9884 Glauber Costa
}
78 e28f9884 Glauber Costa
79 e28f9884 Glauber Costa
static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
80 e28f9884 Glauber Costa
{
81 e28f9884 Glauber Costa
    RomResetData *rrd = qemu_malloc(sizeof *rrd);
82 e28f9884 Glauber Costa
83 e28f9884 Glauber Costa
    rrd->data = qemu_malloc(size);
84 e28f9884 Glauber Costa
    cpu_physical_memory_read(addr, rrd->data, size);
85 e28f9884 Glauber Costa
    rrd->addr = addr;
86 e28f9884 Glauber Costa
    rrd->size = size;
87 a08d4367 Jan Kiszka
    qemu_register_reset(option_rom_reset, rrd);
88 e28f9884 Glauber Costa
}
89 e28f9884 Glauber Costa
90 b41a2cd1 bellard
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
91 80cabfad bellard
{
92 80cabfad bellard
}
93 80cabfad bellard
94 f929aad6 bellard
/* MSDOS compatibility mode FPU exception support */
95 d537cf6c pbrook
static qemu_irq ferr_irq;
96 f929aad6 bellard
/* XXX: add IGNNE support */
97 f929aad6 bellard
void cpu_set_ferr(CPUX86State *s)
98 f929aad6 bellard
{
99 d537cf6c pbrook
    qemu_irq_raise(ferr_irq);
100 f929aad6 bellard
}
101 f929aad6 bellard
102 f929aad6 bellard
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
103 f929aad6 bellard
{
104 d537cf6c pbrook
    qemu_irq_lower(ferr_irq);
105 f929aad6 bellard
}
106 f929aad6 bellard
107 28ab0e2e bellard
/* TSC handling */
108 28ab0e2e bellard
uint64_t cpu_get_tsc(CPUX86State *env)
109 28ab0e2e bellard
{
110 1dce7c3c bellard
    /* Note: when using kqemu, it is more logical to return the host TSC
111 1dce7c3c bellard
       because kqemu does not trap the RDTSC instruction for
112 1dce7c3c bellard
       performance reasons */
113 640f42e4 blueswir1
#ifdef CONFIG_KQEMU
114 1dce7c3c bellard
    if (env->kqemu_enabled) {
115 1dce7c3c bellard
        return cpu_get_real_ticks();
116 5fafdf24 ths
    } else
117 1dce7c3c bellard
#endif
118 1dce7c3c bellard
    {
119 1dce7c3c bellard
        return cpu_get_ticks();
120 1dce7c3c bellard
    }
121 28ab0e2e bellard
}
122 28ab0e2e bellard
123 a5954d5c bellard
/* SMM support */
124 a5954d5c bellard
void cpu_smm_update(CPUState *env)
125 a5954d5c bellard
{
126 a5954d5c bellard
    if (i440fx_state && env == first_cpu)
127 a5954d5c bellard
        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
128 a5954d5c bellard
}
129 a5954d5c bellard
130 a5954d5c bellard
131 3de388f6 bellard
/* IRQ handling */
132 3de388f6 bellard
int cpu_get_pic_interrupt(CPUState *env)
133 3de388f6 bellard
{
134 3de388f6 bellard
    int intno;
135 3de388f6 bellard
136 3de388f6 bellard
    intno = apic_get_interrupt(env);
137 3de388f6 bellard
    if (intno >= 0) {
138 3de388f6 bellard
        /* set irq request if a PIC irq is still pending */
139 3de388f6 bellard
        /* XXX: improve that */
140 5fafdf24 ths
        pic_update_irq(isa_pic);
141 3de388f6 bellard
        return intno;
142 3de388f6 bellard
    }
143 3de388f6 bellard
    /* read the irq from the PIC */
144 0e21e12b ths
    if (!apic_accept_pic_intr(env))
145 0e21e12b ths
        return -1;
146 0e21e12b ths
147 3de388f6 bellard
    intno = pic_read_irq(isa_pic);
148 3de388f6 bellard
    return intno;
149 3de388f6 bellard
}
150 3de388f6 bellard
151 d537cf6c pbrook
static void pic_irq_request(void *opaque, int irq, int level)
152 3de388f6 bellard
{
153 a5b38b51 aurel32
    CPUState *env = first_cpu;
154 a5b38b51 aurel32
155 d5529471 aurel32
    if (env->apic_state) {
156 d5529471 aurel32
        while (env) {
157 d5529471 aurel32
            if (apic_accept_pic_intr(env))
158 1a7de94a aurel32
                apic_deliver_pic_intr(env, level);
159 d5529471 aurel32
            env = env->next_cpu;
160 d5529471 aurel32
        }
161 d5529471 aurel32
    } else {
162 b614106a aurel32
        if (level)
163 b614106a aurel32
            cpu_interrupt(env, CPU_INTERRUPT_HARD);
164 b614106a aurel32
        else
165 b614106a aurel32
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
166 a5b38b51 aurel32
    }
167 3de388f6 bellard
}
168 3de388f6 bellard
169 b0a21b53 bellard
/* PC cmos mappings */
170 b0a21b53 bellard
171 80cabfad bellard
#define REG_EQUIPMENT_BYTE          0x14
172 80cabfad bellard
173 777428f2 bellard
static int cmos_get_fd_drive_type(int fd0)
174 777428f2 bellard
{
175 777428f2 bellard
    int val;
176 777428f2 bellard
177 777428f2 bellard
    switch (fd0) {
178 777428f2 bellard
    case 0:
179 777428f2 bellard
        /* 1.44 Mb 3"5 drive */
180 777428f2 bellard
        val = 4;
181 777428f2 bellard
        break;
182 777428f2 bellard
    case 1:
183 777428f2 bellard
        /* 2.88 Mb 3"5 drive */
184 777428f2 bellard
        val = 5;
185 777428f2 bellard
        break;
186 777428f2 bellard
    case 2:
187 777428f2 bellard
        /* 1.2 Mb 5"5 drive */
188 777428f2 bellard
        val = 2;
189 777428f2 bellard
        break;
190 777428f2 bellard
    default:
191 777428f2 bellard
        val = 0;
192 777428f2 bellard
        break;
193 777428f2 bellard
    }
194 777428f2 bellard
    return val;
195 777428f2 bellard
}
196 777428f2 bellard
197 5fafdf24 ths
static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
198 ba6c2377 bellard
{
199 ba6c2377 bellard
    RTCState *s = rtc_state;
200 ba6c2377 bellard
    int cylinders, heads, sectors;
201 ba6c2377 bellard
    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
202 ba6c2377 bellard
    rtc_set_memory(s, type_ofs, 47);
203 ba6c2377 bellard
    rtc_set_memory(s, info_ofs, cylinders);
204 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
205 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 2, heads);
206 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 3, 0xff);
207 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 4, 0xff);
208 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
209 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 6, cylinders);
210 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
211 ba6c2377 bellard
    rtc_set_memory(s, info_ofs + 8, sectors);
212 ba6c2377 bellard
}
213 ba6c2377 bellard
214 6ac0e82d balrog
/* convert boot_device letter to something recognizable by the bios */
215 6ac0e82d balrog
static int boot_device2nibble(char boot_device)
216 6ac0e82d balrog
{
217 6ac0e82d balrog
    switch(boot_device) {
218 6ac0e82d balrog
    case 'a':
219 6ac0e82d balrog
    case 'b':
220 6ac0e82d balrog
        return 0x01; /* floppy boot */
221 6ac0e82d balrog
    case 'c':
222 6ac0e82d balrog
        return 0x02; /* hard drive boot */
223 6ac0e82d balrog
    case 'd':
224 6ac0e82d balrog
        return 0x03; /* CD-ROM boot */
225 6ac0e82d balrog
    case 'n':
226 6ac0e82d balrog
        return 0x04; /* Network boot */
227 6ac0e82d balrog
    }
228 6ac0e82d balrog
    return 0;
229 6ac0e82d balrog
}
230 6ac0e82d balrog
231 0ecdffbb aurel32
/* copy/pasted from cmos_init, should be made a general function
232 0ecdffbb aurel32
 and used there as well */
233 3b4366de blueswir1
static int pc_boot_set(void *opaque, const char *boot_device)
234 0ecdffbb aurel32
{
235 376253ec aliguori
    Monitor *mon = cur_mon;
236 0ecdffbb aurel32
#define PC_MAX_BOOT_DEVICES 3
237 3b4366de blueswir1
    RTCState *s = (RTCState *)opaque;
238 0ecdffbb aurel32
    int nbds, bds[3] = { 0, };
239 0ecdffbb aurel32
    int i;
240 0ecdffbb aurel32
241 0ecdffbb aurel32
    nbds = strlen(boot_device);
242 0ecdffbb aurel32
    if (nbds > PC_MAX_BOOT_DEVICES) {
243 376253ec aliguori
        monitor_printf(mon, "Too many boot devices for PC\n");
244 0ecdffbb aurel32
        return(1);
245 0ecdffbb aurel32
    }
246 0ecdffbb aurel32
    for (i = 0; i < nbds; i++) {
247 0ecdffbb aurel32
        bds[i] = boot_device2nibble(boot_device[i]);
248 0ecdffbb aurel32
        if (bds[i] == 0) {
249 376253ec aliguori
            monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
250 376253ec aliguori
                           boot_device[i]);
251 0ecdffbb aurel32
            return(1);
252 0ecdffbb aurel32
        }
253 0ecdffbb aurel32
    }
254 0ecdffbb aurel32
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
255 0ecdffbb aurel32
    rtc_set_memory(s, 0x38, (bds[2] << 4));
256 0ecdffbb aurel32
    return(0);
257 0ecdffbb aurel32
}
258 0ecdffbb aurel32
259 ba6c2377 bellard
/* hd_table must contain 4 block drivers */
260 00f82b8a aurel32
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
261 00f82b8a aurel32
                      const char *boot_device, BlockDriverState **hd_table)
262 80cabfad bellard
{
263 b0a21b53 bellard
    RTCState *s = rtc_state;
264 28c5af54 j_mayer
    int nbds, bds[3] = { 0, };
265 80cabfad bellard
    int val;
266 b41a2cd1 bellard
    int fd0, fd1, nb;
267 ba6c2377 bellard
    int i;
268 b0a21b53 bellard
269 b0a21b53 bellard
    /* various important CMOS locations needed by PC/Bochs bios */
270 80cabfad bellard
271 80cabfad bellard
    /* memory size */
272 333190eb bellard
    val = 640; /* base memory in K */
273 333190eb bellard
    rtc_set_memory(s, 0x15, val);
274 333190eb bellard
    rtc_set_memory(s, 0x16, val >> 8);
275 333190eb bellard
276 80cabfad bellard
    val = (ram_size / 1024) - 1024;
277 80cabfad bellard
    if (val > 65535)
278 80cabfad bellard
        val = 65535;
279 b0a21b53 bellard
    rtc_set_memory(s, 0x17, val);
280 b0a21b53 bellard
    rtc_set_memory(s, 0x18, val >> 8);
281 b0a21b53 bellard
    rtc_set_memory(s, 0x30, val);
282 b0a21b53 bellard
    rtc_set_memory(s, 0x31, val >> 8);
283 80cabfad bellard
284 00f82b8a aurel32
    if (above_4g_mem_size) {
285 00f82b8a aurel32
        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
286 00f82b8a aurel32
        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
287 00f82b8a aurel32
        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
288 00f82b8a aurel32
    }
289 00f82b8a aurel32
290 9da98861 bellard
    if (ram_size > (16 * 1024 * 1024))
291 9da98861 bellard
        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
292 9da98861 bellard
    else
293 9da98861 bellard
        val = 0;
294 80cabfad bellard
    if (val > 65535)
295 80cabfad bellard
        val = 65535;
296 b0a21b53 bellard
    rtc_set_memory(s, 0x34, val);
297 b0a21b53 bellard
    rtc_set_memory(s, 0x35, val >> 8);
298 3b46e624 ths
299 298e01b6 aurel32
    /* set the number of CPU */
300 298e01b6 aurel32
    rtc_set_memory(s, 0x5f, smp_cpus - 1);
301 298e01b6 aurel32
302 6ac0e82d balrog
    /* set boot devices, and disable floppy signature check if requested */
303 28c5af54 j_mayer
#define PC_MAX_BOOT_DEVICES 3
304 28c5af54 j_mayer
    nbds = strlen(boot_device);
305 28c5af54 j_mayer
    if (nbds > PC_MAX_BOOT_DEVICES) {
306 28c5af54 j_mayer
        fprintf(stderr, "Too many boot devices for PC\n");
307 28c5af54 j_mayer
        exit(1);
308 28c5af54 j_mayer
    }
309 28c5af54 j_mayer
    for (i = 0; i < nbds; i++) {
310 28c5af54 j_mayer
        bds[i] = boot_device2nibble(boot_device[i]);
311 28c5af54 j_mayer
        if (bds[i] == 0) {
312 28c5af54 j_mayer
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
313 28c5af54 j_mayer
                    boot_device[i]);
314 28c5af54 j_mayer
            exit(1);
315 28c5af54 j_mayer
        }
316 28c5af54 j_mayer
    }
317 28c5af54 j_mayer
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
318 28c5af54 j_mayer
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
319 80cabfad bellard
320 b41a2cd1 bellard
    /* floppy type */
321 b41a2cd1 bellard
322 baca51fa bellard
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
323 baca51fa bellard
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
324 80cabfad bellard
325 777428f2 bellard
    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
326 b0a21b53 bellard
    rtc_set_memory(s, 0x10, val);
327 3b46e624 ths
328 b0a21b53 bellard
    val = 0;
329 b41a2cd1 bellard
    nb = 0;
330 80cabfad bellard
    if (fd0 < 3)
331 80cabfad bellard
        nb++;
332 80cabfad bellard
    if (fd1 < 3)
333 80cabfad bellard
        nb++;
334 80cabfad bellard
    switch (nb) {
335 80cabfad bellard
    case 0:
336 80cabfad bellard
        break;
337 80cabfad bellard
    case 1:
338 b0a21b53 bellard
        val |= 0x01; /* 1 drive, ready for boot */
339 80cabfad bellard
        break;
340 80cabfad bellard
    case 2:
341 b0a21b53 bellard
        val |= 0x41; /* 2 drives, ready for boot */
342 80cabfad bellard
        break;
343 80cabfad bellard
    }
344 b0a21b53 bellard
    val |= 0x02; /* FPU is there */
345 b0a21b53 bellard
    val |= 0x04; /* PS/2 mouse installed */
346 b0a21b53 bellard
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
347 b0a21b53 bellard
348 ba6c2377 bellard
    /* hard drives */
349 ba6c2377 bellard
350 ba6c2377 bellard
    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
351 ba6c2377 bellard
    if (hd_table[0])
352 ba6c2377 bellard
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
353 5fafdf24 ths
    if (hd_table[1])
354 ba6c2377 bellard
        cmos_init_hd(0x1a, 0x24, hd_table[1]);
355 ba6c2377 bellard
356 ba6c2377 bellard
    val = 0;
357 40b6ecc6 bellard
    for (i = 0; i < 4; i++) {
358 ba6c2377 bellard
        if (hd_table[i]) {
359 46d4767d bellard
            int cylinders, heads, sectors, translation;
360 46d4767d bellard
            /* NOTE: bdrv_get_geometry_hint() returns the physical
361 46d4767d bellard
                geometry.  It is always such that: 1 <= sects <= 63, 1
362 46d4767d bellard
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
363 46d4767d bellard
                geometry can be different if a translation is done. */
364 46d4767d bellard
            translation = bdrv_get_translation_hint(hd_table[i]);
365 46d4767d bellard
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
366 46d4767d bellard
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
367 46d4767d bellard
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
368 46d4767d bellard
                    /* No translation. */
369 46d4767d bellard
                    translation = 0;
370 46d4767d bellard
                } else {
371 46d4767d bellard
                    /* LBA translation. */
372 46d4767d bellard
                    translation = 1;
373 46d4767d bellard
                }
374 40b6ecc6 bellard
            } else {
375 46d4767d bellard
                translation--;
376 ba6c2377 bellard
            }
377 ba6c2377 bellard
            val |= translation << (i * 2);
378 ba6c2377 bellard
        }
379 40b6ecc6 bellard
    }
380 ba6c2377 bellard
    rtc_set_memory(s, 0x39, val);
381 80cabfad bellard
}
382 80cabfad bellard
383 59b8ad81 bellard
void ioport_set_a20(int enable)
384 59b8ad81 bellard
{
385 59b8ad81 bellard
    /* XXX: send to all CPUs ? */
386 59b8ad81 bellard
    cpu_x86_set_a20(first_cpu, enable);
387 59b8ad81 bellard
}
388 59b8ad81 bellard
389 59b8ad81 bellard
int ioport_get_a20(void)
390 59b8ad81 bellard
{
391 59b8ad81 bellard
    return ((first_cpu->a20_mask >> 20) & 1);
392 59b8ad81 bellard
}
393 59b8ad81 bellard
394 e1a23744 bellard
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
395 e1a23744 bellard
{
396 59b8ad81 bellard
    ioport_set_a20((val >> 1) & 1);
397 e1a23744 bellard
    /* XXX: bit 0 is fast reset */
398 e1a23744 bellard
}
399 e1a23744 bellard
400 e1a23744 bellard
static uint32_t ioport92_read(void *opaque, uint32_t addr)
401 e1a23744 bellard
{
402 59b8ad81 bellard
    return ioport_get_a20() << 1;
403 e1a23744 bellard
}
404 e1a23744 bellard
405 80cabfad bellard
/***********************************************************/
406 80cabfad bellard
/* Bochs BIOS debug ports */
407 80cabfad bellard
408 9596ebb7 pbrook
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
409 80cabfad bellard
{
410 a2f659ee bellard
    static const char shutdown_str[8] = "Shutdown";
411 a2f659ee bellard
    static int shutdown_index = 0;
412 3b46e624 ths
413 80cabfad bellard
    switch(addr) {
414 80cabfad bellard
        /* Bochs BIOS messages */
415 80cabfad bellard
    case 0x400:
416 80cabfad bellard
    case 0x401:
417 80cabfad bellard
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
418 80cabfad bellard
        exit(1);
419 80cabfad bellard
    case 0x402:
420 80cabfad bellard
    case 0x403:
421 80cabfad bellard
#ifdef DEBUG_BIOS
422 80cabfad bellard
        fprintf(stderr, "%c", val);
423 80cabfad bellard
#endif
424 80cabfad bellard
        break;
425 a2f659ee bellard
    case 0x8900:
426 a2f659ee bellard
        /* same as Bochs power off */
427 a2f659ee bellard
        if (val == shutdown_str[shutdown_index]) {
428 a2f659ee bellard
            shutdown_index++;
429 a2f659ee bellard
            if (shutdown_index == 8) {
430 a2f659ee bellard
                shutdown_index = 0;
431 a2f659ee bellard
                qemu_system_shutdown_request();
432 a2f659ee bellard
            }
433 a2f659ee bellard
        } else {
434 a2f659ee bellard
            shutdown_index = 0;
435 a2f659ee bellard
        }
436 a2f659ee bellard
        break;
437 80cabfad bellard
438 80cabfad bellard
        /* LGPL'ed VGA BIOS messages */
439 80cabfad bellard
    case 0x501:
440 80cabfad bellard
    case 0x502:
441 80cabfad bellard
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
442 80cabfad bellard
        exit(1);
443 80cabfad bellard
    case 0x500:
444 80cabfad bellard
    case 0x503:
445 80cabfad bellard
#ifdef DEBUG_BIOS
446 80cabfad bellard
        fprintf(stderr, "%c", val);
447 80cabfad bellard
#endif
448 80cabfad bellard
        break;
449 80cabfad bellard
    }
450 80cabfad bellard
}
451 80cabfad bellard
452 11c2fd3e aliguori
extern uint64_t node_cpumask[MAX_NODES];
453 11c2fd3e aliguori
454 bf483392 Alexander Graf
static void *bochs_bios_init(void)
455 80cabfad bellard
{
456 3cce6243 blueswir1
    void *fw_cfg;
457 b6f6e3d3 aliguori
    uint8_t *smbios_table;
458 b6f6e3d3 aliguori
    size_t smbios_len;
459 11c2fd3e aliguori
    uint64_t *numa_fw_cfg;
460 11c2fd3e aliguori
    int i, j;
461 3cce6243 blueswir1
462 b41a2cd1 bellard
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
463 b41a2cd1 bellard
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
464 b41a2cd1 bellard
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
465 b41a2cd1 bellard
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
466 a2f659ee bellard
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
467 b41a2cd1 bellard
468 b41a2cd1 bellard
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
469 b41a2cd1 bellard
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
470 b41a2cd1 bellard
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
471 b41a2cd1 bellard
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
472 3cce6243 blueswir1
473 3cce6243 blueswir1
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
474 bf483392 Alexander Graf
475 3cce6243 blueswir1
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
476 905fdcb5 blueswir1
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
477 80deece2 blueswir1
    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
478 80deece2 blueswir1
                     acpi_tables_len);
479 b6f6e3d3 aliguori
480 b6f6e3d3 aliguori
    smbios_table = smbios_get_table(&smbios_len);
481 b6f6e3d3 aliguori
    if (smbios_table)
482 b6f6e3d3 aliguori
        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
483 b6f6e3d3 aliguori
                         smbios_table, smbios_len);
484 11c2fd3e aliguori
485 11c2fd3e aliguori
    /* allocate memory for the NUMA channel: one (64bit) word for the number
486 11c2fd3e aliguori
     * of nodes, one word for each VCPU->node and one word for each node to
487 11c2fd3e aliguori
     * hold the amount of memory.
488 11c2fd3e aliguori
     */
489 11c2fd3e aliguori
    numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
490 11c2fd3e aliguori
    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
491 11c2fd3e aliguori
    for (i = 0; i < smp_cpus; i++) {
492 11c2fd3e aliguori
        for (j = 0; j < nb_numa_nodes; j++) {
493 11c2fd3e aliguori
            if (node_cpumask[j] & (1 << i)) {
494 11c2fd3e aliguori
                numa_fw_cfg[i + 1] = cpu_to_le64(j);
495 11c2fd3e aliguori
                break;
496 11c2fd3e aliguori
            }
497 11c2fd3e aliguori
        }
498 11c2fd3e aliguori
    }
499 11c2fd3e aliguori
    for (i = 0; i < nb_numa_nodes; i++) {
500 11c2fd3e aliguori
        numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
501 11c2fd3e aliguori
    }
502 11c2fd3e aliguori
    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
503 11c2fd3e aliguori
                     (1 + smp_cpus + nb_numa_nodes) * 8);
504 bf483392 Alexander Graf
505 bf483392 Alexander Graf
    return fw_cfg;
506 80cabfad bellard
}
507 80cabfad bellard
508 642a4f96 ths
/* Generate an initial boot sector which sets state and jump to
509 642a4f96 ths
   a specified vector */
510 7ffa4767 pbrook
static void generate_bootsect(target_phys_addr_t option_rom,
511 4fc9af53 aliguori
                              uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
512 642a4f96 ths
{
513 4fc9af53 aliguori
    uint8_t rom[512], *p, *reloc;
514 4fc9af53 aliguori
    uint8_t sum;
515 642a4f96 ths
    int i;
516 642a4f96 ths
517 4fc9af53 aliguori
    memset(rom, 0, sizeof(rom));
518 4fc9af53 aliguori
519 4fc9af53 aliguori
    p = rom;
520 4fc9af53 aliguori
    /* Make sure we have an option rom signature */
521 4fc9af53 aliguori
    *p++ = 0x55;
522 4fc9af53 aliguori
    *p++ = 0xaa;
523 642a4f96 ths
524 4fc9af53 aliguori
    /* ROM size in sectors*/
525 4fc9af53 aliguori
    *p++ = 1;
526 642a4f96 ths
527 4fc9af53 aliguori
    /* Hook int19 */
528 642a4f96 ths
529 4fc9af53 aliguori
    *p++ = 0x50;                /* push ax */
530 4fc9af53 aliguori
    *p++ = 0x1e;                /* push ds */
531 4fc9af53 aliguori
    *p++ = 0x31; *p++ = 0xc0;        /* xor ax, ax */
532 4fc9af53 aliguori
    *p++ = 0x8e; *p++ = 0xd8;        /* mov ax, ds */
533 642a4f96 ths
534 4fc9af53 aliguori
    *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
535 4fc9af53 aliguori
    *p++ = 0x64; *p++ = 0x00;
536 4fc9af53 aliguori
    reloc = p;
537 4fc9af53 aliguori
    *p++ = 0x00; *p++ = 0x00;
538 4fc9af53 aliguori
539 4fc9af53 aliguori
    *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
540 4fc9af53 aliguori
    *p++ = 0x66; *p++ = 0x00;
541 4fc9af53 aliguori
542 4fc9af53 aliguori
    *p++ = 0x1f;                /* pop ds */
543 4fc9af53 aliguori
    *p++ = 0x58;                /* pop ax */
544 4fc9af53 aliguori
    *p++ = 0xcb;                /* lret */
545 4fc9af53 aliguori
    
546 642a4f96 ths
    /* Actual code */
547 4fc9af53 aliguori
    *reloc = (p - rom);
548 4fc9af53 aliguori
549 642a4f96 ths
    *p++ = 0xfa;                /* CLI */
550 642a4f96 ths
    *p++ = 0xfc;                /* CLD */
551 642a4f96 ths
552 642a4f96 ths
    for (i = 0; i < 6; i++) {
553 642a4f96 ths
        if (i == 1)                /* Skip CS */
554 642a4f96 ths
            continue;
555 642a4f96 ths
556 642a4f96 ths
        *p++ = 0xb8;                /* MOV AX,imm16 */
557 642a4f96 ths
        *p++ = segs[i];
558 642a4f96 ths
        *p++ = segs[i] >> 8;
559 642a4f96 ths
        *p++ = 0x8e;                /* MOV <seg>,AX */
560 642a4f96 ths
        *p++ = 0xc0 + (i << 3);
561 642a4f96 ths
    }
562 642a4f96 ths
563 642a4f96 ths
    for (i = 0; i < 8; i++) {
564 642a4f96 ths
        *p++ = 0x66;                /* 32-bit operand size */
565 642a4f96 ths
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
566 642a4f96 ths
        *p++ = gpr[i];
567 642a4f96 ths
        *p++ = gpr[i] >> 8;
568 642a4f96 ths
        *p++ = gpr[i] >> 16;
569 642a4f96 ths
        *p++ = gpr[i] >> 24;
570 642a4f96 ths
    }
571 642a4f96 ths
572 642a4f96 ths
    *p++ = 0xea;                /* JMP FAR */
573 642a4f96 ths
    *p++ = ip;                        /* IP */
574 642a4f96 ths
    *p++ = ip >> 8;
575 642a4f96 ths
    *p++ = segs[1];                /* CS */
576 642a4f96 ths
    *p++ = segs[1] >> 8;
577 642a4f96 ths
578 4fc9af53 aliguori
    /* sign rom */
579 4fc9af53 aliguori
    sum = 0;
580 4fc9af53 aliguori
    for (i = 0; i < (sizeof(rom) - 1); i++)
581 4fc9af53 aliguori
        sum += rom[i];
582 4fc9af53 aliguori
    rom[sizeof(rom) - 1] = -sum;
583 4fc9af53 aliguori
584 7ffa4767 pbrook
    cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
585 d6ecb036 Glauber Costa
    option_rom_setup_reset(option_rom, sizeof (rom));
586 642a4f96 ths
}
587 80cabfad bellard
588 642a4f96 ths
static long get_file_size(FILE *f)
589 642a4f96 ths
{
590 642a4f96 ths
    long where, size;
591 642a4f96 ths
592 642a4f96 ths
    /* XXX: on Unix systems, using fstat() probably makes more sense */
593 642a4f96 ths
594 642a4f96 ths
    where = ftell(f);
595 642a4f96 ths
    fseek(f, 0, SEEK_END);
596 642a4f96 ths
    size = ftell(f);
597 642a4f96 ths
    fseek(f, where, SEEK_SET);
598 642a4f96 ths
599 642a4f96 ths
    return size;
600 642a4f96 ths
}
601 642a4f96 ths
602 f16408df Alexander Graf
#define MULTIBOOT_STRUCT_ADDR 0x9000
603 f16408df Alexander Graf
604 f16408df Alexander Graf
#if MULTIBOOT_STRUCT_ADDR > 0xf0000
605 f16408df Alexander Graf
#error multiboot struct needs to fit in 16 bit real mode
606 f16408df Alexander Graf
#endif
607 f16408df Alexander Graf
608 f16408df Alexander Graf
static int load_multiboot(void *fw_cfg,
609 f16408df Alexander Graf
                          FILE *f,
610 f16408df Alexander Graf
                          const char *kernel_filename,
611 f16408df Alexander Graf
                          const char *initrd_filename,
612 f16408df Alexander Graf
                          const char *kernel_cmdline,
613 f16408df Alexander Graf
                          uint8_t *header)
614 f16408df Alexander Graf
{
615 f16408df Alexander Graf
    int i, t, is_multiboot = 0;
616 f16408df Alexander Graf
    uint32_t flags = 0;
617 f16408df Alexander Graf
    uint32_t mh_entry_addr;
618 f16408df Alexander Graf
    uint32_t mh_load_addr;
619 f16408df Alexander Graf
    uint32_t mb_kernel_size;
620 f16408df Alexander Graf
    uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
621 f16408df Alexander Graf
    uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
622 f16408df Alexander Graf
    uint32_t mb_cmdline = mb_bootinfo + 0x200;
623 f16408df Alexander Graf
    uint32_t mb_mod_end;
624 f16408df Alexander Graf
625 f16408df Alexander Graf
    /* Ok, let's see if it is a multiboot image.
626 f16408df Alexander Graf
       The header is 12x32bit long, so the latest entry may be 8192 - 48. */
627 f16408df Alexander Graf
    for (i = 0; i < (8192 - 48); i += 4) {
628 f16408df Alexander Graf
        if (ldl_p(header+i) == 0x1BADB002) {
629 f16408df Alexander Graf
            uint32_t checksum = ldl_p(header+i+8);
630 f16408df Alexander Graf
            flags = ldl_p(header+i+4);
631 f16408df Alexander Graf
            checksum += flags;
632 f16408df Alexander Graf
            checksum += (uint32_t)0x1BADB002;
633 f16408df Alexander Graf
            if (!checksum) {
634 f16408df Alexander Graf
                is_multiboot = 1;
635 f16408df Alexander Graf
                break;
636 f16408df Alexander Graf
            }
637 f16408df Alexander Graf
        }
638 f16408df Alexander Graf
    }
639 f16408df Alexander Graf
640 f16408df Alexander Graf
    if (!is_multiboot)
641 f16408df Alexander Graf
        return 0; /* no multiboot */
642 f16408df Alexander Graf
643 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
644 f16408df Alexander Graf
    fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
645 f16408df Alexander Graf
#endif
646 f16408df Alexander Graf
647 f16408df Alexander Graf
    if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
648 f16408df Alexander Graf
        fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
649 f16408df Alexander Graf
    }
650 f16408df Alexander Graf
    if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
651 f16408df Alexander Graf
        uint64_t elf_entry;
652 f16408df Alexander Graf
        int kernel_size;
653 f16408df Alexander Graf
        fclose(f);
654 f16408df Alexander Graf
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
655 f16408df Alexander Graf
        if (kernel_size < 0) {
656 f16408df Alexander Graf
            fprintf(stderr, "Error while loading elf kernel\n");
657 f16408df Alexander Graf
            exit(1);
658 f16408df Alexander Graf
        }
659 f16408df Alexander Graf
        mh_load_addr = mh_entry_addr = elf_entry;
660 f16408df Alexander Graf
        mb_kernel_size = kernel_size;
661 f16408df Alexander Graf
662 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
663 f16408df Alexander Graf
        fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
664 f16408df Alexander Graf
                mb_kernel_size, (size_t)mh_entry_addr);
665 f16408df Alexander Graf
#endif
666 f16408df Alexander Graf
    } else {
667 f16408df Alexander Graf
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
668 f16408df Alexander Graf
        uint32_t mh_header_addr = ldl_p(header+i+12);
669 f16408df Alexander Graf
        mh_load_addr = ldl_p(header+i+16);
670 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
671 f16408df Alexander Graf
        uint32_t mh_load_end_addr = ldl_p(header+i+20);
672 f16408df Alexander Graf
        uint32_t mh_bss_end_addr = ldl_p(header+i+24);
673 f16408df Alexander Graf
#endif
674 f16408df Alexander Graf
        uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
675 f16408df Alexander Graf
676 f16408df Alexander Graf
        mh_entry_addr = ldl_p(header+i+28);
677 f16408df Alexander Graf
        mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
678 f16408df Alexander Graf
679 f16408df Alexander Graf
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
680 f16408df Alexander Graf
        uint32_t mh_mode_type = ldl_p(header+i+32);
681 f16408df Alexander Graf
        uint32_t mh_width = ldl_p(header+i+36);
682 f16408df Alexander Graf
        uint32_t mh_height = ldl_p(header+i+40);
683 f16408df Alexander Graf
        uint32_t mh_depth = ldl_p(header+i+44); */
684 f16408df Alexander Graf
685 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
686 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
687 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
688 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
689 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
690 f16408df Alexander Graf
#endif
691 f16408df Alexander Graf
692 f16408df Alexander Graf
        fseek(f, mb_kernel_text_offset, SEEK_SET);
693 f16408df Alexander Graf
694 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
695 f16408df Alexander Graf
        fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
696 f16408df Alexander Graf
                mb_kernel_size, mh_load_addr);
697 f16408df Alexander Graf
#endif
698 f16408df Alexander Graf
699 f16408df Alexander Graf
        if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
700 f16408df Alexander Graf
            fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
701 f16408df Alexander Graf
                    kernel_filename, mb_kernel_size);
702 f16408df Alexander Graf
            exit(1);
703 f16408df Alexander Graf
        }
704 f16408df Alexander Graf
        fclose(f);
705 f16408df Alexander Graf
    }
706 f16408df Alexander Graf
707 f16408df Alexander Graf
    /* blob size is only the kernel for now */
708 f16408df Alexander Graf
    mb_mod_end = mh_load_addr + mb_kernel_size;
709 f16408df Alexander Graf
710 f16408df Alexander Graf
    /* load modules */
711 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */
712 f16408df Alexander Graf
    if (initrd_filename) {
713 f16408df Alexander Graf
        uint32_t mb_mod_info = mb_bootinfo + 0x100;
714 f16408df Alexander Graf
        uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
715 f16408df Alexander Graf
        uint32_t mb_mod_start = mh_load_addr;
716 f16408df Alexander Graf
        uint32_t mb_mod_length = mb_kernel_size;
717 f16408df Alexander Graf
        char *next_initrd;
718 f16408df Alexander Graf
        char *next_space;
719 f16408df Alexander Graf
        int mb_mod_count = 0;
720 f16408df Alexander Graf
721 f16408df Alexander Graf
        do {
722 f16408df Alexander Graf
            next_initrd = strchr(initrd_filename, ',');
723 f16408df Alexander Graf
            if (next_initrd)
724 f16408df Alexander Graf
                *next_initrd = '\0';
725 f16408df Alexander Graf
            /* if a space comes after the module filename, treat everything
726 f16408df Alexander Graf
               after that as parameters */
727 f16408df Alexander Graf
            cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename,
728 f16408df Alexander Graf
                                      strlen(initrd_filename) + 1);
729 f16408df Alexander Graf
            stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */
730 f16408df Alexander Graf
            mb_mod_cmdline += strlen(initrd_filename) + 1;
731 f16408df Alexander Graf
            if ((next_space = strchr(initrd_filename, ' ')))
732 f16408df Alexander Graf
                *next_space = '\0';
733 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
734 f16408df Alexander Graf
             printf("multiboot loading module: %s\n", initrd_filename);
735 f16408df Alexander Graf
#endif
736 f16408df Alexander Graf
            f = fopen(initrd_filename, "rb");
737 f16408df Alexander Graf
            if (f) {
738 f16408df Alexander Graf
                mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
739 f16408df Alexander Graf
                             & (TARGET_PAGE_MASK);
740 f16408df Alexander Graf
                mb_mod_length = get_file_size(f);
741 f16408df Alexander Graf
                mb_mod_end = mb_mod_start + mb_mod_length;
742 f16408df Alexander Graf
743 f16408df Alexander Graf
                if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
744 f16408df Alexander Graf
                    fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
745 f16408df Alexander Graf
                            initrd_filename, mb_mod_length);
746 f16408df Alexander Graf
                    exit(1);
747 f16408df Alexander Graf
                }
748 f16408df Alexander Graf
749 f16408df Alexander Graf
                mb_mod_count++;
750 f16408df Alexander Graf
                stl_phys(mb_mod_info + 0, mb_mod_start);
751 f16408df Alexander Graf
                stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
752 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
753 f16408df Alexander Graf
                printf("mod_start: %#x\nmod_end:   %#x\n", mb_mod_start,
754 f16408df Alexander Graf
                       mb_mod_start + mb_mod_length);
755 f16408df Alexander Graf
#endif
756 f16408df Alexander Graf
                stl_phys(mb_mod_info + 12, 0x0); /* reserved */
757 f16408df Alexander Graf
            }
758 f16408df Alexander Graf
            initrd_filename = next_initrd+1;
759 f16408df Alexander Graf
            mb_mod_info += 16;
760 f16408df Alexander Graf
        } while (next_initrd);
761 f16408df Alexander Graf
        stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */
762 f16408df Alexander Graf
        stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
763 f16408df Alexander Graf
    }
764 f16408df Alexander Graf
765 f16408df Alexander Graf
    /* Make sure we're getting kernel + modules back after reset */
766 f16408df Alexander Graf
    option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr);
767 f16408df Alexander Graf
768 f16408df Alexander Graf
    /* Commandline support */
769 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 16, mb_cmdline);
770 f16408df Alexander Graf
    t = strlen(kernel_filename);
771 f16408df Alexander Graf
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t);
772 f16408df Alexander Graf
    mb_cmdline += t;
773 f16408df Alexander Graf
    stb_phys(mb_cmdline++, ' ');
774 f16408df Alexander Graf
    t = strlen(kernel_cmdline) + 1;
775 f16408df Alexander Graf
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t);
776 f16408df Alexander Graf
777 f16408df Alexander Graf
    /* the kernel is where we want it to be now */
778 f16408df Alexander Graf
779 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
780 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
781 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
782 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MODULES (1 << 3)
783 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MMAP (1 << 6)
784 f16408df Alexander Graf
    stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY
785 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_BOOT_DEVICE
786 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_CMDLINE
787 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_MODULES
788 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_MMAP);
789 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 4, 640); /* mem_lower */
790 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */
791 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
792 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */
793 f16408df Alexander Graf
794 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
795 f16408df Alexander Graf
    fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
796 f16408df Alexander Graf
#endif
797 f16408df Alexander Graf
798 f16408df Alexander Graf
    /* Pass variables to option rom */
799 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr);
800 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
801 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr);
802 f16408df Alexander Graf
803 f16408df Alexander Graf
    /* Make sure we're getting the config space back after reset */
804 f16408df Alexander Graf
    option_rom_setup_reset(mb_bootinfo, 0x500);
805 f16408df Alexander Graf
806 f16408df Alexander Graf
    option_rom[nb_option_roms] = "multiboot.bin";
807 f16408df Alexander Graf
    nb_option_roms++;
808 f16408df Alexander Graf
809 f16408df Alexander Graf
    return 1; /* yes, we are multiboot */
810 f16408df Alexander Graf
}
811 f16408df Alexander Graf
812 f16408df Alexander Graf
static void load_linux(void *fw_cfg,
813 f16408df Alexander Graf
                       target_phys_addr_t option_rom,
814 4fc9af53 aliguori
                       const char *kernel_filename,
815 642a4f96 ths
                       const char *initrd_filename,
816 e6ade764 Glauber Costa
                       const char *kernel_cmdline,
817 e6ade764 Glauber Costa
               target_phys_addr_t max_ram_size)
818 642a4f96 ths
{
819 642a4f96 ths
    uint16_t protocol;
820 642a4f96 ths
    uint32_t gpr[8];
821 642a4f96 ths
    uint16_t seg[6];
822 642a4f96 ths
    uint16_t real_seg;
823 5cea8590 Paul Brook
    int setup_size, kernel_size, initrd_size = 0, cmdline_size;
824 642a4f96 ths
    uint32_t initrd_max;
825 f16408df Alexander Graf
    uint8_t header[8192];
826 5cea8590 Paul Brook
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
827 642a4f96 ths
    FILE *f, *fi;
828 bf4e5d92 Pascal Terjan
    char *vmode;
829 642a4f96 ths
830 642a4f96 ths
    /* Align to 16 bytes as a paranoia measure */
831 642a4f96 ths
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
832 642a4f96 ths
833 642a4f96 ths
    /* load the kernel header */
834 642a4f96 ths
    f = fopen(kernel_filename, "rb");
835 642a4f96 ths
    if (!f || !(kernel_size = get_file_size(f)) ||
836 f16408df Alexander Graf
        fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
837 f16408df Alexander Graf
        MIN(ARRAY_SIZE(header), kernel_size)) {
838 642a4f96 ths
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
839 642a4f96 ths
                kernel_filename);
840 642a4f96 ths
        exit(1);
841 642a4f96 ths
    }
842 642a4f96 ths
843 642a4f96 ths
    /* kernel protocol version */
844 bc4edd79 bellard
#if 0
845 642a4f96 ths
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
846 bc4edd79 bellard
#endif
847 642a4f96 ths
    if (ldl_p(header+0x202) == 0x53726448)
848 642a4f96 ths
        protocol = lduw_p(header+0x206);
849 f16408df Alexander Graf
    else {
850 f16408df Alexander Graf
        /* This looks like a multiboot kernel. If it is, let's stop
851 f16408df Alexander Graf
           treating it like a Linux kernel. */
852 f16408df Alexander Graf
        if (load_multiboot(fw_cfg, f, kernel_filename,
853 f16408df Alexander Graf
                           initrd_filename, kernel_cmdline, header))
854 f16408df Alexander Graf
           return;
855 642a4f96 ths
        protocol = 0;
856 f16408df Alexander Graf
    }
857 642a4f96 ths
858 642a4f96 ths
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
859 642a4f96 ths
        /* Low kernel */
860 a37af289 blueswir1
        real_addr    = 0x90000;
861 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
862 a37af289 blueswir1
        prot_addr    = 0x10000;
863 642a4f96 ths
    } else if (protocol < 0x202) {
864 642a4f96 ths
        /* High but ancient kernel */
865 a37af289 blueswir1
        real_addr    = 0x90000;
866 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
867 a37af289 blueswir1
        prot_addr    = 0x100000;
868 642a4f96 ths
    } else {
869 642a4f96 ths
        /* High and recent kernel */
870 a37af289 blueswir1
        real_addr    = 0x10000;
871 a37af289 blueswir1
        cmdline_addr = 0x20000;
872 a37af289 blueswir1
        prot_addr    = 0x100000;
873 642a4f96 ths
    }
874 642a4f96 ths
875 bc4edd79 bellard
#if 0
876 642a4f96 ths
    fprintf(stderr,
877 526ccb7a balrog
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
878 526ccb7a balrog
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
879 526ccb7a balrog
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
880 a37af289 blueswir1
            real_addr,
881 a37af289 blueswir1
            cmdline_addr,
882 a37af289 blueswir1
            prot_addr);
883 bc4edd79 bellard
#endif
884 642a4f96 ths
885 642a4f96 ths
    /* highest address for loading the initrd */
886 642a4f96 ths
    if (protocol >= 0x203)
887 642a4f96 ths
        initrd_max = ldl_p(header+0x22c);
888 642a4f96 ths
    else
889 642a4f96 ths
        initrd_max = 0x37ffffff;
890 642a4f96 ths
891 e6ade764 Glauber Costa
    if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
892 e6ade764 Glauber Costa
            initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
893 642a4f96 ths
894 642a4f96 ths
    /* kernel command line */
895 a37af289 blueswir1
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
896 642a4f96 ths
897 642a4f96 ths
    if (protocol >= 0x202) {
898 a37af289 blueswir1
        stl_p(header+0x228, cmdline_addr);
899 642a4f96 ths
    } else {
900 642a4f96 ths
        stw_p(header+0x20, 0xA33F);
901 642a4f96 ths
        stw_p(header+0x22, cmdline_addr-real_addr);
902 642a4f96 ths
    }
903 642a4f96 ths
904 bf4e5d92 Pascal Terjan
    /* handle vga= parameter */
905 bf4e5d92 Pascal Terjan
    vmode = strstr(kernel_cmdline, "vga=");
906 bf4e5d92 Pascal Terjan
    if (vmode) {
907 bf4e5d92 Pascal Terjan
        unsigned int video_mode;
908 bf4e5d92 Pascal Terjan
        /* skip "vga=" */
909 bf4e5d92 Pascal Terjan
        vmode += 4;
910 bf4e5d92 Pascal Terjan
        if (!strncmp(vmode, "normal", 6)) {
911 bf4e5d92 Pascal Terjan
            video_mode = 0xffff;
912 bf4e5d92 Pascal Terjan
        } else if (!strncmp(vmode, "ext", 3)) {
913 bf4e5d92 Pascal Terjan
            video_mode = 0xfffe;
914 bf4e5d92 Pascal Terjan
        } else if (!strncmp(vmode, "ask", 3)) {
915 bf4e5d92 Pascal Terjan
            video_mode = 0xfffd;
916 bf4e5d92 Pascal Terjan
        } else {
917 bf4e5d92 Pascal Terjan
            video_mode = strtol(vmode, NULL, 0);
918 bf4e5d92 Pascal Terjan
        }
919 bf4e5d92 Pascal Terjan
        stw_p(header+0x1fa, video_mode);
920 bf4e5d92 Pascal Terjan
    }
921 bf4e5d92 Pascal Terjan
922 642a4f96 ths
    /* loader type */
923 642a4f96 ths
    /* High nybble = B reserved for Qemu; low nybble is revision number.
924 642a4f96 ths
       If this code is substantially changed, you may want to consider
925 642a4f96 ths
       incrementing the revision. */
926 642a4f96 ths
    if (protocol >= 0x200)
927 642a4f96 ths
        header[0x210] = 0xB0;
928 642a4f96 ths
929 642a4f96 ths
    /* heap */
930 642a4f96 ths
    if (protocol >= 0x201) {
931 642a4f96 ths
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
932 642a4f96 ths
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
933 642a4f96 ths
    }
934 642a4f96 ths
935 642a4f96 ths
    /* load initrd */
936 642a4f96 ths
    if (initrd_filename) {
937 642a4f96 ths
        if (protocol < 0x200) {
938 642a4f96 ths
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
939 642a4f96 ths
            exit(1);
940 642a4f96 ths
        }
941 642a4f96 ths
942 642a4f96 ths
        fi = fopen(initrd_filename, "rb");
943 642a4f96 ths
        if (!fi) {
944 642a4f96 ths
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
945 642a4f96 ths
                    initrd_filename);
946 642a4f96 ths
            exit(1);
947 642a4f96 ths
        }
948 642a4f96 ths
949 642a4f96 ths
        initrd_size = get_file_size(fi);
950 a37af289 blueswir1
        initrd_addr = (initrd_max-initrd_size) & ~4095;
951 642a4f96 ths
952 a37af289 blueswir1
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
953 642a4f96 ths
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
954 642a4f96 ths
                    initrd_filename);
955 642a4f96 ths
            exit(1);
956 642a4f96 ths
        }
957 642a4f96 ths
        fclose(fi);
958 642a4f96 ths
959 a37af289 blueswir1
        stl_p(header+0x218, initrd_addr);
960 642a4f96 ths
        stl_p(header+0x21c, initrd_size);
961 642a4f96 ths
    }
962 642a4f96 ths
963 642a4f96 ths
    /* store the finalized header and load the rest of the kernel */
964 f16408df Alexander Graf
    cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header));
965 642a4f96 ths
966 642a4f96 ths
    setup_size = header[0x1f1];
967 642a4f96 ths
    if (setup_size == 0)
968 642a4f96 ths
        setup_size = 4;
969 642a4f96 ths
970 642a4f96 ths
    setup_size = (setup_size+1)*512;
971 f16408df Alexander Graf
    /* Size of protected-mode code */
972 f16408df Alexander Graf
    kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header);
973 f16408df Alexander Graf
974 f16408df Alexander Graf
    /* In case we have read too much already, copy that over */
975 f16408df Alexander Graf
    if (setup_size < ARRAY_SIZE(header)) {
976 f16408df Alexander Graf
        cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size);
977 f16408df Alexander Graf
        prot_addr += (ARRAY_SIZE(header) - setup_size);
978 f16408df Alexander Graf
        setup_size = ARRAY_SIZE(header);
979 f16408df Alexander Graf
    }
980 642a4f96 ths
981 f16408df Alexander Graf
    if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
982 f16408df Alexander Graf
                           setup_size - ARRAY_SIZE(header), f) ||
983 a37af289 blueswir1
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
984 642a4f96 ths
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
985 642a4f96 ths
                kernel_filename);
986 642a4f96 ths
        exit(1);
987 642a4f96 ths
    }
988 642a4f96 ths
    fclose(f);
989 642a4f96 ths
990 642a4f96 ths
    /* generate bootsector to set up the initial register state */
991 a37af289 blueswir1
    real_seg = real_addr >> 4;
992 642a4f96 ths
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
993 642a4f96 ths
    seg[1] = real_seg+0x20;        /* CS */
994 642a4f96 ths
    memset(gpr, 0, sizeof gpr);
995 642a4f96 ths
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
996 642a4f96 ths
997 d6ecb036 Glauber Costa
    option_rom_setup_reset(real_addr, setup_size);
998 d6ecb036 Glauber Costa
    option_rom_setup_reset(prot_addr, kernel_size);
999 d6ecb036 Glauber Costa
    option_rom_setup_reset(cmdline_addr, cmdline_size);
1000 d6ecb036 Glauber Costa
    if (initrd_filename)
1001 d6ecb036 Glauber Costa
        option_rom_setup_reset(initrd_addr, initrd_size);
1002 d6ecb036 Glauber Costa
1003 4fc9af53 aliguori
    generate_bootsect(option_rom, gpr, seg, 0);
1004 642a4f96 ths
}
1005 642a4f96 ths
1006 b41a2cd1 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
1007 b41a2cd1 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
1008 b41a2cd1 bellard
static const int ide_irq[2] = { 14, 15 };
1009 b41a2cd1 bellard
1010 b41a2cd1 bellard
#define NE2000_NB_MAX 6
1011 b41a2cd1 bellard
1012 8d11df9e bellard
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
1013 b41a2cd1 bellard
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1014 b41a2cd1 bellard
1015 8d11df9e bellard
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
1016 8d11df9e bellard
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
1017 8d11df9e bellard
1018 6508fe59 bellard
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
1019 6508fe59 bellard
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1020 6508fe59 bellard
1021 6a36d84e bellard
#ifdef HAS_AUDIO
1022 d537cf6c pbrook
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1023 6a36d84e bellard
{
1024 6a36d84e bellard
    struct soundhw *c;
1025 6a36d84e bellard
1026 3a8bae3e malc
    for (c = soundhw; c->name; ++c) {
1027 3a8bae3e malc
        if (c->enabled) {
1028 3a8bae3e malc
            if (c->isa) {
1029 3a8bae3e malc
                c->init.init_isa(pic);
1030 3a8bae3e malc
            } else {
1031 3a8bae3e malc
                if (pci_bus) {
1032 3a8bae3e malc
                    c->init.init_pci(pci_bus);
1033 6a36d84e bellard
                }
1034 6a36d84e bellard
            }
1035 6a36d84e bellard
        }
1036 6a36d84e bellard
    }
1037 6a36d84e bellard
}
1038 6a36d84e bellard
#endif
1039 6a36d84e bellard
1040 d537cf6c pbrook
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
1041 a41b2ff2 pbrook
{
1042 a41b2ff2 pbrook
    static int nb_ne2k = 0;
1043 a41b2ff2 pbrook
1044 a41b2ff2 pbrook
    if (nb_ne2k == NE2000_NB_MAX)
1045 a41b2ff2 pbrook
        return;
1046 d537cf6c pbrook
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
1047 a41b2ff2 pbrook
    nb_ne2k++;
1048 a41b2ff2 pbrook
}
1049 a41b2ff2 pbrook
1050 f753ff16 pbrook
static int load_option_rom(const char *oprom, target_phys_addr_t start,
1051 f753ff16 pbrook
                           target_phys_addr_t end)
1052 f753ff16 pbrook
{
1053 f753ff16 pbrook
        int size;
1054 5cea8590 Paul Brook
        char *filename;
1055 5cea8590 Paul Brook
1056 5cea8590 Paul Brook
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
1057 5cea8590 Paul Brook
        if (filename) {
1058 5cea8590 Paul Brook
            size = get_image_size(filename);
1059 5cea8590 Paul Brook
            if (size > 0 && start + size > end) {
1060 5cea8590 Paul Brook
                fprintf(stderr, "Not enough space to load option rom '%s'\n",
1061 5cea8590 Paul Brook
                        oprom);
1062 5cea8590 Paul Brook
                exit(1);
1063 5cea8590 Paul Brook
            }
1064 5cea8590 Paul Brook
            size = load_image_targphys(filename, start, end - start);
1065 5cea8590 Paul Brook
            qemu_free(filename);
1066 5cea8590 Paul Brook
        } else {
1067 5cea8590 Paul Brook
            size = -1;
1068 f753ff16 pbrook
        }
1069 f753ff16 pbrook
        if (size < 0) {
1070 f753ff16 pbrook
            fprintf(stderr, "Could not load option rom '%s'\n", oprom);
1071 f753ff16 pbrook
            exit(1);
1072 f753ff16 pbrook
        }
1073 f753ff16 pbrook
        /* Round up optiom rom size to the next 2k boundary */
1074 f753ff16 pbrook
        size = (size + 2047) & ~2047;
1075 e28f9884 Glauber Costa
        option_rom_setup_reset(start, size);
1076 f753ff16 pbrook
        return size;
1077 f753ff16 pbrook
}
1078 f753ff16 pbrook
1079 678e12cc Gleb Natapov
int cpu_is_bsp(CPUState *env)
1080 678e12cc Gleb Natapov
{
1081 678e12cc Gleb Natapov
        return env->cpuid_apic_id == 0;
1082 678e12cc Gleb Natapov
}
1083 678e12cc Gleb Natapov
1084 3a31f36a Jan Kiszka
static CPUState *pc_new_cpu(const char *cpu_model)
1085 3a31f36a Jan Kiszka
{
1086 3a31f36a Jan Kiszka
    CPUState *env;
1087 3a31f36a Jan Kiszka
1088 3a31f36a Jan Kiszka
    env = cpu_init(cpu_model);
1089 3a31f36a Jan Kiszka
    if (!env) {
1090 3a31f36a Jan Kiszka
        fprintf(stderr, "Unable to find x86 CPU definition\n");
1091 3a31f36a Jan Kiszka
        exit(1);
1092 3a31f36a Jan Kiszka
    }
1093 3a31f36a Jan Kiszka
    if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1094 3a31f36a Jan Kiszka
        env->cpuid_apic_id = env->cpu_index;
1095 3a31f36a Jan Kiszka
        /* APIC reset callback resets cpu */
1096 3a31f36a Jan Kiszka
        apic_init(env);
1097 3a31f36a Jan Kiszka
    } else {
1098 3a31f36a Jan Kiszka
        qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1099 3a31f36a Jan Kiszka
    }
1100 3a31f36a Jan Kiszka
    return env;
1101 3a31f36a Jan Kiszka
}
1102 3a31f36a Jan Kiszka
1103 e8b2a1c6 Mark McLoughlin
enum {
1104 e8b2a1c6 Mark McLoughlin
    COMPAT_DEFAULT = 0,
1105 e8b2a1c6 Mark McLoughlin
    COMPAT_0_10, /* compatible with qemu 0.10.x */
1106 e8b2a1c6 Mark McLoughlin
};
1107 e8b2a1c6 Mark McLoughlin
1108 80cabfad bellard
/* PC hardware initialisation */
1109 fbe1b595 Paul Brook
static void pc_init1(ram_addr_t ram_size,
1110 3023f332 aliguori
                     const char *boot_device,
1111 e8b2a1c6 Mark McLoughlin
                     const char *kernel_filename,
1112 e8b2a1c6 Mark McLoughlin
                     const char *kernel_cmdline,
1113 3dbbdc25 bellard
                     const char *initrd_filename,
1114 e8b2a1c6 Mark McLoughlin
                     const char *cpu_model,
1115 e8b2a1c6 Mark McLoughlin
                     int pci_enabled,
1116 e8b2a1c6 Mark McLoughlin
                     int compat_level)
1117 80cabfad bellard
{
1118 5cea8590 Paul Brook
    char *filename;
1119 642a4f96 ths
    int ret, linux_boot, i;
1120 b584726d pbrook
    ram_addr_t ram_addr, bios_offset, option_rom_offset;
1121 00f82b8a aurel32
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1122 f753ff16 pbrook
    int bios_size, isa_bios_size, oprom_area_size;
1123 46e50e9d bellard
    PCIBus *pci_bus;
1124 c2cc47a4 Markus Armbruster
    PCIDevice *pci_dev;
1125 5c3ff3a7 pbrook
    int piix3_devfn = -1;
1126 59b8ad81 bellard
    CPUState *env;
1127 d537cf6c pbrook
    qemu_irq *cpu_irq;
1128 d537cf6c pbrook
    qemu_irq *i8259;
1129 e4bcb14c ths
    int index;
1130 e4bcb14c ths
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1131 e4bcb14c ths
    BlockDriverState *fd[MAX_FD];
1132 34b39c2b aliguori
    int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
1133 bf483392 Alexander Graf
    void *fw_cfg;
1134 e8b2a1c6 Mark McLoughlin
    const char *virtio_blk_name, *virtio_console_name;
1135 d592d303 bellard
1136 00f82b8a aurel32
    if (ram_size >= 0xe0000000 ) {
1137 00f82b8a aurel32
        above_4g_mem_size = ram_size - 0xe0000000;
1138 00f82b8a aurel32
        below_4g_mem_size = 0xe0000000;
1139 00f82b8a aurel32
    } else {
1140 00f82b8a aurel32
        below_4g_mem_size = ram_size;
1141 00f82b8a aurel32
    }
1142 00f82b8a aurel32
1143 80cabfad bellard
    linux_boot = (kernel_filename != NULL);
1144 80cabfad bellard
1145 59b8ad81 bellard
    /* init CPUs */
1146 a049de61 bellard
    if (cpu_model == NULL) {
1147 a049de61 bellard
#ifdef TARGET_X86_64
1148 a049de61 bellard
        cpu_model = "qemu64";
1149 a049de61 bellard
#else
1150 a049de61 bellard
        cpu_model = "qemu32";
1151 a049de61 bellard
#endif
1152 a049de61 bellard
    }
1153 3a31f36a Jan Kiszka
1154 3a31f36a Jan Kiszka
    for (i = 0; i < smp_cpus; i++) {
1155 3a31f36a Jan Kiszka
        env = pc_new_cpu(cpu_model);
1156 59b8ad81 bellard
    }
1157 59b8ad81 bellard
1158 26fb5e48 aurel32
    vmport_init();
1159 26fb5e48 aurel32
1160 80cabfad bellard
    /* allocate RAM */
1161 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0xa0000);
1162 82b36dc3 aliguori
    cpu_register_physical_memory(0, 0xa0000, ram_addr);
1163 82b36dc3 aliguori
1164 82b36dc3 aliguori
    /* Allocate, even though we won't register, so we don't break the
1165 82b36dc3 aliguori
     * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1166 82b36dc3 aliguori
     * and some bios areas, which will be registered later
1167 82b36dc3 aliguori
     */
1168 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1169 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1170 82b36dc3 aliguori
    cpu_register_physical_memory(0x100000,
1171 82b36dc3 aliguori
                 below_4g_mem_size - 0x100000,
1172 82b36dc3 aliguori
                 ram_addr);
1173 00f82b8a aurel32
1174 00f82b8a aurel32
    /* above 4giga memory allocation */
1175 00f82b8a aurel32
    if (above_4g_mem_size > 0) {
1176 8a637d44 Paul Brook
#if TARGET_PHYS_ADDR_BITS == 32
1177 8a637d44 Paul Brook
        hw_error("To much RAM for 32-bit physical address");
1178 8a637d44 Paul Brook
#else
1179 82b36dc3 aliguori
        ram_addr = qemu_ram_alloc(above_4g_mem_size);
1180 82b36dc3 aliguori
        cpu_register_physical_memory(0x100000000ULL,
1181 526ccb7a balrog
                                     above_4g_mem_size,
1182 82b36dc3 aliguori
                                     ram_addr);
1183 8a637d44 Paul Brook
#endif
1184 00f82b8a aurel32
    }
1185 80cabfad bellard
1186 82b36dc3 aliguori
1187 970ac5a3 bellard
    /* BIOS load */
1188 1192dad8 j_mayer
    if (bios_name == NULL)
1189 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
1190 5cea8590 Paul Brook
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1191 5cea8590 Paul Brook
    if (filename) {
1192 5cea8590 Paul Brook
        bios_size = get_image_size(filename);
1193 5cea8590 Paul Brook
    } else {
1194 5cea8590 Paul Brook
        bios_size = -1;
1195 5cea8590 Paul Brook
    }
1196 5fafdf24 ths
    if (bios_size <= 0 ||
1197 970ac5a3 bellard
        (bios_size % 65536) != 0) {
1198 7587cf44 bellard
        goto bios_error;
1199 7587cf44 bellard
    }
1200 970ac5a3 bellard
    bios_offset = qemu_ram_alloc(bios_size);
1201 5cea8590 Paul Brook
    ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
1202 7587cf44 bellard
    if (ret != bios_size) {
1203 7587cf44 bellard
    bios_error:
1204 5cea8590 Paul Brook
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1205 80cabfad bellard
        exit(1);
1206 80cabfad bellard
    }
1207 5cea8590 Paul Brook
    if (filename) {
1208 5cea8590 Paul Brook
        qemu_free(filename);
1209 5cea8590 Paul Brook
    }
1210 7587cf44 bellard
    /* map the last 128KB of the BIOS in ISA space */
1211 7587cf44 bellard
    isa_bios_size = bios_size;
1212 7587cf44 bellard
    if (isa_bios_size > (128 * 1024))
1213 7587cf44 bellard
        isa_bios_size = 128 * 1024;
1214 5fafdf24 ths
    cpu_register_physical_memory(0x100000 - isa_bios_size,
1215 5fafdf24 ths
                                 isa_bios_size,
1216 7587cf44 bellard
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1217 9ae02555 ths
1218 4fc9af53 aliguori
1219 f753ff16 pbrook
1220 f753ff16 pbrook
    option_rom_offset = qemu_ram_alloc(0x20000);
1221 f753ff16 pbrook
    oprom_area_size = 0;
1222 49669fc5 Glauber Costa
    cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
1223 f753ff16 pbrook
1224 f753ff16 pbrook
    if (using_vga) {
1225 5cea8590 Paul Brook
        const char *vgabios_filename;
1226 f753ff16 pbrook
        /* VGA BIOS load */
1227 f753ff16 pbrook
        if (cirrus_vga_enabled) {
1228 5cea8590 Paul Brook
            vgabios_filename = VGABIOS_CIRRUS_FILENAME;
1229 f753ff16 pbrook
        } else {
1230 5cea8590 Paul Brook
            vgabios_filename = VGABIOS_FILENAME;
1231 970ac5a3 bellard
        }
1232 5cea8590 Paul Brook
        oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
1233 f753ff16 pbrook
    }
1234 f753ff16 pbrook
    /* Although video roms can grow larger than 0x8000, the area between
1235 f753ff16 pbrook
     * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
1236 f753ff16 pbrook
     * for any other kind of option rom inside this area */
1237 f753ff16 pbrook
    if (oprom_area_size < 0x8000)
1238 f753ff16 pbrook
        oprom_area_size = 0x8000;
1239 f753ff16 pbrook
1240 1d108d97 Alexander Graf
    /* map all the bios at the top of memory */
1241 1d108d97 Alexander Graf
    cpu_register_physical_memory((uint32_t)(-bios_size),
1242 1d108d97 Alexander Graf
                                 bios_size, bios_offset | IO_MEM_ROM);
1243 1d108d97 Alexander Graf
1244 bf483392 Alexander Graf
    fw_cfg = bochs_bios_init();
1245 1d108d97 Alexander Graf
1246 f753ff16 pbrook
    if (linux_boot) {
1247 f16408df Alexander Graf
        load_linux(fw_cfg, 0xc0000 + oprom_area_size,
1248 e6ade764 Glauber Costa
                   kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1249 f753ff16 pbrook
        oprom_area_size += 2048;
1250 f753ff16 pbrook
    }
1251 f753ff16 pbrook
1252 f753ff16 pbrook
    for (i = 0; i < nb_option_roms; i++) {
1253 406c8df3 Glauber Costa
        oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
1254 406c8df3 Glauber Costa
                                           0xe0000);
1255 406c8df3 Glauber Costa
    }
1256 406c8df3 Glauber Costa
1257 406c8df3 Glauber Costa
    for (i = 0; i < nb_nics; i++) {
1258 406c8df3 Glauber Costa
        char nic_oprom[1024];
1259 406c8df3 Glauber Costa
        const char *model = nd_table[i].model;
1260 406c8df3 Glauber Costa
1261 406c8df3 Glauber Costa
        if (!nd_table[i].bootable)
1262 406c8df3 Glauber Costa
            continue;
1263 406c8df3 Glauber Costa
1264 406c8df3 Glauber Costa
        if (model == NULL)
1265 406c8df3 Glauber Costa
            model = "ne2k_pci";
1266 406c8df3 Glauber Costa
        snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
1267 406c8df3 Glauber Costa
1268 406c8df3 Glauber Costa
        oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
1269 406c8df3 Glauber Costa
                                           0xe0000);
1270 9ae02555 ths
    }
1271 9ae02555 ths
1272 a5b38b51 aurel32
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1273 d537cf6c pbrook
    i8259 = i8259_init(cpu_irq[0]);
1274 d537cf6c pbrook
    ferr_irq = i8259[13];
1275 d537cf6c pbrook
1276 69b91039 bellard
    if (pci_enabled) {
1277 d537cf6c pbrook
        pci_bus = i440fx_init(&i440fx_state, i8259);
1278 8f1c91d8 ths
        piix3_devfn = piix3_init(pci_bus, -1);
1279 46e50e9d bellard
    } else {
1280 46e50e9d bellard
        pci_bus = NULL;
1281 69b91039 bellard
    }
1282 69b91039 bellard
1283 80cabfad bellard
    /* init basic PC hardware */
1284 b41a2cd1 bellard
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1285 80cabfad bellard
1286 f929aad6 bellard
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1287 f929aad6 bellard
1288 1f04275e bellard
    if (cirrus_vga_enabled) {
1289 1f04275e bellard
        if (pci_enabled) {
1290 fbe1b595 Paul Brook
            pci_cirrus_vga_init(pci_bus);
1291 1f04275e bellard
        } else {
1292 fbe1b595 Paul Brook
            isa_cirrus_vga_init();
1293 1f04275e bellard
        }
1294 d34cab9f ths
    } else if (vmsvga_enabled) {
1295 d34cab9f ths
        if (pci_enabled)
1296 fbe1b595 Paul Brook
            pci_vmsvga_init(pci_bus);
1297 d34cab9f ths
        else
1298 d34cab9f ths
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1299 c2b3b41a aliguori
    } else if (std_vga_enabled) {
1300 89b6b508 bellard
        if (pci_enabled) {
1301 fbe1b595 Paul Brook
            pci_vga_init(pci_bus, 0, 0);
1302 89b6b508 bellard
        } else {
1303 fbe1b595 Paul Brook
            isa_vga_init();
1304 89b6b508 bellard
        }
1305 1f04275e bellard
    }
1306 80cabfad bellard
1307 42fc73a1 aurel32
    rtc_state = rtc_init(0x70, i8259[8], 2000);
1308 80cabfad bellard
1309 3b4366de blueswir1
    qemu_register_boot_set(pc_boot_set, rtc_state);
1310 3b4366de blueswir1
1311 e1a23744 bellard
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1312 e1a23744 bellard
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1313 e1a23744 bellard
1314 d592d303 bellard
    if (pci_enabled) {
1315 d592d303 bellard
        ioapic = ioapic_init();
1316 d592d303 bellard
    }
1317 d537cf6c pbrook
    pit = pit_init(0x40, i8259[0]);
1318 fd06c375 bellard
    pcspk_init(pit);
1319 16b29ae1 aliguori
    if (!no_hpet) {
1320 16b29ae1 aliguori
        hpet_init(i8259);
1321 16b29ae1 aliguori
    }
1322 d592d303 bellard
    if (pci_enabled) {
1323 d592d303 bellard
        pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1324 d592d303 bellard
    }
1325 b41a2cd1 bellard
1326 8d11df9e bellard
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1327 8d11df9e bellard
        if (serial_hds[i]) {
1328 b6cd0ea1 aurel32
            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1329 b6cd0ea1 aurel32
                        serial_hds[i]);
1330 8d11df9e bellard
        }
1331 8d11df9e bellard
    }
1332 b41a2cd1 bellard
1333 6508fe59 bellard
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1334 6508fe59 bellard
        if (parallel_hds[i]) {
1335 d537cf6c pbrook
            parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1336 d537cf6c pbrook
                          parallel_hds[i]);
1337 6508fe59 bellard
        }
1338 6508fe59 bellard
    }
1339 6508fe59 bellard
1340 9dd986cc Richard W.M. Jones
    watchdog_pc_init(pci_bus);
1341 9dd986cc Richard W.M. Jones
1342 a41b2ff2 pbrook
    for(i = 0; i < nb_nics; i++) {
1343 cb457d76 aliguori
        NICInfo *nd = &nd_table[i];
1344 cb457d76 aliguori
1345 cb457d76 aliguori
        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1346 d537cf6c pbrook
            pc_init_ne2k_isa(nd, i8259);
1347 cb457d76 aliguori
        else
1348 5607c388 Markus Armbruster
            pci_nic_init(nd, "ne2k_pci", NULL);
1349 a41b2ff2 pbrook
    }
1350 b41a2cd1 bellard
1351 9d5e77a2 Isaku Yamahata
    piix4_acpi_system_hot_add_init();
1352 5e3cb534 aliguori
1353 e4bcb14c ths
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1354 e4bcb14c ths
        fprintf(stderr, "qemu: too many IDE bus\n");
1355 e4bcb14c ths
        exit(1);
1356 e4bcb14c ths
    }
1357 e4bcb14c ths
1358 e4bcb14c ths
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1359 e4bcb14c ths
        index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1360 e4bcb14c ths
        if (index != -1)
1361 e4bcb14c ths
            hd[i] = drives_table[index].bdrv;
1362 e4bcb14c ths
        else
1363 e4bcb14c ths
            hd[i] = NULL;
1364 e4bcb14c ths
    }
1365 e4bcb14c ths
1366 a41b2ff2 pbrook
    if (pci_enabled) {
1367 e4bcb14c ths
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1368 a41b2ff2 pbrook
    } else {
1369 e4bcb14c ths
        for(i = 0; i < MAX_IDE_BUS; i++) {
1370 d537cf6c pbrook
            isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1371 e4bcb14c ths
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1372 69b91039 bellard
        }
1373 b41a2cd1 bellard
    }
1374 69b91039 bellard
1375 d537cf6c pbrook
    i8042_init(i8259[1], i8259[12], 0x60);
1376 7c29d0c0 bellard
    DMA_init(0);
1377 6a36d84e bellard
#ifdef HAS_AUDIO
1378 d537cf6c pbrook
    audio_init(pci_enabled ? pci_bus : NULL, i8259);
1379 fb065187 bellard
#endif
1380 80cabfad bellard
1381 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
1382 e4bcb14c ths
        index = drive_get_index(IF_FLOPPY, 0, i);
1383 e4bcb14c ths
        if (index != -1)
1384 e4bcb14c ths
            fd[i] = drives_table[index].bdrv;
1385 e4bcb14c ths
        else
1386 e4bcb14c ths
            fd[i] = NULL;
1387 e4bcb14c ths
    }
1388 e4bcb14c ths
    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1389 b41a2cd1 bellard
1390 00f82b8a aurel32
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1391 69b91039 bellard
1392 bb36d470 bellard
    if (pci_enabled && usb_enabled) {
1393 afcc3cdf ths
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1394 bb36d470 bellard
    }
1395 bb36d470 bellard
1396 6515b203 bellard
    if (pci_enabled && acpi_enabled) {
1397 3fffc223 ths
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1398 0ff596d0 pbrook
        i2c_bus *smbus;
1399 0ff596d0 pbrook
1400 0ff596d0 pbrook
        /* TODO: Populate SPD eeprom data.  */
1401 cf7a2fe2 aurel32
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1402 3fffc223 ths
        for (i = 0; i < 8; i++) {
1403 1ea96673 Paul Brook
            DeviceState *eeprom;
1404 02e2da45 Paul Brook
            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1405 1ea96673 Paul Brook
            qdev_set_prop_int(eeprom, "address", 0x50 + i);
1406 1ea96673 Paul Brook
            qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
1407 1ea96673 Paul Brook
            qdev_init(eeprom);
1408 3fffc223 ths
        }
1409 6515b203 bellard
    }
1410 3b46e624 ths
1411 a5954d5c bellard
    if (i440fx_state) {
1412 a5954d5c bellard
        i440fx_init_memory_mappings(i440fx_state);
1413 a5954d5c bellard
    }
1414 e4bcb14c ths
1415 7d8406be pbrook
    if (pci_enabled) {
1416 e4bcb14c ths
        int max_bus;
1417 9be5dafe Paul Brook
        int bus;
1418 96d30e48 ths
1419 e4bcb14c ths
        max_bus = drive_get_max_bus(IF_SCSI);
1420 e4bcb14c ths
        for (bus = 0; bus <= max_bus; bus++) {
1421 9be5dafe Paul Brook
            pci_create_simple(pci_bus, -1, "lsi53c895a");
1422 e4bcb14c ths
        }
1423 7d8406be pbrook
    }
1424 6e02c38d aliguori
1425 e8b2a1c6 Mark McLoughlin
    switch (compat_level) {
1426 e8b2a1c6 Mark McLoughlin
    case COMPAT_DEFAULT:
1427 e8b2a1c6 Mark McLoughlin
    default:
1428 e8b2a1c6 Mark McLoughlin
        virtio_blk_name = "virtio-blk-pci";
1429 e8b2a1c6 Mark McLoughlin
        virtio_console_name = "virtio-console-pci";
1430 e8b2a1c6 Mark McLoughlin
        break;
1431 e8b2a1c6 Mark McLoughlin
1432 e8b2a1c6 Mark McLoughlin
    case COMPAT_0_10:
1433 e8b2a1c6 Mark McLoughlin
        virtio_blk_name = "virtio-blk-pci-0-10";
1434 e8b2a1c6 Mark McLoughlin
        virtio_console_name = "virtio-console-pci-0-10";
1435 e8b2a1c6 Mark McLoughlin
        break;
1436 e8b2a1c6 Mark McLoughlin
    }
1437 e8b2a1c6 Mark McLoughlin
1438 6e02c38d aliguori
    /* Add virtio block devices */
1439 6e02c38d aliguori
    if (pci_enabled) {
1440 6e02c38d aliguori
        int index;
1441 6e02c38d aliguori
        int unit_id = 0;
1442 6e02c38d aliguori
1443 6e02c38d aliguori
        while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1444 e8b2a1c6 Mark McLoughlin
            pci_dev = pci_create(virtio_blk_name,
1445 c2cc47a4 Markus Armbruster
                                 drives_table[index].devaddr);
1446 c2cc47a4 Markus Armbruster
            qdev_init(&pci_dev->qdev);
1447 6e02c38d aliguori
            unit_id++;
1448 6e02c38d aliguori
        }
1449 6e02c38d aliguori
    }
1450 bd322087 aliguori
1451 bd322087 aliguori
    /* Add virtio balloon device */
1452 7d4c3d53 Markus Armbruster
    if (pci_enabled && virtio_balloon) {
1453 7d4c3d53 Markus Armbruster
        pci_dev = pci_create("virtio-balloon-pci", virtio_balloon_devaddr);
1454 7d4c3d53 Markus Armbruster
        qdev_init(&pci_dev->qdev);
1455 2d72c572 Paul Brook
    }
1456 a2fa19f9 aliguori
1457 a2fa19f9 aliguori
    /* Add virtio console devices */
1458 a2fa19f9 aliguori
    if (pci_enabled) {
1459 a2fa19f9 aliguori
        for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1460 0e058a8a Paul Brook
            if (virtcon_hds[i]) {
1461 e8b2a1c6 Mark McLoughlin
                pci_create_simple(pci_bus, -1, virtio_console_name);
1462 0e058a8a Paul Brook
            }
1463 a2fa19f9 aliguori
        }
1464 a2fa19f9 aliguori
    }
1465 80cabfad bellard
}
1466 b5ff2d6e bellard
1467 fbe1b595 Paul Brook
static void pc_init_pci(ram_addr_t ram_size,
1468 3023f332 aliguori
                        const char *boot_device,
1469 5fafdf24 ths
                        const char *kernel_filename,
1470 3dbbdc25 bellard
                        const char *kernel_cmdline,
1471 94fc95cd j_mayer
                        const char *initrd_filename,
1472 94fc95cd j_mayer
                        const char *cpu_model)
1473 3dbbdc25 bellard
{
1474 fbe1b595 Paul Brook
    pc_init1(ram_size, boot_device,
1475 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1476 e8b2a1c6 Mark McLoughlin
             initrd_filename, cpu_model,
1477 e8b2a1c6 Mark McLoughlin
             1, COMPAT_DEFAULT);
1478 3dbbdc25 bellard
}
1479 3dbbdc25 bellard
1480 fbe1b595 Paul Brook
static void pc_init_isa(ram_addr_t ram_size,
1481 3023f332 aliguori
                        const char *boot_device,
1482 5fafdf24 ths
                        const char *kernel_filename,
1483 3dbbdc25 bellard
                        const char *kernel_cmdline,
1484 94fc95cd j_mayer
                        const char *initrd_filename,
1485 94fc95cd j_mayer
                        const char *cpu_model)
1486 3dbbdc25 bellard
{
1487 fbe1b595 Paul Brook
    pc_init1(ram_size, boot_device,
1488 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1489 e8b2a1c6 Mark McLoughlin
             initrd_filename, cpu_model,
1490 e8b2a1c6 Mark McLoughlin
             0, COMPAT_DEFAULT);
1491 e8b2a1c6 Mark McLoughlin
}
1492 e8b2a1c6 Mark McLoughlin
1493 e8b2a1c6 Mark McLoughlin
static void pc_init_pci_0_10(ram_addr_t ram_size,
1494 e8b2a1c6 Mark McLoughlin
                             const char *boot_device,
1495 e8b2a1c6 Mark McLoughlin
                             const char *kernel_filename,
1496 e8b2a1c6 Mark McLoughlin
                             const char *kernel_cmdline,
1497 e8b2a1c6 Mark McLoughlin
                             const char *initrd_filename,
1498 e8b2a1c6 Mark McLoughlin
                             const char *cpu_model)
1499 e8b2a1c6 Mark McLoughlin
{
1500 e8b2a1c6 Mark McLoughlin
    pc_init1(ram_size, boot_device,
1501 e8b2a1c6 Mark McLoughlin
             kernel_filename, kernel_cmdline,
1502 e8b2a1c6 Mark McLoughlin
             initrd_filename, cpu_model,
1503 e8b2a1c6 Mark McLoughlin
             1, COMPAT_0_10);
1504 3dbbdc25 bellard
}
1505 3dbbdc25 bellard
1506 0bacd130 aliguori
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1507 0bacd130 aliguori
   BIOS will read it and start S3 resume at POST Entry */
1508 0bacd130 aliguori
void cmos_set_s3_resume(void)
1509 0bacd130 aliguori
{
1510 0bacd130 aliguori
    if (rtc_state)
1511 0bacd130 aliguori
        rtc_set_memory(rtc_state, 0xF, 0xFE);
1512 0bacd130 aliguori
}
1513 0bacd130 aliguori
1514 f80f9ec9 Anthony Liguori
static QEMUMachine pc_machine = {
1515 a245f2e7 aurel32
    .name = "pc",
1516 a245f2e7 aurel32
    .desc = "Standard PC",
1517 a245f2e7 aurel32
    .init = pc_init_pci,
1518 b2097003 aliguori
    .max_cpus = 255,
1519 0c257437 Anthony Liguori
    .is_default = 1,
1520 3dbbdc25 bellard
};
1521 3dbbdc25 bellard
1522 f80f9ec9 Anthony Liguori
static QEMUMachine isapc_machine = {
1523 a245f2e7 aurel32
    .name = "isapc",
1524 a245f2e7 aurel32
    .desc = "ISA-only PC",
1525 a245f2e7 aurel32
    .init = pc_init_isa,
1526 b2097003 aliguori
    .max_cpus = 1,
1527 b5ff2d6e bellard
};
1528 f80f9ec9 Anthony Liguori
1529 e8b2a1c6 Mark McLoughlin
static QEMUMachine pc_0_10_machine = {
1530 e8b2a1c6 Mark McLoughlin
    .name = "pc-0-10",
1531 e8b2a1c6 Mark McLoughlin
    .desc = "Standard PC compatible with qemu 0.10.x",
1532 e8b2a1c6 Mark McLoughlin
    .init = pc_init_pci_0_10,
1533 e8b2a1c6 Mark McLoughlin
    .max_cpus = 255,
1534 e8b2a1c6 Mark McLoughlin
};
1535 e8b2a1c6 Mark McLoughlin
1536 f80f9ec9 Anthony Liguori
static void pc_machine_init(void)
1537 f80f9ec9 Anthony Liguori
{
1538 f80f9ec9 Anthony Liguori
    qemu_register_machine(&pc_machine);
1539 f80f9ec9 Anthony Liguori
    qemu_register_machine(&isapc_machine);
1540 e8b2a1c6 Mark McLoughlin
1541 e8b2a1c6 Mark McLoughlin
    /* For compatibility with 0.10.x */
1542 e8b2a1c6 Mark McLoughlin
    qemu_register_machine(&pc_0_10_machine);
1543 f80f9ec9 Anthony Liguori
}
1544 f80f9ec9 Anthony Liguori
1545 f80f9ec9 Anthony Liguori
machine_init(pc_machine_init);