tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()functions as the ARM architecture allows that, it doesn't make sensefor qemu_ld/st functions. These functions use comparison instructions...
tcg/arm: use ext* ops in qemu_ld
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to bebyte swapped. Two temporary registers are needed for qemu_st to dothe bswap. r0 and r1 are used in system mode, do the same in usermode, which implies reworking the constraints....
tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to theconstraints. Don't check if they equals these registers.
tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specifiedby the "Procedure Call Standard for the ARM Architecture".
tcg/arm: sxtb and sxth are available starting with ARMv6
tcg/arm: use the blx instruction when possible
tcg/arm: add rotation ops
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to asubroutine. According to the "Procedure Call Standard for the ARMArchitecture", it is the job of the callee to save this register.Moreover, this register is already saved in the prologue/epilogue....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Removethem.
tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediatevalues and register number. This makes the code difficult to read.
The patch below replaces all (if I haven't miss any ;-) integer values...
tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".
tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, dependingon the ARM_ARCH_* GCC defines.
tcg/ppc: Remove redundant comparison from brcond2
Signed-off-by: malc <av1474@comtv.ru>
Fix --enable-profiler compilation.
There's a header file inclusion ordering problem between cpu-all.hand qemu-timer.h, such that cpu_get_real_ticks is not defined whenwe attempt to use it in profile_getclock.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: Add missing static qualifier
Build breaks otherwise when USE_LIVENESS_ANALYSIS is not defined.
tcg/ppc: Fix signed versions of brcond2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.
tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilationswithout optimisation, because the compiler makes heavy useof this register (so the resulting code crashes).
Register s0 had been used for TCG_AREG1 in earlier releases,...
tcg/README: improve description of bswap*
tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors. We'd need to emit a call tothe millicode routine $$dyncall. However, this situation doesn'tactually arise, since we always have the descriptor available atTCG code generation time....
tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.Also, improve sub2 to handle some constants the second input low part.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ia64: fix tlb addend read
tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE supportsimilar to ppc64, with the value stored in a register. Add missing...
tcg/ppc64: Fix typo
tcg/ppc: Fix typo
tcg/ppc: Implment bswap16/32
tcg/mips: fix 64-bit linux-user on big endian MIPS
tcg/mips: use seb/seh instructions on MIPS32R2
tcg/ppc: Implement eqv, nand and nor
Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,so needed to be able to hold both host addresses (unsigned long) and guestphysical addresses (target_phys_addr_t). However since the introduction of...
tcg/ppc: Fix not_i32
Thanks to Alexander Graf for bug report and a good reproducible testcase.
tcg/TODO: remove setcond
tcg: initial ia64 support
tcg/mips: fix branch offset during retranslation
Branch offsets should only be overwritten during relocation, to supportpartial retranslation.
tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg-mips: add guest base support
tcg/mips: implement the not_i32 op the same way as gcc
tcg-mips: implement nor
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Allow target-specific implementation of NOR.
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
tcg: Use not_i32 to implement not_i64.
tcg: Change TCGType to an enumeration.
The TCGType name was already used consistently. Changing itto an enumeration instead of a set of defines aids debugging.
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix 64-bit argument ordering
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
tcg/arm: fix load/store definitions for 32-bit targets
tcg: protect div2 in tcg/tcg-opc.h
tcg: declare internal helpers as const and pure
TCG internal helpers only access to the values passed in arguments, anddo not modify the CPU internal state. Thus they can be declared asconst and pure.
tcg/arm: use helpers for divu/remu
tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers fordiv/rem/divu/remu.
Create a #define for div2 so that targets can select betweendiv, div2 and helper implementation. Use the helper version if noneof the #define are present....
Fix build with -DNDEBUG in CFLAGS
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/arm: implement andc op
tcg: update README with const and pure helpers
tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crasheson ARM hosts. This is not a bug of this commit, but a latent bugrevealed by this commit.
The TCG code is called through a procedure call using the prologue...
Fix Sparc host build breakage
Fix error: CC sparc-bsd-user/op_helper.oIn file included from /src/qemu/tcg/tcg.c:158:/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined
tcg/ppc64: Only define addend load helpers in softmmu case
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg/arm: merge the two sets of #define for optional ops
tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add a missing break
tcg/arm: implement setcond2
tcg/arm: implement setcond
tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skippedvalues.
tcg/ppc: Fix right rotation
tcg/ppc64: Use C90 style comments
tcg/ppc: Implement some of the optional ops
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg: fix assertion with --enable-debug
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix thefollowing assertion failure:
qemu-alpha: tcg/tcg.c:1055:tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.
Signed-off-by: Jay Foad <jay.foad@gmail.com>...
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement ORC.
tcg-sparc: Implement ANDC.
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg-sparc: Implement not.
The fallback implementation of "ret = arg1 ^ -1" isn't idealbecause of the extra tcg op to load the minus one.
tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,first because of the extra tcg op to load the zero, and secondbecause we fail to handle zero as %g0 for arg1 of the sub.
tcg/ppc: Consistently use calling convention selection macros
Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}.
New version after malc's comments. (This avoids having to do #if defined linux || defined FreeBSD || defined FreeBSD_kernelfor the third case.)...
tcg: Add consistency checks for op definitions
When compiled with CONFIG_DEBUG_TCG, this code looksfor missing, duplicate and wrong entries in theop definitions.
Errors will raise an assertion at program start(all checks are done in the initial phase)....
tcg-sparc: Implement setcond, setcond2.
tcg: Add tcg_swap_cond.
Returns the condition as if with swapped comparison operands.
tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fastpath is taken, which leads to a crash. Fix that by using the a0 registerinstead.
tcg/mips: implement setcond2
tcg/mips: implement setcond
tcg: move setcond* ops to non-optional section
setcond is not an optional op, move it to the non-optional section.
tcg: add setcondi pseudo-op
tcg/ppc64: implement setcond
tcg/ppc32: proper setcond implementation
tcg/ppc32: implement setcond2
tcg-i386: Implement setcond.
tcg-i386: Implement small forward branches.
There are places, like brcond2, where we know that the destinationof a forward branch will be within 127 bytes.
Add the R_386_PC8 relocation type to support this. Add a flag totcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the...
tcg: add tcg_invert_cond
It is very handy to have a reliable mapping of a condition to its inverse.
tcg-x86_64: implement setcond