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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * OMAP clocks.
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3 | c3d2689d | balrog | *
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4 | 827df9f3 | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
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7 | c3d2689d | balrog | *
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8 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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9 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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10 | c3d2689d | balrog | * published by the Free Software Foundation; either version 2 of
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11 | c3d2689d | balrog | * the License, or (at your option) any later version.
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12 | c3d2689d | balrog | *
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13 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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14 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | c3d2689d | balrog | * GNU General Public License for more details.
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17 | c3d2689d | balrog | *
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18 | c3d2689d | balrog | * You should have received a copy of the GNU General Public License
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19 | c3d2689d | balrog | * along with this program; if not, write to the Free Software
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20 | c3d2689d | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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21 | c3d2689d | balrog | * MA 02111-1307 USA
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22 | c3d2689d | balrog | */
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23 | 87ecb68b | pbrook | #include "hw.h" |
24 | 87ecb68b | pbrook | #include "omap.h" |
25 | c3d2689d | balrog | |
26 | c3d2689d | balrog | struct clk {
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27 | c3d2689d | balrog | const char *name; |
28 | c3d2689d | balrog | const char *alias; |
29 | c3d2689d | balrog | struct clk *parent;
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30 | c3d2689d | balrog | struct clk *child1;
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31 | c3d2689d | balrog | struct clk *sibling;
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32 | c3d2689d | balrog | #define ALWAYS_ENABLED (1 << 0) |
33 | c3d2689d | balrog | #define CLOCK_IN_OMAP310 (1 << 10) |
34 | c3d2689d | balrog | #define CLOCK_IN_OMAP730 (1 << 11) |
35 | c3d2689d | balrog | #define CLOCK_IN_OMAP1510 (1 << 12) |
36 | c3d2689d | balrog | #define CLOCK_IN_OMAP16XX (1 << 13) |
37 | 827df9f3 | balrog | #define CLOCK_IN_OMAP242X (1 << 14) |
38 | 827df9f3 | balrog | #define CLOCK_IN_OMAP243X (1 << 15) |
39 | 827df9f3 | balrog | #define CLOCK_IN_OMAP343X (1 << 16) |
40 | c3d2689d | balrog | uint32_t flags; |
41 | c3d2689d | balrog | int id;
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42 | c3d2689d | balrog | |
43 | c3d2689d | balrog | int running; /* Is currently ticking */ |
44 | c3d2689d | balrog | int enabled; /* Is enabled, regardless of its input clk */ |
45 | c3d2689d | balrog | unsigned long rate; /* Current rate (if .running) */ |
46 | c3d2689d | balrog | unsigned int divisor; /* Rate relative to input (if .enabled) */ |
47 | c3d2689d | balrog | unsigned int multiplier; /* Rate relative to input (if .enabled) */ |
48 | c3d2689d | balrog | qemu_irq users[16]; /* Who to notify on change */ |
49 | c3d2689d | balrog | int usecount; /* Automatically idle when unused */ |
50 | c3d2689d | balrog | }; |
51 | c3d2689d | balrog | |
52 | c3d2689d | balrog | static struct clk xtal_osc12m = { |
53 | c3d2689d | balrog | .name = "xtal_osc_12m",
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54 | c3d2689d | balrog | .rate = 12000000,
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55 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
56 | c3d2689d | balrog | }; |
57 | c3d2689d | balrog | |
58 | c3d2689d | balrog | static struct clk xtal_osc32k = { |
59 | c3d2689d | balrog | .name = "xtal_osc_32k",
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60 | c3d2689d | balrog | .rate = 32768,
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61 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
62 | 827df9f3 | balrog | CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
63 | c3d2689d | balrog | }; |
64 | c3d2689d | balrog | |
65 | c3d2689d | balrog | static struct clk ck_ref = { |
66 | c3d2689d | balrog | .name = "ck_ref",
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67 | c3d2689d | balrog | .alias = "clkin",
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68 | c3d2689d | balrog | .parent = &xtal_osc12m, |
69 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
70 | c3d2689d | balrog | ALWAYS_ENABLED, |
71 | c3d2689d | balrog | }; |
72 | c3d2689d | balrog | |
73 | c3d2689d | balrog | /* If a dpll is disabled it becomes a bypass, child clocks don't stop */
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74 | c3d2689d | balrog | static struct clk dpll1 = { |
75 | c3d2689d | balrog | .name = "dpll1",
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76 | c3d2689d | balrog | .parent = &ck_ref, |
77 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
78 | c3d2689d | balrog | ALWAYS_ENABLED, |
79 | c3d2689d | balrog | }; |
80 | c3d2689d | balrog | |
81 | c3d2689d | balrog | static struct clk dpll2 = { |
82 | c3d2689d | balrog | .name = "dpll2",
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83 | c3d2689d | balrog | .parent = &ck_ref, |
84 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
85 | c3d2689d | balrog | }; |
86 | c3d2689d | balrog | |
87 | c3d2689d | balrog | static struct clk dpll3 = { |
88 | c3d2689d | balrog | .name = "dpll3",
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89 | c3d2689d | balrog | .parent = &ck_ref, |
90 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
91 | c3d2689d | balrog | }; |
92 | c3d2689d | balrog | |
93 | c3d2689d | balrog | static struct clk dpll4 = { |
94 | c3d2689d | balrog | .name = "dpll4",
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95 | c3d2689d | balrog | .parent = &ck_ref, |
96 | c3d2689d | balrog | .multiplier = 4,
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97 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
98 | c3d2689d | balrog | }; |
99 | c3d2689d | balrog | |
100 | c3d2689d | balrog | static struct clk apll = { |
101 | c3d2689d | balrog | .name = "apll",
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102 | c3d2689d | balrog | .parent = &ck_ref, |
103 | c3d2689d | balrog | .multiplier = 48,
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104 | c3d2689d | balrog | .divisor = 12,
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105 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
106 | c3d2689d | balrog | }; |
107 | c3d2689d | balrog | |
108 | c3d2689d | balrog | static struct clk ck_48m = { |
109 | c3d2689d | balrog | .name = "ck_48m",
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110 | c3d2689d | balrog | .parent = &dpll4, /* either dpll4 or apll */
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111 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
112 | c3d2689d | balrog | }; |
113 | c3d2689d | balrog | |
114 | c3d2689d | balrog | static struct clk ck_dpll1out = { |
115 | c3d2689d | balrog | .name = "ck_dpll1out",
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116 | c3d2689d | balrog | .parent = &dpll1, |
117 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
118 | c3d2689d | balrog | }; |
119 | c3d2689d | balrog | |
120 | c3d2689d | balrog | static struct clk sossi_ck = { |
121 | c3d2689d | balrog | .name = "ck_sossi",
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122 | c3d2689d | balrog | .parent = &ck_dpll1out, |
123 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
124 | c3d2689d | balrog | }; |
125 | c3d2689d | balrog | |
126 | c3d2689d | balrog | static struct clk clkm1 = { |
127 | c3d2689d | balrog | .name = "clkm1",
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128 | c3d2689d | balrog | .alias = "ck_gen1",
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129 | c3d2689d | balrog | .parent = &dpll1, |
130 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
131 | c3d2689d | balrog | ALWAYS_ENABLED, |
132 | c3d2689d | balrog | }; |
133 | c3d2689d | balrog | |
134 | c3d2689d | balrog | static struct clk clkm2 = { |
135 | c3d2689d | balrog | .name = "clkm2",
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136 | c3d2689d | balrog | .alias = "ck_gen2",
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137 | c3d2689d | balrog | .parent = &dpll1, |
138 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
139 | c3d2689d | balrog | ALWAYS_ENABLED, |
140 | c3d2689d | balrog | }; |
141 | c3d2689d | balrog | |
142 | c3d2689d | balrog | static struct clk clkm3 = { |
143 | c3d2689d | balrog | .name = "clkm3",
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144 | c3d2689d | balrog | .alias = "ck_gen3",
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145 | c3d2689d | balrog | .parent = &dpll1, /* either dpll1 or ck_ref */
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146 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
147 | c3d2689d | balrog | ALWAYS_ENABLED, |
148 | c3d2689d | balrog | }; |
149 | c3d2689d | balrog | |
150 | c3d2689d | balrog | static struct clk arm_ck = { |
151 | c3d2689d | balrog | .name = "arm_ck",
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152 | c3d2689d | balrog | .alias = "mpu_ck",
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153 | c3d2689d | balrog | .parent = &clkm1, |
154 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
155 | c3d2689d | balrog | ALWAYS_ENABLED, |
156 | c3d2689d | balrog | }; |
157 | c3d2689d | balrog | |
158 | c3d2689d | balrog | static struct clk armper_ck = { |
159 | c3d2689d | balrog | .name = "armper_ck",
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160 | c3d2689d | balrog | .alias = "mpuper_ck",
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161 | c3d2689d | balrog | .parent = &clkm1, |
162 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
163 | c3d2689d | balrog | }; |
164 | c3d2689d | balrog | |
165 | c3d2689d | balrog | static struct clk arm_gpio_ck = { |
166 | c3d2689d | balrog | .name = "arm_gpio_ck",
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167 | c3d2689d | balrog | .alias = "mpu_gpio_ck",
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168 | c3d2689d | balrog | .parent = &clkm1, |
169 | c3d2689d | balrog | .divisor = 1,
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170 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
171 | c3d2689d | balrog | }; |
172 | c3d2689d | balrog | |
173 | c3d2689d | balrog | static struct clk armxor_ck = { |
174 | c3d2689d | balrog | .name = "armxor_ck",
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175 | c3d2689d | balrog | .alias = "mpuxor_ck",
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176 | c3d2689d | balrog | .parent = &ck_ref, |
177 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
178 | c3d2689d | balrog | }; |
179 | c3d2689d | balrog | |
180 | c3d2689d | balrog | static struct clk armtim_ck = { |
181 | c3d2689d | balrog | .name = "armtim_ck",
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182 | c3d2689d | balrog | .alias = "mputim_ck",
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183 | c3d2689d | balrog | .parent = &ck_ref, /* either CLKIN or DPLL1 */
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184 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
185 | c3d2689d | balrog | }; |
186 | c3d2689d | balrog | |
187 | c3d2689d | balrog | static struct clk armwdt_ck = { |
188 | c3d2689d | balrog | .name = "armwdt_ck",
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189 | c3d2689d | balrog | .alias = "mpuwd_ck",
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190 | c3d2689d | balrog | .parent = &clkm1, |
191 | c3d2689d | balrog | .divisor = 14,
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192 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
193 | c3d2689d | balrog | ALWAYS_ENABLED, |
194 | c3d2689d | balrog | }; |
195 | c3d2689d | balrog | |
196 | c3d2689d | balrog | static struct clk arminth_ck16xx = { |
197 | c3d2689d | balrog | .name = "arminth_ck",
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198 | c3d2689d | balrog | .parent = &arm_ck, |
199 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
200 | c3d2689d | balrog | /* Note: On 16xx the frequency can be divided by 2 by programming
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201 | c3d2689d | balrog | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
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202 | c3d2689d | balrog | *
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203 | c3d2689d | balrog | * 1510 version is in TC clocks.
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204 | c3d2689d | balrog | */
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205 | c3d2689d | balrog | }; |
206 | c3d2689d | balrog | |
207 | c3d2689d | balrog | static struct clk dsp_ck = { |
208 | c3d2689d | balrog | .name = "dsp_ck",
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209 | c3d2689d | balrog | .parent = &clkm2, |
210 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
211 | c3d2689d | balrog | }; |
212 | c3d2689d | balrog | |
213 | c3d2689d | balrog | static struct clk dspmmu_ck = { |
214 | c3d2689d | balrog | .name = "dspmmu_ck",
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215 | c3d2689d | balrog | .parent = &clkm2, |
216 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
217 | c3d2689d | balrog | ALWAYS_ENABLED, |
218 | c3d2689d | balrog | }; |
219 | c3d2689d | balrog | |
220 | c3d2689d | balrog | static struct clk dspper_ck = { |
221 | c3d2689d | balrog | .name = "dspper_ck",
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222 | c3d2689d | balrog | .parent = &clkm2, |
223 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
224 | c3d2689d | balrog | }; |
225 | c3d2689d | balrog | |
226 | c3d2689d | balrog | static struct clk dspxor_ck = { |
227 | c3d2689d | balrog | .name = "dspxor_ck",
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228 | c3d2689d | balrog | .parent = &ck_ref, |
229 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
230 | c3d2689d | balrog | }; |
231 | c3d2689d | balrog | |
232 | c3d2689d | balrog | static struct clk dsptim_ck = { |
233 | c3d2689d | balrog | .name = "dsptim_ck",
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234 | c3d2689d | balrog | .parent = &ck_ref, |
235 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
236 | c3d2689d | balrog | }; |
237 | c3d2689d | balrog | |
238 | c3d2689d | balrog | static struct clk tc_ck = { |
239 | c3d2689d | balrog | .name = "tc_ck",
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240 | c3d2689d | balrog | .parent = &clkm3, |
241 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
242 | c3d2689d | balrog | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | |
243 | c3d2689d | balrog | ALWAYS_ENABLED, |
244 | c3d2689d | balrog | }; |
245 | c3d2689d | balrog | |
246 | c3d2689d | balrog | static struct clk arminth_ck15xx = { |
247 | c3d2689d | balrog | .name = "arminth_ck",
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248 | c3d2689d | balrog | .parent = &tc_ck, |
249 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
250 | c3d2689d | balrog | /* Note: On 1510 the frequency follows TC_CK
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251 | c3d2689d | balrog | *
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252 | c3d2689d | balrog | * 16xx version is in MPU clocks.
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253 | c3d2689d | balrog | */
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254 | c3d2689d | balrog | }; |
255 | c3d2689d | balrog | |
256 | c3d2689d | balrog | static struct clk tipb_ck = { |
257 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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258 | c3d2689d | balrog | .name = "tipb_ck",
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259 | c3d2689d | balrog | .parent = &tc_ck, |
260 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
261 | c3d2689d | balrog | }; |
262 | c3d2689d | balrog | |
263 | c3d2689d | balrog | static struct clk l3_ocpi_ck = { |
264 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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265 | c3d2689d | balrog | .name = "l3_ocpi_ck",
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266 | c3d2689d | balrog | .parent = &tc_ck, |
267 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
268 | c3d2689d | balrog | }; |
269 | c3d2689d | balrog | |
270 | c3d2689d | balrog | static struct clk tc1_ck = { |
271 | c3d2689d | balrog | .name = "tc1_ck",
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272 | c3d2689d | balrog | .parent = &tc_ck, |
273 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
274 | c3d2689d | balrog | }; |
275 | c3d2689d | balrog | |
276 | c3d2689d | balrog | static struct clk tc2_ck = { |
277 | c3d2689d | balrog | .name = "tc2_ck",
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278 | c3d2689d | balrog | .parent = &tc_ck, |
279 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
280 | c3d2689d | balrog | }; |
281 | c3d2689d | balrog | |
282 | c3d2689d | balrog | static struct clk dma_ck = { |
283 | c3d2689d | balrog | /* No-idle controlled by "tc_ck" */
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284 | c3d2689d | balrog | .name = "dma_ck",
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285 | c3d2689d | balrog | .parent = &tc_ck, |
286 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
287 | c3d2689d | balrog | ALWAYS_ENABLED, |
288 | c3d2689d | balrog | }; |
289 | c3d2689d | balrog | |
290 | c3d2689d | balrog | static struct clk dma_lcdfree_ck = { |
291 | c3d2689d | balrog | .name = "dma_lcdfree_ck",
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292 | c3d2689d | balrog | .parent = &tc_ck, |
293 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
294 | c3d2689d | balrog | }; |
295 | c3d2689d | balrog | |
296 | c3d2689d | balrog | static struct clk api_ck = { |
297 | c3d2689d | balrog | .name = "api_ck",
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298 | c3d2689d | balrog | .alias = "mpui_ck",
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299 | c3d2689d | balrog | .parent = &tc_ck, |
300 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
301 | c3d2689d | balrog | }; |
302 | c3d2689d | balrog | |
303 | c3d2689d | balrog | static struct clk lb_ck = { |
304 | c3d2689d | balrog | .name = "lb_ck",
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305 | c3d2689d | balrog | .parent = &tc_ck, |
306 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
307 | c3d2689d | balrog | }; |
308 | c3d2689d | balrog | |
309 | c3d2689d | balrog | static struct clk lbfree_ck = { |
310 | c3d2689d | balrog | .name = "lbfree_ck",
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311 | c3d2689d | balrog | .parent = &tc_ck, |
312 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
313 | c3d2689d | balrog | }; |
314 | c3d2689d | balrog | |
315 | d8f699cb | balrog | static struct clk hsab_ck = { |
316 | d8f699cb | balrog | .name = "hsab_ck",
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317 | d8f699cb | balrog | .parent = &tc_ck, |
318 | d8f699cb | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
319 | d8f699cb | balrog | }; |
320 | d8f699cb | balrog | |
321 | c3d2689d | balrog | static struct clk rhea1_ck = { |
322 | c3d2689d | balrog | .name = "rhea1_ck",
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323 | c3d2689d | balrog | .parent = &tc_ck, |
324 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
325 | c3d2689d | balrog | }; |
326 | c3d2689d | balrog | |
327 | c3d2689d | balrog | static struct clk rhea2_ck = { |
328 | c3d2689d | balrog | .name = "rhea2_ck",
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329 | c3d2689d | balrog | .parent = &tc_ck, |
330 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
331 | c3d2689d | balrog | }; |
332 | c3d2689d | balrog | |
333 | c3d2689d | balrog | static struct clk lcd_ck_16xx = { |
334 | c3d2689d | balrog | .name = "lcd_ck",
|
335 | c3d2689d | balrog | .parent = &clkm3, |
336 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, |
337 | c3d2689d | balrog | }; |
338 | c3d2689d | balrog | |
339 | c3d2689d | balrog | static struct clk lcd_ck_1510 = { |
340 | c3d2689d | balrog | .name = "lcd_ck",
|
341 | c3d2689d | balrog | .parent = &clkm3, |
342 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
343 | c3d2689d | balrog | }; |
344 | c3d2689d | balrog | |
345 | c3d2689d | balrog | static struct clk uart1_1510 = { |
346 | c3d2689d | balrog | .name = "uart1_ck",
|
347 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
348 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
349 | c3d2689d | balrog | .rate = 12000000,
|
350 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
351 | c3d2689d | balrog | }; |
352 | c3d2689d | balrog | |
353 | c3d2689d | balrog | static struct clk uart1_16xx = { |
354 | c3d2689d | balrog | .name = "uart1_ck",
|
355 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
356 | c3d2689d | balrog | .parent = &armper_ck, |
357 | c3d2689d | balrog | .rate = 48000000,
|
358 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
359 | c3d2689d | balrog | }; |
360 | c3d2689d | balrog | |
361 | c3d2689d | balrog | static struct clk uart2_ck = { |
362 | c3d2689d | balrog | .name = "uart2_ck",
|
363 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
364 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
365 | c3d2689d | balrog | .rate = 12000000,
|
366 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
367 | c3d2689d | balrog | ALWAYS_ENABLED, |
368 | c3d2689d | balrog | }; |
369 | c3d2689d | balrog | |
370 | c3d2689d | balrog | static struct clk uart3_1510 = { |
371 | c3d2689d | balrog | .name = "uart3_ck",
|
372 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
373 | d8f699cb | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
374 | c3d2689d | balrog | .rate = 12000000,
|
375 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
376 | c3d2689d | balrog | }; |
377 | c3d2689d | balrog | |
378 | c3d2689d | balrog | static struct clk uart3_16xx = { |
379 | c3d2689d | balrog | .name = "uart3_ck",
|
380 | c3d2689d | balrog | /* Direct from ULPD, no real parent */
|
381 | c3d2689d | balrog | .parent = &armper_ck, |
382 | c3d2689d | balrog | .rate = 48000000,
|
383 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
384 | c3d2689d | balrog | }; |
385 | c3d2689d | balrog | |
386 | c3d2689d | balrog | static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ |
387 | c3d2689d | balrog | .name = "usb_clk0",
|
388 | c3d2689d | balrog | .alias = "usb.clko",
|
389 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
390 | c3d2689d | balrog | .rate = 6000000,
|
391 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
392 | c3d2689d | balrog | }; |
393 | c3d2689d | balrog | |
394 | c3d2689d | balrog | static struct clk usb_hhc_ck1510 = { |
395 | c3d2689d | balrog | .name = "usb_hhc_ck",
|
396 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
397 | c3d2689d | balrog | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
398 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
399 | c3d2689d | balrog | }; |
400 | c3d2689d | balrog | |
401 | c3d2689d | balrog | static struct clk usb_hhc_ck16xx = { |
402 | c3d2689d | balrog | .name = "usb_hhc_ck",
|
403 | c3d2689d | balrog | /* Direct from ULPD, no parent */
|
404 | c3d2689d | balrog | .rate = 48000000,
|
405 | c3d2689d | balrog | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
406 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
407 | c3d2689d | balrog | }; |
408 | c3d2689d | balrog | |
409 | d8f699cb | balrog | static struct clk usb_w2fc_mclk = { |
410 | d8f699cb | balrog | .name = "usb_w2fc_mclk",
|
411 | d8f699cb | balrog | .alias = "usb_w2fc_ck",
|
412 | d8f699cb | balrog | .parent = &ck_48m, |
413 | c3d2689d | balrog | .rate = 48000000,
|
414 | d8f699cb | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
415 | c3d2689d | balrog | }; |
416 | c3d2689d | balrog | |
417 | c3d2689d | balrog | static struct clk mclk_1510 = { |
418 | c3d2689d | balrog | .name = "mclk",
|
419 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
420 | c3d2689d | balrog | .rate = 12000000,
|
421 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510, |
422 | c3d2689d | balrog | }; |
423 | c3d2689d | balrog | |
424 | c3d2689d | balrog | static struct clk bclk_310 = { |
425 | c3d2689d | balrog | .name = "bt_mclk_out", /* Alias midi_mclk_out? */ |
426 | c3d2689d | balrog | .parent = &armper_ck, |
427 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310, |
428 | c3d2689d | balrog | }; |
429 | c3d2689d | balrog | |
430 | c3d2689d | balrog | static struct clk mclk_310 = { |
431 | c3d2689d | balrog | .name = "com_mclk_out",
|
432 | c3d2689d | balrog | .parent = &armper_ck, |
433 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310, |
434 | c3d2689d | balrog | }; |
435 | c3d2689d | balrog | |
436 | c3d2689d | balrog | static struct clk mclk_16xx = { |
437 | c3d2689d | balrog | .name = "mclk",
|
438 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
439 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
440 | c3d2689d | balrog | }; |
441 | c3d2689d | balrog | |
442 | c3d2689d | balrog | static struct clk bclk_1510 = { |
443 | c3d2689d | balrog | .name = "bclk",
|
444 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
445 | c3d2689d | balrog | .rate = 12000000,
|
446 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510, |
447 | c3d2689d | balrog | }; |
448 | c3d2689d | balrog | |
449 | c3d2689d | balrog | static struct clk bclk_16xx = { |
450 | c3d2689d | balrog | .name = "bclk",
|
451 | c3d2689d | balrog | /* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
452 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
453 | c3d2689d | balrog | }; |
454 | c3d2689d | balrog | |
455 | c3d2689d | balrog | static struct clk mmc1_ck = { |
456 | c3d2689d | balrog | .name = "mmc_ck",
|
457 | c3d2689d | balrog | .id = 1,
|
458 | c3d2689d | balrog | /* Functional clock is direct from ULPD, interface clock is ARMPER */
|
459 | c3d2689d | balrog | .parent = &armper_ck, /* either armper_ck or dpll4 */
|
460 | c3d2689d | balrog | .rate = 48000000,
|
461 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
462 | c3d2689d | balrog | }; |
463 | c3d2689d | balrog | |
464 | c3d2689d | balrog | static struct clk mmc2_ck = { |
465 | c3d2689d | balrog | .name = "mmc_ck",
|
466 | c3d2689d | balrog | .id = 2,
|
467 | c3d2689d | balrog | /* Functional clock is direct from ULPD, interface clock is ARMPER */
|
468 | c3d2689d | balrog | .parent = &armper_ck, |
469 | c3d2689d | balrog | .rate = 48000000,
|
470 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX, |
471 | c3d2689d | balrog | }; |
472 | c3d2689d | balrog | |
473 | c3d2689d | balrog | static struct clk cam_mclk = { |
474 | c3d2689d | balrog | .name = "cam.mclk",
|
475 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
476 | c3d2689d | balrog | .rate = 12000000,
|
477 | c3d2689d | balrog | }; |
478 | c3d2689d | balrog | |
479 | c3d2689d | balrog | static struct clk cam_exclk = { |
480 | c3d2689d | balrog | .name = "cam.exclk",
|
481 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
482 | c3d2689d | balrog | /* Either 12M from cam.mclk or 48M from dpll4 */
|
483 | c3d2689d | balrog | .parent = &cam_mclk, |
484 | c3d2689d | balrog | }; |
485 | c3d2689d | balrog | |
486 | c3d2689d | balrog | static struct clk cam_lclk = { |
487 | c3d2689d | balrog | .name = "cam.lclk",
|
488 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
489 | c3d2689d | balrog | }; |
490 | c3d2689d | balrog | |
491 | c3d2689d | balrog | static struct clk i2c_fck = { |
492 | c3d2689d | balrog | .name = "i2c_fck",
|
493 | c3d2689d | balrog | .id = 1,
|
494 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
495 | c3d2689d | balrog | ALWAYS_ENABLED, |
496 | c3d2689d | balrog | .parent = &armxor_ck, |
497 | c3d2689d | balrog | }; |
498 | c3d2689d | balrog | |
499 | c3d2689d | balrog | static struct clk i2c_ick = { |
500 | c3d2689d | balrog | .name = "i2c_ick",
|
501 | c3d2689d | balrog | .id = 1,
|
502 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
503 | c3d2689d | balrog | .parent = &armper_ck, |
504 | c3d2689d | balrog | }; |
505 | c3d2689d | balrog | |
506 | c3d2689d | balrog | static struct clk clk32k = { |
507 | c3d2689d | balrog | .name = "clk32-kHz",
|
508 | c3d2689d | balrog | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
509 | 827df9f3 | balrog | CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
510 | 827df9f3 | balrog | .parent = &xtal_osc32k, |
511 | 827df9f3 | balrog | }; |
512 | 827df9f3 | balrog | |
513 | 827df9f3 | balrog | static struct clk apll_96m = { |
514 | 827df9f3 | balrog | .name = "apll_96m",
|
515 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
516 | 827df9f3 | balrog | .rate = 96000000,
|
517 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
518 | 827df9f3 | balrog | }; |
519 | 827df9f3 | balrog | |
520 | 827df9f3 | balrog | static struct clk apll_54m = { |
521 | 827df9f3 | balrog | .name = "apll_54m",
|
522 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
523 | 827df9f3 | balrog | .rate = 54000000,
|
524 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
525 | 827df9f3 | balrog | }; |
526 | 827df9f3 | balrog | |
527 | 827df9f3 | balrog | static struct clk sys_clk = { |
528 | 827df9f3 | balrog | .name = "sys_clk",
|
529 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
530 | 827df9f3 | balrog | .rate = 32768,
|
531 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
532 | 827df9f3 | balrog | }; |
533 | 827df9f3 | balrog | |
534 | 827df9f3 | balrog | static struct clk sleep_clk = { |
535 | 827df9f3 | balrog | .name = "sleep_clk",
|
536 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
537 | 827df9f3 | balrog | .rate = 32768,
|
538 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
539 | 827df9f3 | balrog | }; |
540 | 827df9f3 | balrog | |
541 | 827df9f3 | balrog | static struct clk dpll_ck = { |
542 | 827df9f3 | balrog | .name = "dpll",
|
543 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
544 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
545 | 827df9f3 | balrog | }; |
546 | 827df9f3 | balrog | |
547 | 827df9f3 | balrog | static struct clk dpll_x2_ck = { |
548 | 827df9f3 | balrog | .name = "dpll_x2",
|
549 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
550 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
551 | 827df9f3 | balrog | }; |
552 | 827df9f3 | balrog | |
553 | 827df9f3 | balrog | static struct clk wdt1_sys_clk = { |
554 | 827df9f3 | balrog | .name = "wdt1_sys_clk",
|
555 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED, |
556 | 827df9f3 | balrog | .rate = 32768,
|
557 | 827df9f3 | balrog | /*.parent = sys.xtalin */
|
558 | 827df9f3 | balrog | }; |
559 | 827df9f3 | balrog | |
560 | 827df9f3 | balrog | static struct clk func_96m_clk = { |
561 | 827df9f3 | balrog | .name = "func_96m_clk",
|
562 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
563 | 827df9f3 | balrog | .divisor = 1,
|
564 | 827df9f3 | balrog | .parent = &apll_96m, |
565 | 827df9f3 | balrog | }; |
566 | 827df9f3 | balrog | |
567 | 827df9f3 | balrog | static struct clk func_48m_clk = { |
568 | 827df9f3 | balrog | .name = "func_48m_clk",
|
569 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
570 | 827df9f3 | balrog | .divisor = 2,
|
571 | 827df9f3 | balrog | .parent = &apll_96m, |
572 | 827df9f3 | balrog | }; |
573 | 827df9f3 | balrog | |
574 | 827df9f3 | balrog | static struct clk func_12m_clk = { |
575 | 827df9f3 | balrog | .name = "func_12m_clk",
|
576 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
577 | 827df9f3 | balrog | .divisor = 8,
|
578 | 827df9f3 | balrog | .parent = &apll_96m, |
579 | 827df9f3 | balrog | }; |
580 | 827df9f3 | balrog | |
581 | 827df9f3 | balrog | static struct clk func_54m_clk = { |
582 | 827df9f3 | balrog | .name = "func_54m_clk",
|
583 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X, |
584 | 827df9f3 | balrog | .divisor = 1,
|
585 | 827df9f3 | balrog | .parent = &apll_54m, |
586 | 827df9f3 | balrog | }; |
587 | 827df9f3 | balrog | |
588 | 827df9f3 | balrog | static struct clk sys_clkout = { |
589 | 827df9f3 | balrog | .name = "clkout",
|
590 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
591 | 827df9f3 | balrog | .parent = &sys_clk, |
592 | 827df9f3 | balrog | }; |
593 | 827df9f3 | balrog | |
594 | 827df9f3 | balrog | static struct clk sys_clkout2 = { |
595 | 827df9f3 | balrog | .name = "clkout2",
|
596 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
597 | 827df9f3 | balrog | .parent = &sys_clk, |
598 | 827df9f3 | balrog | }; |
599 | 827df9f3 | balrog | |
600 | 827df9f3 | balrog | static struct clk core_clk = { |
601 | 827df9f3 | balrog | .name = "core_clk",
|
602 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
603 | 827df9f3 | balrog | .parent = &dpll_ck, |
604 | 827df9f3 | balrog | }; |
605 | 827df9f3 | balrog | |
606 | 827df9f3 | balrog | static struct clk l3_clk = { |
607 | 827df9f3 | balrog | .name = "l3_clk",
|
608 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
609 | 827df9f3 | balrog | .parent = &core_clk, |
610 | 827df9f3 | balrog | }; |
611 | 827df9f3 | balrog | |
612 | 827df9f3 | balrog | static struct clk core_l4_iclk = { |
613 | 827df9f3 | balrog | .name = "core_l4_iclk",
|
614 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
615 | 827df9f3 | balrog | .parent = &l3_clk, |
616 | 827df9f3 | balrog | }; |
617 | 827df9f3 | balrog | |
618 | 827df9f3 | balrog | static struct clk wu_l4_iclk = { |
619 | 827df9f3 | balrog | .name = "wu_l4_iclk",
|
620 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
621 | 827df9f3 | balrog | .parent = &l3_clk, |
622 | 827df9f3 | balrog | }; |
623 | 827df9f3 | balrog | |
624 | 827df9f3 | balrog | static struct clk core_l3_iclk = { |
625 | 827df9f3 | balrog | .name = "core_l3_iclk",
|
626 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
627 | 827df9f3 | balrog | .parent = &core_clk, |
628 | 827df9f3 | balrog | }; |
629 | 827df9f3 | balrog | |
630 | 827df9f3 | balrog | static struct clk core_l4_usb_clk = { |
631 | 827df9f3 | balrog | .name = "core_l4_usb_clk",
|
632 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
633 | 827df9f3 | balrog | .parent = &l3_clk, |
634 | 827df9f3 | balrog | }; |
635 | 827df9f3 | balrog | |
636 | 827df9f3 | balrog | static struct clk wu_gpt1_clk = { |
637 | 827df9f3 | balrog | .name = "wu_gpt1_clk",
|
638 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
639 | 827df9f3 | balrog | .parent = &sys_clk, |
640 | 827df9f3 | balrog | }; |
641 | 827df9f3 | balrog | |
642 | 827df9f3 | balrog | static struct clk wu_32k_clk = { |
643 | 827df9f3 | balrog | .name = "wu_32k_clk",
|
644 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
645 | 827df9f3 | balrog | .parent = &sys_clk, |
646 | 827df9f3 | balrog | }; |
647 | 827df9f3 | balrog | |
648 | 827df9f3 | balrog | static struct clk uart1_fclk = { |
649 | 827df9f3 | balrog | .name = "uart1_fclk",
|
650 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
651 | 827df9f3 | balrog | .parent = &func_48m_clk, |
652 | 827df9f3 | balrog | }; |
653 | 827df9f3 | balrog | |
654 | 827df9f3 | balrog | static struct clk uart1_iclk = { |
655 | 827df9f3 | balrog | .name = "uart1_iclk",
|
656 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
657 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
658 | 827df9f3 | balrog | }; |
659 | 827df9f3 | balrog | |
660 | 827df9f3 | balrog | static struct clk uart2_fclk = { |
661 | 827df9f3 | balrog | .name = "uart2_fclk",
|
662 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
663 | 827df9f3 | balrog | .parent = &func_48m_clk, |
664 | 827df9f3 | balrog | }; |
665 | 827df9f3 | balrog | |
666 | 827df9f3 | balrog | static struct clk uart2_iclk = { |
667 | 827df9f3 | balrog | .name = "uart2_iclk",
|
668 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
669 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
670 | 827df9f3 | balrog | }; |
671 | 827df9f3 | balrog | |
672 | 827df9f3 | balrog | static struct clk uart3_fclk = { |
673 | 827df9f3 | balrog | .name = "uart3_fclk",
|
674 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
675 | 827df9f3 | balrog | .parent = &func_48m_clk, |
676 | 827df9f3 | balrog | }; |
677 | 827df9f3 | balrog | |
678 | 827df9f3 | balrog | static struct clk uart3_iclk = { |
679 | 827df9f3 | balrog | .name = "uart3_iclk",
|
680 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
681 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
682 | 827df9f3 | balrog | }; |
683 | 827df9f3 | balrog | |
684 | 827df9f3 | balrog | static struct clk mpu_fclk = { |
685 | 827df9f3 | balrog | .name = "mpu_fclk",
|
686 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
687 | 827df9f3 | balrog | .parent = &core_clk, |
688 | 827df9f3 | balrog | }; |
689 | 827df9f3 | balrog | |
690 | 827df9f3 | balrog | static struct clk mpu_iclk = { |
691 | 827df9f3 | balrog | .name = "mpu_iclk",
|
692 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
693 | 827df9f3 | balrog | .parent = &core_clk, |
694 | 827df9f3 | balrog | }; |
695 | 827df9f3 | balrog | |
696 | 827df9f3 | balrog | static struct clk int_m_fclk = { |
697 | 827df9f3 | balrog | .name = "int_m_fclk",
|
698 | 827df9f3 | balrog | .alias = "mpu_intc_fclk",
|
699 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
700 | 827df9f3 | balrog | .parent = &core_clk, |
701 | 827df9f3 | balrog | }; |
702 | 827df9f3 | balrog | |
703 | 827df9f3 | balrog | static struct clk int_m_iclk = { |
704 | 827df9f3 | balrog | .name = "int_m_iclk",
|
705 | 827df9f3 | balrog | .alias = "mpu_intc_iclk",
|
706 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
707 | 827df9f3 | balrog | .parent = &core_clk, |
708 | 827df9f3 | balrog | }; |
709 | 827df9f3 | balrog | |
710 | 827df9f3 | balrog | static struct clk core_gpt2_clk = { |
711 | 827df9f3 | balrog | .name = "core_gpt2_clk",
|
712 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
713 | 827df9f3 | balrog | .parent = &sys_clk, |
714 | 827df9f3 | balrog | }; |
715 | 827df9f3 | balrog | |
716 | 827df9f3 | balrog | static struct clk core_gpt3_clk = { |
717 | 827df9f3 | balrog | .name = "core_gpt3_clk",
|
718 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
719 | 827df9f3 | balrog | .parent = &sys_clk, |
720 | 827df9f3 | balrog | }; |
721 | 827df9f3 | balrog | |
722 | 827df9f3 | balrog | static struct clk core_gpt4_clk = { |
723 | 827df9f3 | balrog | .name = "core_gpt4_clk",
|
724 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
725 | 827df9f3 | balrog | .parent = &sys_clk, |
726 | 827df9f3 | balrog | }; |
727 | 827df9f3 | balrog | |
728 | 827df9f3 | balrog | static struct clk core_gpt5_clk = { |
729 | 827df9f3 | balrog | .name = "core_gpt5_clk",
|
730 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
731 | 827df9f3 | balrog | .parent = &sys_clk, |
732 | 827df9f3 | balrog | }; |
733 | 827df9f3 | balrog | |
734 | 827df9f3 | balrog | static struct clk core_gpt6_clk = { |
735 | 827df9f3 | balrog | .name = "core_gpt6_clk",
|
736 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
737 | 827df9f3 | balrog | .parent = &sys_clk, |
738 | 827df9f3 | balrog | }; |
739 | 827df9f3 | balrog | |
740 | 827df9f3 | balrog | static struct clk core_gpt7_clk = { |
741 | 827df9f3 | balrog | .name = "core_gpt7_clk",
|
742 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
743 | 827df9f3 | balrog | .parent = &sys_clk, |
744 | 827df9f3 | balrog | }; |
745 | 827df9f3 | balrog | |
746 | 827df9f3 | balrog | static struct clk core_gpt8_clk = { |
747 | 827df9f3 | balrog | .name = "core_gpt8_clk",
|
748 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
749 | 827df9f3 | balrog | .parent = &sys_clk, |
750 | 827df9f3 | balrog | }; |
751 | 827df9f3 | balrog | |
752 | 827df9f3 | balrog | static struct clk core_gpt9_clk = { |
753 | 827df9f3 | balrog | .name = "core_gpt9_clk",
|
754 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
755 | 827df9f3 | balrog | .parent = &sys_clk, |
756 | 827df9f3 | balrog | }; |
757 | 827df9f3 | balrog | |
758 | 827df9f3 | balrog | static struct clk core_gpt10_clk = { |
759 | 827df9f3 | balrog | .name = "core_gpt10_clk",
|
760 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
761 | 827df9f3 | balrog | .parent = &sys_clk, |
762 | 827df9f3 | balrog | }; |
763 | 827df9f3 | balrog | |
764 | 827df9f3 | balrog | static struct clk core_gpt11_clk = { |
765 | 827df9f3 | balrog | .name = "core_gpt11_clk",
|
766 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
767 | 827df9f3 | balrog | .parent = &sys_clk, |
768 | 827df9f3 | balrog | }; |
769 | 827df9f3 | balrog | |
770 | 827df9f3 | balrog | static struct clk core_gpt12_clk = { |
771 | 827df9f3 | balrog | .name = "core_gpt12_clk",
|
772 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
773 | 827df9f3 | balrog | .parent = &sys_clk, |
774 | 827df9f3 | balrog | }; |
775 | 827df9f3 | balrog | |
776 | 827df9f3 | balrog | static struct clk mcbsp1_clk = { |
777 | 827df9f3 | balrog | .name = "mcbsp1_cg",
|
778 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
779 | 827df9f3 | balrog | .divisor = 2,
|
780 | 827df9f3 | balrog | .parent = &func_96m_clk, |
781 | 827df9f3 | balrog | }; |
782 | 827df9f3 | balrog | |
783 | 827df9f3 | balrog | static struct clk mcbsp2_clk = { |
784 | 827df9f3 | balrog | .name = "mcbsp2_cg",
|
785 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
786 | 827df9f3 | balrog | .divisor = 2,
|
787 | 827df9f3 | balrog | .parent = &func_96m_clk, |
788 | 827df9f3 | balrog | }; |
789 | 827df9f3 | balrog | |
790 | 827df9f3 | balrog | static struct clk emul_clk = { |
791 | 827df9f3 | balrog | .name = "emul_ck",
|
792 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
793 | 827df9f3 | balrog | .parent = &func_54m_clk, |
794 | 827df9f3 | balrog | }; |
795 | 827df9f3 | balrog | |
796 | 827df9f3 | balrog | static struct clk sdma_fclk = { |
797 | 827df9f3 | balrog | .name = "sdma_fclk",
|
798 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
799 | 827df9f3 | balrog | .parent = &l3_clk, |
800 | 827df9f3 | balrog | }; |
801 | 827df9f3 | balrog | |
802 | 827df9f3 | balrog | static struct clk sdma_iclk = { |
803 | 827df9f3 | balrog | .name = "sdma_iclk",
|
804 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
805 | 827df9f3 | balrog | .parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */
|
806 | 827df9f3 | balrog | }; |
807 | 827df9f3 | balrog | |
808 | 827df9f3 | balrog | static struct clk i2c1_fclk = { |
809 | 827df9f3 | balrog | .name = "i2c1.fclk",
|
810 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
811 | 827df9f3 | balrog | .parent = &func_12m_clk, |
812 | 827df9f3 | balrog | .divisor = 1,
|
813 | 827df9f3 | balrog | }; |
814 | 827df9f3 | balrog | |
815 | 827df9f3 | balrog | static struct clk i2c1_iclk = { |
816 | 827df9f3 | balrog | .name = "i2c1.iclk",
|
817 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
818 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
819 | 827df9f3 | balrog | }; |
820 | 827df9f3 | balrog | |
821 | 827df9f3 | balrog | static struct clk i2c2_fclk = { |
822 | 827df9f3 | balrog | .name = "i2c2.fclk",
|
823 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
824 | 827df9f3 | balrog | .parent = &func_12m_clk, |
825 | 827df9f3 | balrog | .divisor = 1,
|
826 | 827df9f3 | balrog | }; |
827 | 827df9f3 | balrog | |
828 | 827df9f3 | balrog | static struct clk i2c2_iclk = { |
829 | 827df9f3 | balrog | .name = "i2c2.iclk",
|
830 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
831 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
832 | 827df9f3 | balrog | }; |
833 | 827df9f3 | balrog | |
834 | 827df9f3 | balrog | static struct clk gpio_dbclk[4] = { |
835 | 827df9f3 | balrog | { |
836 | 827df9f3 | balrog | .name = "gpio1_dbclk",
|
837 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
838 | 827df9f3 | balrog | .parent = &wu_32k_clk, |
839 | 827df9f3 | balrog | }, { |
840 | 827df9f3 | balrog | .name = "gpio2_dbclk",
|
841 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
842 | 827df9f3 | balrog | .parent = &wu_32k_clk, |
843 | 827df9f3 | balrog | }, { |
844 | 827df9f3 | balrog | .name = "gpio3_dbclk",
|
845 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
846 | 827df9f3 | balrog | .parent = &wu_32k_clk, |
847 | 827df9f3 | balrog | }, { |
848 | 827df9f3 | balrog | .name = "gpio4_dbclk",
|
849 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
850 | 827df9f3 | balrog | .parent = &wu_32k_clk, |
851 | 827df9f3 | balrog | }, |
852 | 827df9f3 | balrog | }; |
853 | 827df9f3 | balrog | |
854 | 827df9f3 | balrog | static struct clk gpio_iclk = { |
855 | 827df9f3 | balrog | .name = "gpio_iclk",
|
856 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
857 | 827df9f3 | balrog | .parent = &wu_l4_iclk, |
858 | 827df9f3 | balrog | }; |
859 | 827df9f3 | balrog | |
860 | 827df9f3 | balrog | static struct clk mmc_fck = { |
861 | 827df9f3 | balrog | .name = "mmc_fclk",
|
862 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X, |
863 | 827df9f3 | balrog | .parent = &func_96m_clk, |
864 | 827df9f3 | balrog | }; |
865 | 827df9f3 | balrog | |
866 | 827df9f3 | balrog | static struct clk mmc_ick = { |
867 | 827df9f3 | balrog | .name = "mmc_iclk",
|
868 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X, |
869 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
870 | 827df9f3 | balrog | }; |
871 | 827df9f3 | balrog | |
872 | 827df9f3 | balrog | static struct clk spi_fclk[3] = { |
873 | 827df9f3 | balrog | { |
874 | 827df9f3 | balrog | .name = "spi1_fclk",
|
875 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
876 | 827df9f3 | balrog | .parent = &func_48m_clk, |
877 | 827df9f3 | balrog | }, { |
878 | 827df9f3 | balrog | .name = "spi2_fclk",
|
879 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
880 | 827df9f3 | balrog | .parent = &func_48m_clk, |
881 | 827df9f3 | balrog | }, { |
882 | 827df9f3 | balrog | .name = "spi3_fclk",
|
883 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP243X, |
884 | 827df9f3 | balrog | .parent = &func_48m_clk, |
885 | 827df9f3 | balrog | }, |
886 | 827df9f3 | balrog | }; |
887 | 827df9f3 | balrog | |
888 | 827df9f3 | balrog | static struct clk dss_clk[2] = { |
889 | 827df9f3 | balrog | { |
890 | 827df9f3 | balrog | .name = "dss_clk1",
|
891 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
892 | 827df9f3 | balrog | .parent = &core_clk, |
893 | 827df9f3 | balrog | }, { |
894 | 827df9f3 | balrog | .name = "dss_clk2",
|
895 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
896 | 827df9f3 | balrog | .parent = &sys_clk, |
897 | 827df9f3 | balrog | }, |
898 | 827df9f3 | balrog | }; |
899 | 827df9f3 | balrog | |
900 | 827df9f3 | balrog | static struct clk dss_54m_clk = { |
901 | 827df9f3 | balrog | .name = "dss_54m_clk",
|
902 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
903 | 827df9f3 | balrog | .parent = &func_54m_clk, |
904 | 827df9f3 | balrog | }; |
905 | 827df9f3 | balrog | |
906 | 827df9f3 | balrog | static struct clk dss_l3_iclk = { |
907 | 827df9f3 | balrog | .name = "dss_l3_iclk",
|
908 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
909 | 827df9f3 | balrog | .parent = &core_l3_iclk, |
910 | 827df9f3 | balrog | }; |
911 | 827df9f3 | balrog | |
912 | 827df9f3 | balrog | static struct clk dss_l4_iclk = { |
913 | 827df9f3 | balrog | .name = "dss_l4_iclk",
|
914 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
915 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
916 | 827df9f3 | balrog | }; |
917 | 827df9f3 | balrog | |
918 | 827df9f3 | balrog | static struct clk spi_iclk[3] = { |
919 | 827df9f3 | balrog | { |
920 | 827df9f3 | balrog | .name = "spi1_iclk",
|
921 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
922 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
923 | 827df9f3 | balrog | }, { |
924 | 827df9f3 | balrog | .name = "spi2_iclk",
|
925 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
926 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
927 | 827df9f3 | balrog | }, { |
928 | 827df9f3 | balrog | .name = "spi3_iclk",
|
929 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP243X, |
930 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
931 | 827df9f3 | balrog | }, |
932 | 827df9f3 | balrog | }; |
933 | 827df9f3 | balrog | |
934 | 827df9f3 | balrog | static struct clk omapctrl_clk = { |
935 | 827df9f3 | balrog | .name = "omapctrl_iclk",
|
936 | 827df9f3 | balrog | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
937 | 827df9f3 | balrog | /* XXX Should be in WKUP domain */
|
938 | 827df9f3 | balrog | .parent = &core_l4_iclk, |
939 | c3d2689d | balrog | }; |
940 | c3d2689d | balrog | |
941 | c3d2689d | balrog | static struct clk *onchip_clks[] = { |
942 | 827df9f3 | balrog | /* OMAP 1 */
|
943 | 827df9f3 | balrog | |
944 | c3d2689d | balrog | /* non-ULPD clocks */
|
945 | c3d2689d | balrog | &xtal_osc12m, |
946 | c3d2689d | balrog | &xtal_osc32k, |
947 | c3d2689d | balrog | &ck_ref, |
948 | c3d2689d | balrog | &dpll1, |
949 | c3d2689d | balrog | &dpll2, |
950 | c3d2689d | balrog | &dpll3, |
951 | c3d2689d | balrog | &dpll4, |
952 | c3d2689d | balrog | &apll, |
953 | c3d2689d | balrog | &ck_48m, |
954 | c3d2689d | balrog | /* CK_GEN1 clocks */
|
955 | c3d2689d | balrog | &clkm1, |
956 | c3d2689d | balrog | &ck_dpll1out, |
957 | c3d2689d | balrog | &sossi_ck, |
958 | c3d2689d | balrog | &arm_ck, |
959 | c3d2689d | balrog | &armper_ck, |
960 | c3d2689d | balrog | &arm_gpio_ck, |
961 | c3d2689d | balrog | &armxor_ck, |
962 | c3d2689d | balrog | &armtim_ck, |
963 | c3d2689d | balrog | &armwdt_ck, |
964 | c3d2689d | balrog | &arminth_ck15xx, &arminth_ck16xx, |
965 | c3d2689d | balrog | /* CK_GEN2 clocks */
|
966 | c3d2689d | balrog | &clkm2, |
967 | c3d2689d | balrog | &dsp_ck, |
968 | c3d2689d | balrog | &dspmmu_ck, |
969 | c3d2689d | balrog | &dspper_ck, |
970 | c3d2689d | balrog | &dspxor_ck, |
971 | c3d2689d | balrog | &dsptim_ck, |
972 | c3d2689d | balrog | /* CK_GEN3 clocks */
|
973 | c3d2689d | balrog | &clkm3, |
974 | c3d2689d | balrog | &tc_ck, |
975 | c3d2689d | balrog | &tipb_ck, |
976 | c3d2689d | balrog | &l3_ocpi_ck, |
977 | c3d2689d | balrog | &tc1_ck, |
978 | c3d2689d | balrog | &tc2_ck, |
979 | c3d2689d | balrog | &dma_ck, |
980 | c3d2689d | balrog | &dma_lcdfree_ck, |
981 | c3d2689d | balrog | &api_ck, |
982 | c3d2689d | balrog | &lb_ck, |
983 | c3d2689d | balrog | &lbfree_ck, |
984 | d8f699cb | balrog | &hsab_ck, |
985 | c3d2689d | balrog | &rhea1_ck, |
986 | c3d2689d | balrog | &rhea2_ck, |
987 | c3d2689d | balrog | &lcd_ck_16xx, |
988 | c3d2689d | balrog | &lcd_ck_1510, |
989 | c3d2689d | balrog | /* ULPD clocks */
|
990 | c3d2689d | balrog | &uart1_1510, |
991 | c3d2689d | balrog | &uart1_16xx, |
992 | c3d2689d | balrog | &uart2_ck, |
993 | c3d2689d | balrog | &uart3_1510, |
994 | c3d2689d | balrog | &uart3_16xx, |
995 | c3d2689d | balrog | &usb_clk0, |
996 | c3d2689d | balrog | &usb_hhc_ck1510, &usb_hhc_ck16xx, |
997 | c3d2689d | balrog | &mclk_1510, &mclk_16xx, &mclk_310, |
998 | c3d2689d | balrog | &bclk_1510, &bclk_16xx, &bclk_310, |
999 | c3d2689d | balrog | &mmc1_ck, |
1000 | c3d2689d | balrog | &mmc2_ck, |
1001 | c3d2689d | balrog | &cam_mclk, |
1002 | c3d2689d | balrog | &cam_exclk, |
1003 | c3d2689d | balrog | &cam_lclk, |
1004 | c3d2689d | balrog | &clk32k, |
1005 | d8f699cb | balrog | &usb_w2fc_mclk, |
1006 | c3d2689d | balrog | /* Virtual clocks */
|
1007 | c3d2689d | balrog | &i2c_fck, |
1008 | c3d2689d | balrog | &i2c_ick, |
1009 | 827df9f3 | balrog | |
1010 | 827df9f3 | balrog | /* OMAP 2 */
|
1011 | 827df9f3 | balrog | |
1012 | 827df9f3 | balrog | &apll_96m, |
1013 | 827df9f3 | balrog | &apll_54m, |
1014 | 827df9f3 | balrog | &sys_clk, |
1015 | 827df9f3 | balrog | &sleep_clk, |
1016 | 827df9f3 | balrog | &dpll_ck, |
1017 | 827df9f3 | balrog | &dpll_x2_ck, |
1018 | 827df9f3 | balrog | &wdt1_sys_clk, |
1019 | 827df9f3 | balrog | &func_96m_clk, |
1020 | 827df9f3 | balrog | &func_48m_clk, |
1021 | 827df9f3 | balrog | &func_12m_clk, |
1022 | 827df9f3 | balrog | &func_54m_clk, |
1023 | 827df9f3 | balrog | &sys_clkout, |
1024 | 827df9f3 | balrog | &sys_clkout2, |
1025 | 827df9f3 | balrog | &core_clk, |
1026 | 827df9f3 | balrog | &l3_clk, |
1027 | 827df9f3 | balrog | &core_l4_iclk, |
1028 | 827df9f3 | balrog | &wu_l4_iclk, |
1029 | 827df9f3 | balrog | &core_l3_iclk, |
1030 | 827df9f3 | balrog | &core_l4_usb_clk, |
1031 | 827df9f3 | balrog | &wu_gpt1_clk, |
1032 | 827df9f3 | balrog | &wu_32k_clk, |
1033 | 827df9f3 | balrog | &uart1_fclk, |
1034 | 827df9f3 | balrog | &uart1_iclk, |
1035 | 827df9f3 | balrog | &uart2_fclk, |
1036 | 827df9f3 | balrog | &uart2_iclk, |
1037 | 827df9f3 | balrog | &uart3_fclk, |
1038 | 827df9f3 | balrog | &uart3_iclk, |
1039 | 827df9f3 | balrog | &mpu_fclk, |
1040 | 827df9f3 | balrog | &mpu_iclk, |
1041 | 827df9f3 | balrog | &int_m_fclk, |
1042 | 827df9f3 | balrog | &int_m_iclk, |
1043 | 827df9f3 | balrog | &core_gpt2_clk, |
1044 | 827df9f3 | balrog | &core_gpt3_clk, |
1045 | 827df9f3 | balrog | &core_gpt4_clk, |
1046 | 827df9f3 | balrog | &core_gpt5_clk, |
1047 | 827df9f3 | balrog | &core_gpt6_clk, |
1048 | 827df9f3 | balrog | &core_gpt7_clk, |
1049 | 827df9f3 | balrog | &core_gpt8_clk, |
1050 | 827df9f3 | balrog | &core_gpt9_clk, |
1051 | 827df9f3 | balrog | &core_gpt10_clk, |
1052 | 827df9f3 | balrog | &core_gpt11_clk, |
1053 | 827df9f3 | balrog | &core_gpt12_clk, |
1054 | 827df9f3 | balrog | &mcbsp1_clk, |
1055 | 827df9f3 | balrog | &mcbsp2_clk, |
1056 | 827df9f3 | balrog | &emul_clk, |
1057 | 827df9f3 | balrog | &sdma_fclk, |
1058 | 827df9f3 | balrog | &sdma_iclk, |
1059 | 827df9f3 | balrog | &i2c1_fclk, |
1060 | 827df9f3 | balrog | &i2c1_iclk, |
1061 | 827df9f3 | balrog | &i2c2_fclk, |
1062 | 827df9f3 | balrog | &i2c2_iclk, |
1063 | 827df9f3 | balrog | &gpio_dbclk[0],
|
1064 | 827df9f3 | balrog | &gpio_dbclk[1],
|
1065 | 827df9f3 | balrog | &gpio_dbclk[2],
|
1066 | 827df9f3 | balrog | &gpio_dbclk[3],
|
1067 | 827df9f3 | balrog | &gpio_iclk, |
1068 | 827df9f3 | balrog | &mmc_fck, |
1069 | 827df9f3 | balrog | &mmc_ick, |
1070 | 827df9f3 | balrog | &spi_fclk[0],
|
1071 | 827df9f3 | balrog | &spi_iclk[0],
|
1072 | 827df9f3 | balrog | &spi_fclk[1],
|
1073 | 827df9f3 | balrog | &spi_iclk[1],
|
1074 | 827df9f3 | balrog | &spi_fclk[2],
|
1075 | 827df9f3 | balrog | &spi_iclk[2],
|
1076 | 827df9f3 | balrog | &dss_clk[0],
|
1077 | 827df9f3 | balrog | &dss_clk[1],
|
1078 | 827df9f3 | balrog | &dss_54m_clk, |
1079 | 827df9f3 | balrog | &dss_l3_iclk, |
1080 | 827df9f3 | balrog | &dss_l4_iclk, |
1081 | 827df9f3 | balrog | &omapctrl_clk, |
1082 | 827df9f3 | balrog | |
1083 | c3d2689d | balrog | 0
|
1084 | c3d2689d | balrog | }; |
1085 | c3d2689d | balrog | |
1086 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user) |
1087 | c3d2689d | balrog | { |
1088 | c3d2689d | balrog | qemu_irq *i; |
1089 | c3d2689d | balrog | |
1090 | c3d2689d | balrog | for (i = clk->users; *i; i ++);
|
1091 | c3d2689d | balrog | *i = user; |
1092 | c3d2689d | balrog | } |
1093 | c3d2689d | balrog | |
1094 | c3d2689d | balrog | /* If a clock is allowed to idle, it is disabled automatically when
|
1095 | c3d2689d | balrog | * all of clock domains using it are disabled. */
|
1096 | c3d2689d | balrog | int omap_clk_is_idle(struct clk *clk) |
1097 | c3d2689d | balrog | { |
1098 | c3d2689d | balrog | struct clk *chld;
|
1099 | c3d2689d | balrog | |
1100 | c3d2689d | balrog | if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
|
1101 | c3d2689d | balrog | return 1; |
1102 | c3d2689d | balrog | if (clk->usecount)
|
1103 | c3d2689d | balrog | return 0; |
1104 | c3d2689d | balrog | |
1105 | c3d2689d | balrog | for (chld = clk->child1; chld; chld = chld->sibling)
|
1106 | c3d2689d | balrog | if (!omap_clk_is_idle(chld))
|
1107 | c3d2689d | balrog | return 0; |
1108 | c3d2689d | balrog | return 1; |
1109 | c3d2689d | balrog | } |
1110 | c3d2689d | balrog | |
1111 | c3d2689d | balrog | struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name) |
1112 | c3d2689d | balrog | { |
1113 | c3d2689d | balrog | struct clk *i;
|
1114 | c3d2689d | balrog | |
1115 | c3d2689d | balrog | for (i = mpu->clks; i->name; i ++)
|
1116 | c3d2689d | balrog | if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
|
1117 | c3d2689d | balrog | return i;
|
1118 | c3d2689d | balrog | cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
|
1119 | c3d2689d | balrog | } |
1120 | c3d2689d | balrog | |
1121 | c3d2689d | balrog | void omap_clk_get(struct clk *clk) |
1122 | c3d2689d | balrog | { |
1123 | c3d2689d | balrog | clk->usecount ++; |
1124 | c3d2689d | balrog | } |
1125 | c3d2689d | balrog | |
1126 | c3d2689d | balrog | void omap_clk_put(struct clk *clk) |
1127 | c3d2689d | balrog | { |
1128 | c3d2689d | balrog | if (!(clk->usecount --))
|
1129 | c3d2689d | balrog | cpu_abort(cpu_single_env, "%s: %s is not in use\n",
|
1130 | c3d2689d | balrog | __FUNCTION__, clk->name); |
1131 | c3d2689d | balrog | } |
1132 | c3d2689d | balrog | |
1133 | c3d2689d | balrog | static void omap_clk_update(struct clk *clk) |
1134 | c3d2689d | balrog | { |
1135 | c3d2689d | balrog | int parent, running;
|
1136 | c3d2689d | balrog | qemu_irq *user; |
1137 | c3d2689d | balrog | struct clk *i;
|
1138 | c3d2689d | balrog | |
1139 | c3d2689d | balrog | if (clk->parent)
|
1140 | c3d2689d | balrog | parent = clk->parent->running; |
1141 | c3d2689d | balrog | else
|
1142 | c3d2689d | balrog | parent = 1;
|
1143 | c3d2689d | balrog | |
1144 | c3d2689d | balrog | running = parent && (clk->enabled || |
1145 | c3d2689d | balrog | ((clk->flags & ALWAYS_ENABLED) && clk->usecount)); |
1146 | c3d2689d | balrog | if (clk->running != running) {
|
1147 | c3d2689d | balrog | clk->running = running; |
1148 | c3d2689d | balrog | for (user = clk->users; *user; user ++)
|
1149 | c3d2689d | balrog | qemu_set_irq(*user, running); |
1150 | c3d2689d | balrog | for (i = clk->child1; i; i = i->sibling)
|
1151 | c3d2689d | balrog | omap_clk_update(i); |
1152 | c3d2689d | balrog | } |
1153 | c3d2689d | balrog | } |
1154 | c3d2689d | balrog | |
1155 | c3d2689d | balrog | static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate, |
1156 | c3d2689d | balrog | unsigned long int div, unsigned long int mult) |
1157 | c3d2689d | balrog | { |
1158 | c3d2689d | balrog | struct clk *i;
|
1159 | c3d2689d | balrog | qemu_irq *user; |
1160 | c3d2689d | balrog | |
1161 | c3d2689d | balrog | clk->rate = muldiv64(rate, mult, div); |
1162 | c3d2689d | balrog | if (clk->running)
|
1163 | c3d2689d | balrog | for (user = clk->users; *user; user ++)
|
1164 | c3d2689d | balrog | qemu_irq_raise(*user); |
1165 | c3d2689d | balrog | for (i = clk->child1; i; i = i->sibling)
|
1166 | c3d2689d | balrog | omap_clk_rate_update_full(i, rate, |
1167 | c3d2689d | balrog | div * i->divisor, mult * i->multiplier); |
1168 | c3d2689d | balrog | } |
1169 | c3d2689d | balrog | |
1170 | c3d2689d | balrog | static void omap_clk_rate_update(struct clk *clk) |
1171 | c3d2689d | balrog | { |
1172 | c3d2689d | balrog | struct clk *i;
|
1173 | c3d2689d | balrog | unsigned long int div, mult = div = 1; |
1174 | c3d2689d | balrog | |
1175 | c3d2689d | balrog | for (i = clk; i->parent; i = i->parent) {
|
1176 | c3d2689d | balrog | div *= i->divisor; |
1177 | c3d2689d | balrog | mult *= i->multiplier; |
1178 | c3d2689d | balrog | } |
1179 | c3d2689d | balrog | |
1180 | c3d2689d | balrog | omap_clk_rate_update_full(clk, i->rate, div, mult); |
1181 | c3d2689d | balrog | } |
1182 | c3d2689d | balrog | |
1183 | c3d2689d | balrog | void omap_clk_reparent(struct clk *clk, struct clk *parent) |
1184 | c3d2689d | balrog | { |
1185 | c3d2689d | balrog | struct clk **p;
|
1186 | c3d2689d | balrog | |
1187 | c3d2689d | balrog | if (clk->parent) {
|
1188 | c3d2689d | balrog | for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
|
1189 | c3d2689d | balrog | *p = clk->sibling; |
1190 | c3d2689d | balrog | } |
1191 | c3d2689d | balrog | |
1192 | c3d2689d | balrog | clk->parent = parent; |
1193 | c3d2689d | balrog | if (parent) {
|
1194 | c3d2689d | balrog | clk->sibling = parent->child1; |
1195 | c3d2689d | balrog | parent->child1 = clk; |
1196 | c3d2689d | balrog | omap_clk_update(clk); |
1197 | c3d2689d | balrog | omap_clk_rate_update(clk); |
1198 | c3d2689d | balrog | } else
|
1199 | c3d2689d | balrog | clk->sibling = 0;
|
1200 | c3d2689d | balrog | } |
1201 | c3d2689d | balrog | |
1202 | c3d2689d | balrog | void omap_clk_onoff(struct clk *clk, int on) |
1203 | c3d2689d | balrog | { |
1204 | c3d2689d | balrog | clk->enabled = on; |
1205 | c3d2689d | balrog | omap_clk_update(clk); |
1206 | c3d2689d | balrog | } |
1207 | c3d2689d | balrog | |
1208 | c3d2689d | balrog | void omap_clk_canidle(struct clk *clk, int can) |
1209 | c3d2689d | balrog | { |
1210 | c3d2689d | balrog | if (can)
|
1211 | c3d2689d | balrog | omap_clk_put(clk); |
1212 | c3d2689d | balrog | else
|
1213 | c3d2689d | balrog | omap_clk_get(clk); |
1214 | c3d2689d | balrog | } |
1215 | c3d2689d | balrog | |
1216 | c3d2689d | balrog | void omap_clk_setrate(struct clk *clk, int divide, int multiply) |
1217 | c3d2689d | balrog | { |
1218 | c3d2689d | balrog | clk->divisor = divide; |
1219 | c3d2689d | balrog | clk->multiplier = multiply; |
1220 | c3d2689d | balrog | omap_clk_rate_update(clk); |
1221 | c3d2689d | balrog | } |
1222 | c3d2689d | balrog | |
1223 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk) |
1224 | c3d2689d | balrog | { |
1225 | c3d2689d | balrog | return clk->rate;
|
1226 | c3d2689d | balrog | } |
1227 | c3d2689d | balrog | |
1228 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu) |
1229 | c3d2689d | balrog | { |
1230 | c3d2689d | balrog | struct clk **i, *j, *k;
|
1231 | c3d2689d | balrog | int count;
|
1232 | c3d2689d | balrog | int flag;
|
1233 | c3d2689d | balrog | |
1234 | c3d2689d | balrog | if (cpu_is_omap310(mpu))
|
1235 | c3d2689d | balrog | flag = CLOCK_IN_OMAP310; |
1236 | c3d2689d | balrog | else if (cpu_is_omap1510(mpu)) |
1237 | c3d2689d | balrog | flag = CLOCK_IN_OMAP1510; |
1238 | 827df9f3 | balrog | else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu)) |
1239 | 827df9f3 | balrog | flag = CLOCK_IN_OMAP242X; |
1240 | 827df9f3 | balrog | else if (cpu_is_omap2430(mpu)) |
1241 | 827df9f3 | balrog | flag = CLOCK_IN_OMAP243X; |
1242 | 827df9f3 | balrog | else if (cpu_is_omap3430(mpu)) |
1243 | 827df9f3 | balrog | flag = CLOCK_IN_OMAP243X; |
1244 | c3d2689d | balrog | else
|
1245 | c3d2689d | balrog | return;
|
1246 | c3d2689d | balrog | |
1247 | c3d2689d | balrog | for (i = onchip_clks, count = 0; *i; i ++) |
1248 | c3d2689d | balrog | if ((*i)->flags & flag)
|
1249 | c3d2689d | balrog | count ++; |
1250 | c3d2689d | balrog | mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1)); |
1251 | c3d2689d | balrog | for (i = onchip_clks, j = mpu->clks; *i; i ++)
|
1252 | c3d2689d | balrog | if ((*i)->flags & flag) {
|
1253 | c3d2689d | balrog | memcpy(j, *i, sizeof(struct clk)); |
1254 | c3d2689d | balrog | for (k = mpu->clks; k < j; k ++)
|
1255 | c3d2689d | balrog | if (j->parent && !strcmp(j->parent->name, k->name)) {
|
1256 | c3d2689d | balrog | j->parent = k; |
1257 | c3d2689d | balrog | j->sibling = k->child1; |
1258 | c3d2689d | balrog | k->child1 = j; |
1259 | c3d2689d | balrog | } else if (k->parent && !strcmp(k->parent->name, j->name)) { |
1260 | c3d2689d | balrog | k->parent = j; |
1261 | c3d2689d | balrog | k->sibling = j->child1; |
1262 | c3d2689d | balrog | j->child1 = k; |
1263 | c3d2689d | balrog | } |
1264 | c3d2689d | balrog | j->divisor = j->divisor ?: 1;
|
1265 | c3d2689d | balrog | j->multiplier = j->multiplier ?: 1;
|
1266 | c3d2689d | balrog | j ++; |
1267 | c3d2689d | balrog | } |
1268 | b854bc19 | balrog | for (j = mpu->clks; count --; j ++) {
|
1269 | b854bc19 | balrog | omap_clk_update(j); |
1270 | b854bc19 | balrog | omap_clk_rate_update(j); |
1271 | b854bc19 | balrog | } |
1272 | c3d2689d | balrog | } |