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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 16450 UART emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-char.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 6936bfe5 | aurel32 | #include "qemu-timer.h" |
29 | 80cabfad | bellard | |
30 | 80cabfad | bellard | //#define DEBUG_SERIAL
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31 | 80cabfad | bellard | |
32 | 80cabfad | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
33 | 80cabfad | bellard | |
34 | 80cabfad | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
35 | 80cabfad | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
36 | 80cabfad | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
37 | 80cabfad | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
38 | 80cabfad | bellard | |
39 | 80cabfad | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
40 | 80cabfad | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
41 | 80cabfad | bellard | |
42 | 80cabfad | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
43 | 80cabfad | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
44 | 80cabfad | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
45 | 80cabfad | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
46 | 80cabfad | bellard | |
47 | 80cabfad | bellard | /*
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48 | 80cabfad | bellard | * These are the definitions for the Modem Control Register
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49 | 80cabfad | bellard | */
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50 | 80cabfad | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
51 | 80cabfad | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
52 | 80cabfad | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
53 | 80cabfad | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
54 | 80cabfad | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
55 | 80cabfad | bellard | |
56 | 80cabfad | bellard | /*
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57 | 80cabfad | bellard | * These are the definitions for the Modem Status Register
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58 | 80cabfad | bellard | */
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59 | 80cabfad | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
60 | 80cabfad | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
61 | 80cabfad | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
62 | 80cabfad | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
63 | 80cabfad | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
64 | 80cabfad | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
65 | 80cabfad | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
66 | 80cabfad | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
67 | 80cabfad | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
68 | 80cabfad | bellard | |
69 | 80cabfad | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
70 | 80cabfad | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
71 | 80cabfad | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
72 | 80cabfad | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
73 | 80cabfad | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
74 | 80cabfad | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
75 | 80cabfad | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
76 | 80cabfad | bellard | |
77 | 6936bfe5 | aurel32 | /*
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78 | 6936bfe5 | aurel32 | * Delay TX IRQ after sending as much characters as the given interval would
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79 | 6936bfe5 | aurel32 | * contain on real hardware. This avoids overloading the guest if it processes
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80 | 6936bfe5 | aurel32 | * its output buffer in a loop inside the TX IRQ handler.
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81 | 6936bfe5 | aurel32 | */
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82 | 6936bfe5 | aurel32 | #define THROTTLE_TX_INTERVAL 10 /* ms */ |
83 | 6936bfe5 | aurel32 | |
84 | b41a2cd1 | bellard | struct SerialState {
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85 | 508d92d0 | bellard | uint16_t divider; |
86 | 80cabfad | bellard | uint8_t rbr; /* receive register */
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87 | 80cabfad | bellard | uint8_t ier; |
88 | 80cabfad | bellard | uint8_t iir; /* read only */
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89 | 80cabfad | bellard | uint8_t lcr; |
90 | 80cabfad | bellard | uint8_t mcr; |
91 | 80cabfad | bellard | uint8_t lsr; /* read only */
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92 | 3e749fe1 | bellard | uint8_t msr; /* read only */
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93 | 80cabfad | bellard | uint8_t scr; |
94 | 80cabfad | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
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95 | 80cabfad | bellard | it can be reset while reading iir */
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96 | 80cabfad | bellard | int thr_ipending;
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97 | d537cf6c | pbrook | qemu_irq irq; |
98 | 82c643ff | bellard | CharDriverState *chr; |
99 | f8d179e3 | bellard | int last_break_enable;
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100 | 71db710f | blueswir1 | target_phys_addr_t base; |
101 | e5d13e2f | bellard | int it_shift;
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102 | b6cd0ea1 | aurel32 | int baudbase;
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103 | 6936bfe5 | aurel32 | QEMUTimer *tx_timer; |
104 | 6936bfe5 | aurel32 | int tx_burst;
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105 | b41a2cd1 | bellard | }; |
106 | 80cabfad | bellard | |
107 | b2a5160c | balrog | static void serial_receive_byte(SerialState *s, int ch); |
108 | b2a5160c | balrog | |
109 | b41a2cd1 | bellard | static void serial_update_irq(SerialState *s) |
110 | 80cabfad | bellard | { |
111 | 80cabfad | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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112 | 80cabfad | bellard | s->iir = UART_IIR_RDI; |
113 | 80cabfad | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
114 | 80cabfad | bellard | s->iir = UART_IIR_THRI; |
115 | 80cabfad | bellard | } else {
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116 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
117 | 80cabfad | bellard | } |
118 | 80cabfad | bellard | if (s->iir != UART_IIR_NO_INT) {
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119 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
120 | 80cabfad | bellard | } else {
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121 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
122 | 80cabfad | bellard | } |
123 | 80cabfad | bellard | } |
124 | 80cabfad | bellard | |
125 | 6936bfe5 | aurel32 | static void serial_tx_done(void *opaque) |
126 | 6936bfe5 | aurel32 | { |
127 | 6936bfe5 | aurel32 | SerialState *s = opaque; |
128 | 6936bfe5 | aurel32 | |
129 | 6936bfe5 | aurel32 | if (s->tx_burst < 0) { |
130 | 6936bfe5 | aurel32 | uint16_t divider; |
131 | 6936bfe5 | aurel32 | |
132 | 6936bfe5 | aurel32 | if (s->divider)
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133 | 6936bfe5 | aurel32 | divider = s->divider; |
134 | 6936bfe5 | aurel32 | else
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135 | 6936bfe5 | aurel32 | divider = 1;
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136 | 6936bfe5 | aurel32 | |
137 | 6936bfe5 | aurel32 | /* We assume 10 bits/char, OK for this purpose. */
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138 | 6936bfe5 | aurel32 | s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
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139 | b6cd0ea1 | aurel32 | (1000000 * 10 / (s->baudbase / divider)); |
140 | 6936bfe5 | aurel32 | } |
141 | 6936bfe5 | aurel32 | s->thr_ipending = 1;
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142 | 6936bfe5 | aurel32 | s->lsr |= UART_LSR_THRE; |
143 | 6936bfe5 | aurel32 | s->lsr |= UART_LSR_TEMT; |
144 | 6936bfe5 | aurel32 | serial_update_irq(s); |
145 | 6936bfe5 | aurel32 | } |
146 | 6936bfe5 | aurel32 | |
147 | f8d179e3 | bellard | static void serial_update_parameters(SerialState *s) |
148 | f8d179e3 | bellard | { |
149 | f8d179e3 | bellard | int speed, parity, data_bits, stop_bits;
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150 | 2122c51a | bellard | QEMUSerialSetParams ssp; |
151 | f8d179e3 | bellard | |
152 | f8d179e3 | bellard | if (s->lcr & 0x08) { |
153 | f8d179e3 | bellard | if (s->lcr & 0x10) |
154 | f8d179e3 | bellard | parity = 'E';
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155 | f8d179e3 | bellard | else
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156 | f8d179e3 | bellard | parity = 'O';
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157 | f8d179e3 | bellard | } else {
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158 | f8d179e3 | bellard | parity = 'N';
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159 | f8d179e3 | bellard | } |
160 | 5fafdf24 | ths | if (s->lcr & 0x04) |
161 | f8d179e3 | bellard | stop_bits = 2;
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162 | f8d179e3 | bellard | else
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163 | f8d179e3 | bellard | stop_bits = 1;
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164 | f8d179e3 | bellard | data_bits = (s->lcr & 0x03) + 5; |
165 | f8d179e3 | bellard | if (s->divider == 0) |
166 | f8d179e3 | bellard | return;
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167 | b6cd0ea1 | aurel32 | speed = s->baudbase / s->divider; |
168 | 2122c51a | bellard | ssp.speed = speed; |
169 | 2122c51a | bellard | ssp.parity = parity; |
170 | 2122c51a | bellard | ssp.data_bits = data_bits; |
171 | 2122c51a | bellard | ssp.stop_bits = stop_bits; |
172 | 2122c51a | bellard | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
173 | 2122c51a | bellard | #if 0
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174 | 5fafdf24 | ths | printf("speed=%d parity=%c data=%d stop=%d\n",
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175 | f8d179e3 | bellard | speed, parity, data_bits, stop_bits);
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176 | f8d179e3 | bellard | #endif
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177 | f8d179e3 | bellard | } |
178 | f8d179e3 | bellard | |
179 | b41a2cd1 | bellard | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
180 | 80cabfad | bellard | { |
181 | b41a2cd1 | bellard | SerialState *s = opaque; |
182 | 80cabfad | bellard | unsigned char ch; |
183 | 3b46e624 | ths | |
184 | 80cabfad | bellard | addr &= 7;
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185 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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186 | 80cabfad | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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187 | 80cabfad | bellard | #endif
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188 | 80cabfad | bellard | switch(addr) {
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189 | 80cabfad | bellard | default:
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190 | 80cabfad | bellard | case 0: |
191 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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192 | 80cabfad | bellard | s->divider = (s->divider & 0xff00) | val;
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193 | f8d179e3 | bellard | serial_update_parameters(s); |
194 | 80cabfad | bellard | } else {
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195 | 80cabfad | bellard | s->thr_ipending = 0;
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196 | 80cabfad | bellard | s->lsr &= ~UART_LSR_THRE; |
197 | b41a2cd1 | bellard | serial_update_irq(s); |
198 | 82c643ff | bellard | ch = val; |
199 | b2a5160c | balrog | if (!(s->mcr & UART_MCR_LOOP)) {
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200 | b2a5160c | balrog | /* when not in loopback mode, send the char */
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201 | b2a5160c | balrog | qemu_chr_write(s->chr, &ch, 1);
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202 | 6936bfe5 | aurel32 | } else {
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203 | b2a5160c | balrog | /* in loopback mode, say that we just received a char */
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204 | b2a5160c | balrog | serial_receive_byte(s, ch); |
205 | b2a5160c | balrog | } |
206 | 6936bfe5 | aurel32 | if (s->tx_burst > 0) { |
207 | 6936bfe5 | aurel32 | s->tx_burst--; |
208 | 6936bfe5 | aurel32 | serial_tx_done(s); |
209 | 6936bfe5 | aurel32 | } else if (s->tx_burst == 0) { |
210 | 6936bfe5 | aurel32 | s->tx_burst--; |
211 | 6936bfe5 | aurel32 | qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) + |
212 | 6936bfe5 | aurel32 | ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
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213 | 6936bfe5 | aurel32 | } |
214 | 80cabfad | bellard | } |
215 | 80cabfad | bellard | break;
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216 | 80cabfad | bellard | case 1: |
217 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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218 | 80cabfad | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
219 | f8d179e3 | bellard | serial_update_parameters(s); |
220 | 80cabfad | bellard | } else {
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221 | 60e336db | bellard | s->ier = val & 0x0f;
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222 | 60e336db | bellard | if (s->lsr & UART_LSR_THRE) {
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223 | 60e336db | bellard | s->thr_ipending = 1;
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224 | 60e336db | bellard | } |
225 | b41a2cd1 | bellard | serial_update_irq(s); |
226 | 80cabfad | bellard | } |
227 | 80cabfad | bellard | break;
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228 | 80cabfad | bellard | case 2: |
229 | 80cabfad | bellard | break;
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230 | 80cabfad | bellard | case 3: |
231 | f8d179e3 | bellard | { |
232 | f8d179e3 | bellard | int break_enable;
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233 | f8d179e3 | bellard | s->lcr = val; |
234 | f8d179e3 | bellard | serial_update_parameters(s); |
235 | f8d179e3 | bellard | break_enable = (val >> 6) & 1; |
236 | f8d179e3 | bellard | if (break_enable != s->last_break_enable) {
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237 | f8d179e3 | bellard | s->last_break_enable = break_enable; |
238 | 5fafdf24 | ths | qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
239 | 2122c51a | bellard | &break_enable); |
240 | f8d179e3 | bellard | } |
241 | f8d179e3 | bellard | } |
242 | 80cabfad | bellard | break;
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243 | 80cabfad | bellard | case 4: |
244 | 60e336db | bellard | s->mcr = val & 0x1f;
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245 | 80cabfad | bellard | break;
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246 | 80cabfad | bellard | case 5: |
247 | 80cabfad | bellard | break;
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248 | 80cabfad | bellard | case 6: |
249 | 80cabfad | bellard | break;
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250 | 80cabfad | bellard | case 7: |
251 | 80cabfad | bellard | s->scr = val; |
252 | 80cabfad | bellard | break;
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253 | 80cabfad | bellard | } |
254 | 80cabfad | bellard | } |
255 | 80cabfad | bellard | |
256 | b41a2cd1 | bellard | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
257 | 80cabfad | bellard | { |
258 | b41a2cd1 | bellard | SerialState *s = opaque; |
259 | 80cabfad | bellard | uint32_t ret; |
260 | 80cabfad | bellard | |
261 | 80cabfad | bellard | addr &= 7;
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262 | 80cabfad | bellard | switch(addr) {
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263 | 80cabfad | bellard | default:
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264 | 80cabfad | bellard | case 0: |
265 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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266 | 5fafdf24 | ths | ret = s->divider & 0xff;
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267 | 80cabfad | bellard | } else {
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268 | 80cabfad | bellard | ret = s->rbr; |
269 | 80cabfad | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
270 | b41a2cd1 | bellard | serial_update_irq(s); |
271 | b2a5160c | balrog | if (!(s->mcr & UART_MCR_LOOP)) {
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272 | b2a5160c | balrog | /* in loopback mode, don't receive any data */
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273 | b2a5160c | balrog | qemu_chr_accept_input(s->chr); |
274 | b2a5160c | balrog | } |
275 | 80cabfad | bellard | } |
276 | 80cabfad | bellard | break;
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277 | 80cabfad | bellard | case 1: |
278 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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279 | 80cabfad | bellard | ret = (s->divider >> 8) & 0xff; |
280 | 80cabfad | bellard | } else {
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281 | 80cabfad | bellard | ret = s->ier; |
282 | 80cabfad | bellard | } |
283 | 80cabfad | bellard | break;
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284 | 80cabfad | bellard | case 2: |
285 | 80cabfad | bellard | ret = s->iir; |
286 | 80cabfad | bellard | /* reset THR pending bit */
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287 | 80cabfad | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
288 | 80cabfad | bellard | s->thr_ipending = 0;
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289 | b41a2cd1 | bellard | serial_update_irq(s); |
290 | 80cabfad | bellard | break;
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291 | 80cabfad | bellard | case 3: |
292 | 80cabfad | bellard | ret = s->lcr; |
293 | 80cabfad | bellard | break;
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294 | 80cabfad | bellard | case 4: |
295 | 80cabfad | bellard | ret = s->mcr; |
296 | 80cabfad | bellard | break;
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297 | 80cabfad | bellard | case 5: |
298 | 80cabfad | bellard | ret = s->lsr; |
299 | 80cabfad | bellard | break;
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300 | 80cabfad | bellard | case 6: |
301 | 80cabfad | bellard | if (s->mcr & UART_MCR_LOOP) {
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302 | 80cabfad | bellard | /* in loopback, the modem output pins are connected to the
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303 | 80cabfad | bellard | inputs */
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304 | 80cabfad | bellard | ret = (s->mcr & 0x0c) << 4; |
305 | 80cabfad | bellard | ret |= (s->mcr & 0x02) << 3; |
306 | 80cabfad | bellard | ret |= (s->mcr & 0x01) << 5; |
307 | 80cabfad | bellard | } else {
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308 | 80cabfad | bellard | ret = s->msr; |
309 | 80cabfad | bellard | } |
310 | 80cabfad | bellard | break;
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311 | 80cabfad | bellard | case 7: |
312 | 80cabfad | bellard | ret = s->scr; |
313 | 80cabfad | bellard | break;
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314 | 80cabfad | bellard | } |
315 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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316 | 80cabfad | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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317 | 80cabfad | bellard | #endif
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318 | 80cabfad | bellard | return ret;
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319 | 80cabfad | bellard | } |
320 | 80cabfad | bellard | |
321 | 82c643ff | bellard | static int serial_can_receive(SerialState *s) |
322 | 80cabfad | bellard | { |
323 | 80cabfad | bellard | return !(s->lsr & UART_LSR_DR);
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324 | 80cabfad | bellard | } |
325 | 80cabfad | bellard | |
326 | 82c643ff | bellard | static void serial_receive_byte(SerialState *s, int ch) |
327 | 80cabfad | bellard | { |
328 | 80cabfad | bellard | s->rbr = ch; |
329 | 80cabfad | bellard | s->lsr |= UART_LSR_DR; |
330 | b41a2cd1 | bellard | serial_update_irq(s); |
331 | 80cabfad | bellard | } |
332 | 80cabfad | bellard | |
333 | 82c643ff | bellard | static void serial_receive_break(SerialState *s) |
334 | 80cabfad | bellard | { |
335 | 80cabfad | bellard | s->rbr = 0;
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336 | 80cabfad | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
337 | b41a2cd1 | bellard | serial_update_irq(s); |
338 | 80cabfad | bellard | } |
339 | 80cabfad | bellard | |
340 | b41a2cd1 | bellard | static int serial_can_receive1(void *opaque) |
341 | 80cabfad | bellard | { |
342 | b41a2cd1 | bellard | SerialState *s = opaque; |
343 | b41a2cd1 | bellard | return serial_can_receive(s);
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344 | b41a2cd1 | bellard | } |
345 | b41a2cd1 | bellard | |
346 | b41a2cd1 | bellard | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
347 | b41a2cd1 | bellard | { |
348 | b41a2cd1 | bellard | SerialState *s = opaque; |
349 | b41a2cd1 | bellard | serial_receive_byte(s, buf[0]);
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350 | b41a2cd1 | bellard | } |
351 | 80cabfad | bellard | |
352 | 82c643ff | bellard | static void serial_event(void *opaque, int event) |
353 | 82c643ff | bellard | { |
354 | 82c643ff | bellard | SerialState *s = opaque; |
355 | 82c643ff | bellard | if (event == CHR_EVENT_BREAK)
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356 | 82c643ff | bellard | serial_receive_break(s); |
357 | 82c643ff | bellard | } |
358 | 82c643ff | bellard | |
359 | 8738a8d0 | bellard | static void serial_save(QEMUFile *f, void *opaque) |
360 | 8738a8d0 | bellard | { |
361 | 8738a8d0 | bellard | SerialState *s = opaque; |
362 | 8738a8d0 | bellard | |
363 | 508d92d0 | bellard | qemu_put_be16s(f,&s->divider); |
364 | 8738a8d0 | bellard | qemu_put_8s(f,&s->rbr); |
365 | 8738a8d0 | bellard | qemu_put_8s(f,&s->ier); |
366 | 8738a8d0 | bellard | qemu_put_8s(f,&s->iir); |
367 | 8738a8d0 | bellard | qemu_put_8s(f,&s->lcr); |
368 | 8738a8d0 | bellard | qemu_put_8s(f,&s->mcr); |
369 | 8738a8d0 | bellard | qemu_put_8s(f,&s->lsr); |
370 | 8738a8d0 | bellard | qemu_put_8s(f,&s->msr); |
371 | 8738a8d0 | bellard | qemu_put_8s(f,&s->scr); |
372 | 8738a8d0 | bellard | } |
373 | 8738a8d0 | bellard | |
374 | 8738a8d0 | bellard | static int serial_load(QEMUFile *f, void *opaque, int version_id) |
375 | 8738a8d0 | bellard | { |
376 | 8738a8d0 | bellard | SerialState *s = opaque; |
377 | 8738a8d0 | bellard | |
378 | 508d92d0 | bellard | if(version_id > 2) |
379 | 8738a8d0 | bellard | return -EINVAL;
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380 | 8738a8d0 | bellard | |
381 | 508d92d0 | bellard | if (version_id >= 2) |
382 | 508d92d0 | bellard | qemu_get_be16s(f, &s->divider); |
383 | 508d92d0 | bellard | else
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384 | 508d92d0 | bellard | s->divider = qemu_get_byte(f); |
385 | 8738a8d0 | bellard | qemu_get_8s(f,&s->rbr); |
386 | 8738a8d0 | bellard | qemu_get_8s(f,&s->ier); |
387 | 8738a8d0 | bellard | qemu_get_8s(f,&s->iir); |
388 | 8738a8d0 | bellard | qemu_get_8s(f,&s->lcr); |
389 | 8738a8d0 | bellard | qemu_get_8s(f,&s->mcr); |
390 | 8738a8d0 | bellard | qemu_get_8s(f,&s->lsr); |
391 | 8738a8d0 | bellard | qemu_get_8s(f,&s->msr); |
392 | 8738a8d0 | bellard | qemu_get_8s(f,&s->scr); |
393 | 8738a8d0 | bellard | |
394 | 8738a8d0 | bellard | return 0; |
395 | 8738a8d0 | bellard | } |
396 | 8738a8d0 | bellard | |
397 | b2a5160c | balrog | static void serial_reset(void *opaque) |
398 | b2a5160c | balrog | { |
399 | b2a5160c | balrog | SerialState *s = opaque; |
400 | b2a5160c | balrog | |
401 | b2a5160c | balrog | s->divider = 0;
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402 | b2a5160c | balrog | s->rbr = 0;
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403 | b2a5160c | balrog | s->ier = 0;
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404 | b2a5160c | balrog | s->iir = UART_IIR_NO_INT; |
405 | b2a5160c | balrog | s->lcr = 0;
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406 | b2a5160c | balrog | s->mcr = 0;
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407 | b2a5160c | balrog | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
408 | b2a5160c | balrog | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
409 | b2a5160c | balrog | s->scr = 0;
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410 | b2a5160c | balrog | |
411 | b2a5160c | balrog | s->thr_ipending = 0;
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412 | b2a5160c | balrog | s->last_break_enable = 0;
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413 | b2a5160c | balrog | qemu_irq_lower(s->irq); |
414 | b2a5160c | balrog | } |
415 | b2a5160c | balrog | |
416 | b41a2cd1 | bellard | /* If fd is zero, it means that the serial device uses the console */
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417 | b6cd0ea1 | aurel32 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
418 | b6cd0ea1 | aurel32 | CharDriverState *chr) |
419 | b41a2cd1 | bellard | { |
420 | b41a2cd1 | bellard | SerialState *s; |
421 | b41a2cd1 | bellard | |
422 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(SerialState));
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423 | b41a2cd1 | bellard | if (!s)
|
424 | b41a2cd1 | bellard | return NULL; |
425 | 80cabfad | bellard | s->irq = irq; |
426 | b6cd0ea1 | aurel32 | s->baudbase = baudbase; |
427 | b2a5160c | balrog | |
428 | 6936bfe5 | aurel32 | s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s); |
429 | 6936bfe5 | aurel32 | if (!s->tx_timer)
|
430 | 6936bfe5 | aurel32 | return NULL; |
431 | 6936bfe5 | aurel32 | |
432 | b2a5160c | balrog | qemu_register_reset(serial_reset, s); |
433 | b2a5160c | balrog | serial_reset(s); |
434 | b41a2cd1 | bellard | |
435 | 508d92d0 | bellard | register_savevm("serial", base, 2, serial_save, serial_load, s); |
436 | 8738a8d0 | bellard | |
437 | b41a2cd1 | bellard | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
438 | b41a2cd1 | bellard | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
439 | 82c643ff | bellard | s->chr = chr; |
440 | e5b0bc44 | pbrook | qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
441 | e5b0bc44 | pbrook | serial_event, s); |
442 | b41a2cd1 | bellard | return s;
|
443 | 80cabfad | bellard | } |
444 | e5d13e2f | bellard | |
445 | e5d13e2f | bellard | /* Memory mapped interface */
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446 | a4bc3afc | ths | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
|
447 | e5d13e2f | bellard | { |
448 | e5d13e2f | bellard | SerialState *s = opaque; |
449 | e5d13e2f | bellard | |
450 | e5d13e2f | bellard | return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; |
451 | e5d13e2f | bellard | } |
452 | e5d13e2f | bellard | |
453 | a4bc3afc | ths | void serial_mm_writeb (void *opaque, |
454 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
455 | e5d13e2f | bellard | { |
456 | e5d13e2f | bellard | SerialState *s = opaque; |
457 | e5d13e2f | bellard | |
458 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
|
459 | e5d13e2f | bellard | } |
460 | e5d13e2f | bellard | |
461 | a4bc3afc | ths | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
|
462 | e5d13e2f | bellard | { |
463 | e5d13e2f | bellard | SerialState *s = opaque; |
464 | e918ee04 | ths | uint32_t val; |
465 | e5d13e2f | bellard | |
466 | e918ee04 | ths | val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
|
467 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
468 | e918ee04 | ths | val = bswap16(val); |
469 | e918ee04 | ths | #endif
|
470 | e918ee04 | ths | return val;
|
471 | e5d13e2f | bellard | } |
472 | e5d13e2f | bellard | |
473 | a4bc3afc | ths | void serial_mm_writew (void *opaque, |
474 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
475 | e5d13e2f | bellard | { |
476 | e5d13e2f | bellard | SerialState *s = opaque; |
477 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
478 | e918ee04 | ths | value = bswap16(value); |
479 | e918ee04 | ths | #endif
|
480 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
|
481 | e5d13e2f | bellard | } |
482 | e5d13e2f | bellard | |
483 | a4bc3afc | ths | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
|
484 | e5d13e2f | bellard | { |
485 | e5d13e2f | bellard | SerialState *s = opaque; |
486 | e918ee04 | ths | uint32_t val; |
487 | e5d13e2f | bellard | |
488 | e918ee04 | ths | val = serial_ioport_read(s, (addr - s->base) >> s->it_shift); |
489 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
490 | e918ee04 | ths | val = bswap32(val); |
491 | e918ee04 | ths | #endif
|
492 | e918ee04 | ths | return val;
|
493 | e5d13e2f | bellard | } |
494 | e5d13e2f | bellard | |
495 | a4bc3afc | ths | void serial_mm_writel (void *opaque, |
496 | a4bc3afc | ths | target_phys_addr_t addr, uint32_t value) |
497 | e5d13e2f | bellard | { |
498 | e5d13e2f | bellard | SerialState *s = opaque; |
499 | e918ee04 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
500 | e918ee04 | ths | value = bswap32(value); |
501 | e918ee04 | ths | #endif
|
502 | e5d13e2f | bellard | serial_ioport_write(s, (addr - s->base) >> s->it_shift, value); |
503 | e5d13e2f | bellard | } |
504 | e5d13e2f | bellard | |
505 | e5d13e2f | bellard | static CPUReadMemoryFunc *serial_mm_read[] = {
|
506 | e5d13e2f | bellard | &serial_mm_readb, |
507 | e5d13e2f | bellard | &serial_mm_readw, |
508 | e5d13e2f | bellard | &serial_mm_readl, |
509 | e5d13e2f | bellard | }; |
510 | e5d13e2f | bellard | |
511 | e5d13e2f | bellard | static CPUWriteMemoryFunc *serial_mm_write[] = {
|
512 | e5d13e2f | bellard | &serial_mm_writeb, |
513 | e5d13e2f | bellard | &serial_mm_writew, |
514 | e5d13e2f | bellard | &serial_mm_writel, |
515 | e5d13e2f | bellard | }; |
516 | e5d13e2f | bellard | |
517 | 71db710f | blueswir1 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
518 | b6cd0ea1 | aurel32 | qemu_irq irq, int baudbase,
|
519 | b6cd0ea1 | aurel32 | CharDriverState *chr, int ioregister)
|
520 | e5d13e2f | bellard | { |
521 | e5d13e2f | bellard | SerialState *s; |
522 | e5d13e2f | bellard | int s_io_memory;
|
523 | e5d13e2f | bellard | |
524 | e5d13e2f | bellard | s = qemu_mallocz(sizeof(SerialState));
|
525 | e5d13e2f | bellard | if (!s)
|
526 | e5d13e2f | bellard | return NULL; |
527 | e5d13e2f | bellard | s->irq = irq; |
528 | e5d13e2f | bellard | s->base = base; |
529 | e5d13e2f | bellard | s->it_shift = it_shift; |
530 | b6cd0ea1 | aurel32 | s->baudbase= baudbase; |
531 | e5d13e2f | bellard | |
532 | 6936bfe5 | aurel32 | s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s); |
533 | 6936bfe5 | aurel32 | if (!s->tx_timer)
|
534 | 6936bfe5 | aurel32 | return NULL; |
535 | 6936bfe5 | aurel32 | |
536 | b2a5160c | balrog | qemu_register_reset(serial_reset, s); |
537 | b2a5160c | balrog | serial_reset(s); |
538 | b2a5160c | balrog | |
539 | 508d92d0 | bellard | register_savevm("serial", base, 2, serial_save, serial_load, s); |
540 | e5d13e2f | bellard | |
541 | a4bc3afc | ths | if (ioregister) {
|
542 | a4bc3afc | ths | s_io_memory = cpu_register_io_memory(0, serial_mm_read,
|
543 | a4bc3afc | ths | serial_mm_write, s); |
544 | a4bc3afc | ths | cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
545 | a4bc3afc | ths | } |
546 | e5d13e2f | bellard | s->chr = chr; |
547 | e5b0bc44 | pbrook | qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, |
548 | e5b0bc44 | pbrook | serial_event, s); |
549 | e5d13e2f | bellard | return s;
|
550 | e5d13e2f | bellard | } |