Revision bf5b7423
| b/hw/sh.h | ||
|---|---|---|
| 35 | 35 |
/* sh_serial.c */ |
| 36 | 36 |
#define SH_SERIAL_FEAT_SCIF (1 << 0) |
| 37 | 37 |
void sh_serial_init (target_phys_addr_t base, int feat, |
| 38 |
uint32_t freq, CharDriverState *chr); |
|
| 38 |
uint32_t freq, CharDriverState *chr, |
|
| 39 |
struct intc_source *eri_source, |
|
| 40 |
struct intc_source *rxi_source, |
|
| 41 |
struct intc_source *txi_source, |
|
| 42 |
struct intc_source *tei_source, |
|
| 43 |
struct intc_source *bri_source); |
|
| 39 | 44 |
|
| 40 | 45 |
/* tc58128.c */ |
| 41 | 46 |
int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
| b/hw/sh7750.c | ||
|---|---|---|
| 556 | 556 |
|
| 557 | 557 |
cpu->intc_handle = &s->intc; |
| 558 | 558 |
|
| 559 |
sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0]); |
|
| 559 |
sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0], |
|
| 560 |
sh_intc_source(&s->intc, SCI1_ERI), |
|
| 561 |
sh_intc_source(&s->intc, SCI1_RXI), |
|
| 562 |
sh_intc_source(&s->intc, SCI1_TXI), |
|
| 563 |
sh_intc_source(&s->intc, SCI1_TEI), |
|
| 564 |
NULL); |
|
| 560 | 565 |
sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF, |
| 561 |
s->periph_freq, serial_hds[1]); |
|
| 566 |
s->periph_freq, serial_hds[1], |
|
| 567 |
sh_intc_source(&s->intc, SCIF_ERI), |
|
| 568 |
sh_intc_source(&s->intc, SCIF_RXI), |
|
| 569 |
sh_intc_source(&s->intc, SCIF_TXI), |
|
| 570 |
NULL, |
|
| 571 |
sh_intc_source(&s->intc, SCIF_BRI)); |
|
| 562 | 572 |
|
| 563 | 573 |
tmu012_init(0x1fd80000, |
| 564 | 574 |
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
| b/hw/sh_serial.c | ||
|---|---|---|
| 55 | 55 |
int flags; |
| 56 | 56 |
|
| 57 | 57 |
CharDriverState *chr; |
| 58 |
|
|
| 59 |
struct intc_source *eri; |
|
| 60 |
struct intc_source *rxi; |
|
| 61 |
struct intc_source *txi; |
|
| 62 |
struct intc_source *tei; |
|
| 63 |
struct intc_source *bri; |
|
| 58 | 64 |
} sh_serial_state; |
| 59 | 65 |
|
| 60 | 66 |
static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val) |
| ... | ... | |
| 74 | 80 |
s->brr = val; |
| 75 | 81 |
return; |
| 76 | 82 |
case 0x08: /* SCR */ |
| 77 |
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfb : 0xff);
|
|
| 83 |
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
|
|
| 78 | 84 |
if (!(val & (1 << 5))) |
| 79 | 85 |
s->flags |= SH_SERIAL_FLAG_TEND; |
| 86 |
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
|
|
| 87 |
if ((val & (1 << 7)) && !(s->txi->asserted)) |
|
| 88 |
sh_intc_toggle_source(s->txi, 0, 1); |
|
| 89 |
else if (!(val & (1 << 7)) && s->txi->asserted) |
|
| 90 |
sh_intc_toggle_source(s->txi, 0, -1); |
|
| 91 |
} |
|
| 80 | 92 |
return; |
| 81 | 93 |
case 0x0c: /* FTDR / TDR */ |
| 82 | 94 |
if (s->chr) {
|
| ... | ... | |
| 159 | 171 |
#endif |
| 160 | 172 |
if (s->feat & SH_SERIAL_FEAT_SCIF) {
|
| 161 | 173 |
switch(offs) {
|
| 174 |
case 0x00: /* SMR */ |
|
| 175 |
ret = s->smr; |
|
| 176 |
break; |
|
| 177 |
case 0x08: /* SCR */ |
|
| 178 |
ret = s->scr; |
|
| 179 |
break; |
|
| 162 | 180 |
case 0x10: /* FSR */ |
| 163 | 181 |
ret = 0; |
| 164 | 182 |
if (s->flags & SH_SERIAL_FLAG_TEND) |
| ... | ... | |
| 278 | 296 |
}; |
| 279 | 297 |
|
| 280 | 298 |
void sh_serial_init (target_phys_addr_t base, int feat, |
| 281 |
uint32_t freq, CharDriverState *chr) |
|
| 299 |
uint32_t freq, CharDriverState *chr, |
|
| 300 |
struct intc_source *eri_source, |
|
| 301 |
struct intc_source *rxi_source, |
|
| 302 |
struct intc_source *txi_source, |
|
| 303 |
struct intc_source *tei_source, |
|
| 304 |
struct intc_source *bri_source) |
|
| 282 | 305 |
{
|
| 283 | 306 |
sh_serial_state *s; |
| 284 | 307 |
int s_io_memory; |
| ... | ... | |
| 314 | 337 |
if (chr) |
| 315 | 338 |
qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, |
| 316 | 339 |
sh_serial_event, s); |
| 340 |
|
|
| 341 |
s->eri = eri_source; |
|
| 342 |
s->rxi = rxi_source; |
|
| 343 |
s->txi = txi_source; |
|
| 344 |
s->tei = tei_source; |
|
| 345 |
s->bri = bri_source; |
|
| 317 | 346 |
} |
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