root / tests / tcg / cris / check_cmpxc.s @ c09015dd
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1 | dd43edf4 | ths | # mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
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2 | dd43edf4 | ths | # output: 2\n2\n2\n2\nffff\nffff\nffff\nffff\nffffffff\nffffffff\nffffffff\n78134452\n78134452\n78134452\n78134452\n4452\n80000032\n |
3 | dd43edf4 | ths | |
4 | dd43edf4 | ths | .include "testutils.inc" |
5 | dd43edf4 | ths | start |
6 | dd43edf4 | ths | moveq 2,r3 |
7 | dd43edf4 | ths | cmps.b 0xff,r3 |
8 | dd43edf4 | ths | test_cc 0 0 0 1 |
9 | dd43edf4 | ths | checkr3 2 |
10 | dd43edf4 | ths | |
11 | dd43edf4 | ths | moveq 2,r3 |
12 | dd43edf4 | ths | cmps.w 0xffff,r3 |
13 | dd43edf4 | ths | test_cc 0 0 0 1 |
14 | dd43edf4 | ths | checkr3 2 |
15 | dd43edf4 | ths | |
16 | dd43edf4 | ths | moveq 2,r3 |
17 | dd43edf4 | ths | cmpu.b 0xff,r3 |
18 | dd43edf4 | ths | test_cc 1 0 0 1 |
19 | dd43edf4 | ths | checkr3 2 |
20 | dd43edf4 | ths | |
21 | dd43edf4 | ths | moveq 2,r3 |
22 | dd43edf4 | ths | move.d 0xffffffff,r4 |
23 | dd43edf4 | ths | cmpu.w -1,r3 |
24 | dd43edf4 | ths | test_cc 1 0 0 1 |
25 | dd43edf4 | ths | checkr3 2 |
26 | dd43edf4 | ths | |
27 | dd43edf4 | ths | move.d 0xffff,r3 |
28 | dd43edf4 | ths | cmpu.b -1,r3 |
29 | dd43edf4 | ths | test_cc 0 0 0 0 |
30 | dd43edf4 | ths | checkr3 ffff |
31 | dd43edf4 | ths | |
32 | dd43edf4 | ths | move.d 0xffff,r3 |
33 | dd43edf4 | ths | cmpu.w -1,r3 |
34 | dd43edf4 | ths | test_cc 0 1 0 0 |
35 | dd43edf4 | ths | checkr3 ffff |
36 | dd43edf4 | ths | |
37 | dd43edf4 | ths | move.d 0xffff,r3 |
38 | dd43edf4 | ths | cmps.b 0xff,r3 |
39 | dd43edf4 | ths | test_cc 0 0 0 1 |
40 | dd43edf4 | ths | checkr3 ffff |
41 | dd43edf4 | ths | |
42 | dd43edf4 | ths | move.d 0xffff,r3 |
43 | dd43edf4 | ths | cmps.w 0xffff,r3 |
44 | dd43edf4 | ths | test_cc 0 0 0 1 |
45 | dd43edf4 | ths | checkr3 ffff |
46 | dd43edf4 | ths | |
47 | dd43edf4 | ths | moveq -1,r3 |
48 | dd43edf4 | ths | cmps.b 0xff,r3 |
49 | dd43edf4 | ths | test_cc 0 1 0 0 |
50 | dd43edf4 | ths | checkr3 ffffffff |
51 | dd43edf4 | ths | |
52 | dd43edf4 | ths | moveq -1,r3 |
53 | dd43edf4 | ths | cmps.w 0xff,r3 |
54 | dd43edf4 | ths | test_cc 1 0 0 0 |
55 | dd43edf4 | ths | checkr3 ffffffff |
56 | dd43edf4 | ths | |
57 | dd43edf4 | ths | moveq -1,r3 |
58 | dd43edf4 | ths | cmps.w 0xffff,r3 |
59 | dd43edf4 | ths | test_cc 0 1 0 0 |
60 | dd43edf4 | ths | checkr3 ffffffff |
61 | dd43edf4 | ths | |
62 | dd43edf4 | ths | move.d 0x78134452,r3 |
63 | dd43edf4 | ths | cmpu.b 0x89,r3 |
64 | dd43edf4 | ths | test_cc 0 0 0 0 |
65 | dd43edf4 | ths | checkr3 78134452 |
66 | dd43edf4 | ths | |
67 | dd43edf4 | ths | move.d 0x78134452,r3 |
68 | dd43edf4 | ths | cmps.b 0x89,r3 |
69 | dd43edf4 | ths | test_cc 0 0 0 1 |
70 | dd43edf4 | ths | checkr3 78134452 |
71 | dd43edf4 | ths | |
72 | dd43edf4 | ths | move.d 0x78134452,r3 |
73 | dd43edf4 | ths | cmpu.w 0xf789,r3 |
74 | dd43edf4 | ths | test_cc 0 0 0 0 |
75 | dd43edf4 | ths | checkr3 78134452 |
76 | dd43edf4 | ths | |
77 | dd43edf4 | ths | move.d 0x78134452,r3 |
78 | dd43edf4 | ths | cmps.w 0xf789,r3 |
79 | dd43edf4 | ths | test_cc 0 0 0 1 |
80 | dd43edf4 | ths | checkr3 78134452 |
81 | dd43edf4 | ths | |
82 | dd43edf4 | ths | move.d 0x4452,r3 |
83 | dd43edf4 | ths | cmps.w 0x8002,r3 |
84 | dd43edf4 | ths | test_cc 0 0 0 1 |
85 | dd43edf4 | ths | checkr3 4452 |
86 | dd43edf4 | ths | |
87 | dd43edf4 | ths | move.d 0x80000032,r3 |
88 | dd43edf4 | ths | cmpu.w 0x764,r3 |
89 | dd43edf4 | ths | test_cc 0 0 1 0 |
90 | dd43edf4 | ths | checkr3 80000032 |
91 | dd43edf4 | ths | |
92 | dd43edf4 | ths | quit |