root / hw / versatilepb.c @ c0b1905b
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1 | 5fafdf24 | ths | /*
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2 | 16406950 | pbrook | * ARM Versatile Platform/Application Baseboard System emulation.
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3 | cdbdb648 | pbrook | *
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4 | a1bb27b1 | pbrook | * Copyright (c) 2005-2007 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | 2e9bdce5 | Paul Brook | #include "sysbus.h" |
11 | 87ecb68b | pbrook | #include "arm-misc.h" |
12 | 87ecb68b | pbrook | #include "primecell.h" |
13 | 87ecb68b | pbrook | #include "devices.h" |
14 | 87ecb68b | pbrook | #include "net.h" |
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 87ecb68b | pbrook | #include "pci.h" |
17 | 87ecb68b | pbrook | #include "boards.h" |
18 | cdbdb648 | pbrook | |
19 | cdbdb648 | pbrook | /* Primary interrupt controller. */
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20 | cdbdb648 | pbrook | |
21 | cdbdb648 | pbrook | typedef struct vpb_sic_state |
22 | cdbdb648 | pbrook | { |
23 | 3950f18b | Paul Brook | SysBusDevice busdev; |
24 | cdbdb648 | pbrook | uint32_t level; |
25 | cdbdb648 | pbrook | uint32_t mask; |
26 | cdbdb648 | pbrook | uint32_t pic_enable; |
27 | 97aff481 | Paul Brook | qemu_irq parent[32];
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28 | cdbdb648 | pbrook | int irq;
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29 | cdbdb648 | pbrook | } vpb_sic_state; |
30 | cdbdb648 | pbrook | |
31 | cdbdb648 | pbrook | static void vpb_sic_update(vpb_sic_state *s) |
32 | cdbdb648 | pbrook | { |
33 | cdbdb648 | pbrook | uint32_t flags; |
34 | cdbdb648 | pbrook | |
35 | cdbdb648 | pbrook | flags = s->level & s->mask; |
36 | d537cf6c | pbrook | qemu_set_irq(s->parent[s->irq], flags != 0);
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37 | cdbdb648 | pbrook | } |
38 | cdbdb648 | pbrook | |
39 | cdbdb648 | pbrook | static void vpb_sic_update_pic(vpb_sic_state *s) |
40 | cdbdb648 | pbrook | { |
41 | cdbdb648 | pbrook | int i;
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42 | cdbdb648 | pbrook | uint32_t mask; |
43 | cdbdb648 | pbrook | |
44 | cdbdb648 | pbrook | for (i = 21; i <= 30; i++) { |
45 | cdbdb648 | pbrook | mask = 1u << i;
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46 | cdbdb648 | pbrook | if (!(s->pic_enable & mask))
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47 | cdbdb648 | pbrook | continue;
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48 | d537cf6c | pbrook | qemu_set_irq(s->parent[i], (s->level & mask) != 0);
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49 | cdbdb648 | pbrook | } |
50 | cdbdb648 | pbrook | } |
51 | cdbdb648 | pbrook | |
52 | cdbdb648 | pbrook | static void vpb_sic_set_irq(void *opaque, int irq, int level) |
53 | cdbdb648 | pbrook | { |
54 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
55 | cdbdb648 | pbrook | if (level)
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56 | cdbdb648 | pbrook | s->level |= 1u << irq;
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57 | cdbdb648 | pbrook | else
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58 | cdbdb648 | pbrook | s->level &= ~(1u << irq);
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59 | cdbdb648 | pbrook | if (s->pic_enable & (1u << irq)) |
60 | d537cf6c | pbrook | qemu_set_irq(s->parent[irq], level); |
61 | cdbdb648 | pbrook | vpb_sic_update(s); |
62 | cdbdb648 | pbrook | } |
63 | cdbdb648 | pbrook | |
64 | c227f099 | Anthony Liguori | static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) |
65 | cdbdb648 | pbrook | { |
66 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
67 | cdbdb648 | pbrook | |
68 | cdbdb648 | pbrook | switch (offset >> 2) { |
69 | cdbdb648 | pbrook | case 0: /* STATUS */ |
70 | cdbdb648 | pbrook | return s->level & s->mask;
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71 | cdbdb648 | pbrook | case 1: /* RAWSTAT */ |
72 | cdbdb648 | pbrook | return s->level;
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73 | cdbdb648 | pbrook | case 2: /* ENABLE */ |
74 | cdbdb648 | pbrook | return s->mask;
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75 | cdbdb648 | pbrook | case 4: /* SOFTINT */ |
76 | cdbdb648 | pbrook | return s->level & 1; |
77 | cdbdb648 | pbrook | case 8: /* PICENABLE */ |
78 | cdbdb648 | pbrook | return s->pic_enable;
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79 | cdbdb648 | pbrook | default:
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80 | e69954b9 | pbrook | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
81 | cdbdb648 | pbrook | return 0; |
82 | cdbdb648 | pbrook | } |
83 | cdbdb648 | pbrook | } |
84 | cdbdb648 | pbrook | |
85 | c227f099 | Anthony Liguori | static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
86 | cdbdb648 | pbrook | uint32_t value) |
87 | cdbdb648 | pbrook | { |
88 | cdbdb648 | pbrook | vpb_sic_state *s = (vpb_sic_state *)opaque; |
89 | cdbdb648 | pbrook | |
90 | cdbdb648 | pbrook | switch (offset >> 2) { |
91 | cdbdb648 | pbrook | case 2: /* ENSET */ |
92 | cdbdb648 | pbrook | s->mask |= value; |
93 | cdbdb648 | pbrook | break;
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94 | cdbdb648 | pbrook | case 3: /* ENCLR */ |
95 | cdbdb648 | pbrook | s->mask &= ~value; |
96 | cdbdb648 | pbrook | break;
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97 | cdbdb648 | pbrook | case 4: /* SOFTINTSET */ |
98 | cdbdb648 | pbrook | if (value)
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99 | cdbdb648 | pbrook | s->mask |= 1;
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100 | cdbdb648 | pbrook | break;
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101 | cdbdb648 | pbrook | case 5: /* SOFTINTCLR */ |
102 | cdbdb648 | pbrook | if (value)
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103 | cdbdb648 | pbrook | s->mask &= ~1u;
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104 | cdbdb648 | pbrook | break;
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105 | cdbdb648 | pbrook | case 8: /* PICENSET */ |
106 | cdbdb648 | pbrook | s->pic_enable |= (value & 0x7fe00000);
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107 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
108 | cdbdb648 | pbrook | break;
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109 | cdbdb648 | pbrook | case 9: /* PICENCLR */ |
110 | cdbdb648 | pbrook | s->pic_enable &= ~value; |
111 | cdbdb648 | pbrook | vpb_sic_update_pic(s); |
112 | cdbdb648 | pbrook | break;
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113 | cdbdb648 | pbrook | default:
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114 | e69954b9 | pbrook | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
115 | cdbdb648 | pbrook | return;
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116 | cdbdb648 | pbrook | } |
117 | cdbdb648 | pbrook | vpb_sic_update(s); |
118 | cdbdb648 | pbrook | } |
119 | cdbdb648 | pbrook | |
120 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const vpb_sic_readfn[] = { |
121 | cdbdb648 | pbrook | vpb_sic_read, |
122 | cdbdb648 | pbrook | vpb_sic_read, |
123 | cdbdb648 | pbrook | vpb_sic_read |
124 | cdbdb648 | pbrook | }; |
125 | cdbdb648 | pbrook | |
126 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const vpb_sic_writefn[] = { |
127 | cdbdb648 | pbrook | vpb_sic_write, |
128 | cdbdb648 | pbrook | vpb_sic_write, |
129 | cdbdb648 | pbrook | vpb_sic_write |
130 | cdbdb648 | pbrook | }; |
131 | cdbdb648 | pbrook | |
132 | 81a322d4 | Gerd Hoffmann | static int vpb_sic_init(SysBusDevice *dev) |
133 | cdbdb648 | pbrook | { |
134 | 3950f18b | Paul Brook | vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev); |
135 | cdbdb648 | pbrook | int iomemtype;
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136 | 97aff481 | Paul Brook | int i;
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137 | cdbdb648 | pbrook | |
138 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
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139 | 97aff481 | Paul Brook | for (i = 0; i < 32; i++) { |
140 | 3950f18b | Paul Brook | sysbus_init_irq(dev, &s->parent[i]); |
141 | 97aff481 | Paul Brook | } |
142 | 3950f18b | Paul Brook | s->irq = 31;
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143 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(vpb_sic_readfn, |
144 | cdbdb648 | pbrook | vpb_sic_writefn, s); |
145 | 3950f18b | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
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146 | cdbdb648 | pbrook | /* ??? Save/restore. */
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147 | 81a322d4 | Gerd Hoffmann | return 0; |
148 | cdbdb648 | pbrook | } |
149 | cdbdb648 | pbrook | |
150 | cdbdb648 | pbrook | /* Board init. */
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151 | cdbdb648 | pbrook | |
152 | 16406950 | pbrook | /* The AB and PB boards both use the same core, just with different
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153 | 16406950 | pbrook | peripherans and expansion busses. For now we emulate a subset of the
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154 | 16406950 | pbrook | PB peripherals and just change the board ID. */
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155 | cdbdb648 | pbrook | |
156 | f93eb9ff | balrog | static struct arm_boot_info versatile_binfo; |
157 | f93eb9ff | balrog | |
158 | c227f099 | Anthony Liguori | static void versatile_init(ram_addr_t ram_size, |
159 | 3023f332 | aliguori | const char *boot_device, |
160 | cdbdb648 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
161 | 3371d272 | pbrook | const char *initrd_filename, const char *cpu_model, |
162 | 3371d272 | pbrook | int board_id)
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163 | cdbdb648 | pbrook | { |
164 | cdbdb648 | pbrook | CPUState *env; |
165 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
166 | 97aff481 | Paul Brook | qemu_irq *cpu_pic; |
167 | 97aff481 | Paul Brook | qemu_irq pic[32];
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168 | 3950f18b | Paul Brook | qemu_irq sic[32];
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169 | 97aff481 | Paul Brook | DeviceState *dev; |
170 | 502a5395 | pbrook | PCIBus *pci_bus; |
171 | 502a5395 | pbrook | NICInfo *nd; |
172 | 502a5395 | pbrook | int n;
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173 | 502a5395 | pbrook | int done_smc = 0; |
174 | cdbdb648 | pbrook | |
175 | 3371d272 | pbrook | if (!cpu_model)
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176 | 3371d272 | pbrook | cpu_model = "arm926";
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177 | aaed909a | bellard | env = cpu_init(cpu_model); |
178 | aaed909a | bellard | if (!env) {
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179 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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180 | aaed909a | bellard | exit(1);
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181 | aaed909a | bellard | } |
182 | 7ffab4d7 | pbrook | ram_offset = qemu_ram_alloc(ram_size); |
183 | 1235fc06 | ths | /* ??? RAM should repeat to fill physical memory space. */
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184 | cdbdb648 | pbrook | /* SDRAM at address zero. */
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185 | 7ffab4d7 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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186 | cdbdb648 | pbrook | |
187 | e69954b9 | pbrook | arm_sysctl_init(0x10000000, 0x41007004); |
188 | 97aff481 | Paul Brook | cpu_pic = arm_pic_init_cpu(env); |
189 | 97aff481 | Paul Brook | dev = sysbus_create_varargs("pl190", 0x10140000, |
190 | 97aff481 | Paul Brook | cpu_pic[0], cpu_pic[1], NULL); |
191 | 97aff481 | Paul Brook | for (n = 0; n < 32; n++) { |
192 | 067a3ddc | Paul Brook | pic[n] = qdev_get_gpio_in(dev, n); |
193 | 97aff481 | Paul Brook | } |
194 | 3950f18b | Paul Brook | dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); |
195 | 3950f18b | Paul Brook | for (n = 0; n < 32; n++) { |
196 | 3950f18b | Paul Brook | sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]); |
197 | 067a3ddc | Paul Brook | sic[n] = qdev_get_gpio_in(dev, n); |
198 | 3950f18b | Paul Brook | } |
199 | 86394e96 | Paul Brook | |
200 | 86394e96 | Paul Brook | sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); |
201 | 86394e96 | Paul Brook | sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); |
202 | cdbdb648 | pbrook | |
203 | 0027b06d | Paul Brook | dev = sysbus_create_varargs("versatile_pci", 0x40000000, |
204 | 0027b06d | Paul Brook | sic[27], sic[28], sic[29], sic[30], NULL); |
205 | 02e2da45 | Paul Brook | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
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206 | 0027b06d | Paul Brook | |
207 | 502a5395 | pbrook | /* The Versatile PCI bridge does not provide access to PCI IO space,
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208 | 502a5395 | pbrook | so many of the qemu PCI devices are not useable. */
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209 | 502a5395 | pbrook | for(n = 0; n < nb_nics; n++) { |
210 | 502a5395 | pbrook | nd = &nd_table[n]; |
211 | 0ae18cee | aliguori | |
212 | 0ae18cee | aliguori | if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { |
213 | d537cf6c | pbrook | smc91c111_init(nd, 0x10010000, sic[25]); |
214 | 0ae18cee | aliguori | done_smc = 1;
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215 | cdbdb648 | pbrook | } else {
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216 | 5607c388 | Markus Armbruster | pci_nic_init(nd, "rtl8139", NULL); |
217 | cdbdb648 | pbrook | } |
218 | cdbdb648 | pbrook | } |
219 | 0d92ed30 | pbrook | if (usb_enabled) {
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220 | 5b19d9a2 | Gerd Hoffmann | usb_ohci_init_pci(pci_bus, -1);
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221 | 0d92ed30 | pbrook | } |
222 | 9be5dafe | Paul Brook | n = drive_get_max_bus(IF_SCSI); |
223 | 9be5dafe | Paul Brook | while (n >= 0) { |
224 | 9be5dafe | Paul Brook | pci_create_simple(pci_bus, -1, "lsi53c895a"); |
225 | 9be5dafe | Paul Brook | n--; |
226 | 7d8406be | pbrook | } |
227 | cdbdb648 | pbrook | |
228 | a7d518a6 | Paul Brook | sysbus_create_simple("pl011", 0x101f1000, pic[12]); |
229 | a7d518a6 | Paul Brook | sysbus_create_simple("pl011", 0x101f2000, pic[13]); |
230 | a7d518a6 | Paul Brook | sysbus_create_simple("pl011", 0x101f3000, pic[14]); |
231 | a7d518a6 | Paul Brook | sysbus_create_simple("pl011", 0x10009000, sic[6]); |
232 | cdbdb648 | pbrook | |
233 | b4496b13 | Paul Brook | sysbus_create_simple("pl080", 0x10130000, pic[17]); |
234 | 6a824ec3 | Paul Brook | sysbus_create_simple("sp804", 0x101e2000, pic[4]); |
235 | 6a824ec3 | Paul Brook | sysbus_create_simple("sp804", 0x101e3000, pic[5]); |
236 | cdbdb648 | pbrook | |
237 | cdbdb648 | pbrook | /* The versatile/PB actually has a modified Color LCD controller
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238 | cdbdb648 | pbrook | that includes hardware cursor support from the PL111. */
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239 | 2e9bdce5 | Paul Brook | sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); |
240 | cdbdb648 | pbrook | |
241 | aa9311d8 | Paul Brook | sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); |
242 | aa9311d8 | Paul Brook | sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); |
243 | a1bb27b1 | pbrook | |
244 | 7e1543c2 | pbrook | /* Add PL031 Real Time Clock. */
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245 | a63bdb31 | Paul Brook | sysbus_create_simple("pl031", 0x101e8000, pic[10]); |
246 | 7e1543c2 | pbrook | |
247 | 16406950 | pbrook | /* Memory map for Versatile/PB: */
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248 | cdbdb648 | pbrook | /* 0x10000000 System registers. */
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249 | cdbdb648 | pbrook | /* 0x10001000 PCI controller config registers. */
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250 | cdbdb648 | pbrook | /* 0x10002000 Serial bus interface. */
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251 | cdbdb648 | pbrook | /* 0x10003000 Secondary interrupt controller. */
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252 | cdbdb648 | pbrook | /* 0x10004000 AACI (audio). */
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253 | a1bb27b1 | pbrook | /* 0x10005000 MMCI0. */
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254 | cdbdb648 | pbrook | /* 0x10006000 KMI0 (keyboard). */
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255 | cdbdb648 | pbrook | /* 0x10007000 KMI1 (mouse). */
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256 | cdbdb648 | pbrook | /* 0x10008000 Character LCD Interface. */
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257 | cdbdb648 | pbrook | /* 0x10009000 UART3. */
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258 | cdbdb648 | pbrook | /* 0x1000a000 Smart card 1. */
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259 | a1bb27b1 | pbrook | /* 0x1000b000 MMCI1. */
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260 | cdbdb648 | pbrook | /* 0x10010000 Ethernet. */
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261 | cdbdb648 | pbrook | /* 0x10020000 USB. */
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262 | cdbdb648 | pbrook | /* 0x10100000 SSMC. */
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263 | cdbdb648 | pbrook | /* 0x10110000 MPMC. */
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264 | cdbdb648 | pbrook | /* 0x10120000 CLCD Controller. */
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265 | cdbdb648 | pbrook | /* 0x10130000 DMA Controller. */
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266 | cdbdb648 | pbrook | /* 0x10140000 Vectored interrupt controller. */
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267 | cdbdb648 | pbrook | /* 0x101d0000 AHB Monitor Interface. */
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268 | cdbdb648 | pbrook | /* 0x101e0000 System Controller. */
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269 | cdbdb648 | pbrook | /* 0x101e1000 Watchdog Interface. */
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270 | cdbdb648 | pbrook | /* 0x101e2000 Timer 0/1. */
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271 | cdbdb648 | pbrook | /* 0x101e3000 Timer 2/3. */
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272 | cdbdb648 | pbrook | /* 0x101e4000 GPIO port 0. */
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273 | cdbdb648 | pbrook | /* 0x101e5000 GPIO port 1. */
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274 | cdbdb648 | pbrook | /* 0x101e6000 GPIO port 2. */
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275 | cdbdb648 | pbrook | /* 0x101e7000 GPIO port 3. */
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276 | cdbdb648 | pbrook | /* 0x101e8000 RTC. */
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277 | cdbdb648 | pbrook | /* 0x101f0000 Smart card 0. */
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278 | cdbdb648 | pbrook | /* 0x101f1000 UART0. */
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279 | cdbdb648 | pbrook | /* 0x101f2000 UART1. */
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280 | cdbdb648 | pbrook | /* 0x101f3000 UART2. */
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281 | cdbdb648 | pbrook | /* 0x101f4000 SSPI. */
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282 | cdbdb648 | pbrook | |
283 | f93eb9ff | balrog | versatile_binfo.ram_size = ram_size; |
284 | f93eb9ff | balrog | versatile_binfo.kernel_filename = kernel_filename; |
285 | f93eb9ff | balrog | versatile_binfo.kernel_cmdline = kernel_cmdline; |
286 | f93eb9ff | balrog | versatile_binfo.initrd_filename = initrd_filename; |
287 | f93eb9ff | balrog | versatile_binfo.board_id = board_id; |
288 | f93eb9ff | balrog | arm_load_kernel(env, &versatile_binfo); |
289 | 16406950 | pbrook | } |
290 | 16406950 | pbrook | |
291 | c227f099 | Anthony Liguori | static void vpb_init(ram_addr_t ram_size, |
292 | 3023f332 | aliguori | const char *boot_device, |
293 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
294 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
295 | 16406950 | pbrook | { |
296 | fbe1b595 | Paul Brook | versatile_init(ram_size, |
297 | 3023f332 | aliguori | boot_device, |
298 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
299 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x183);
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300 | 16406950 | pbrook | } |
301 | 16406950 | pbrook | |
302 | c227f099 | Anthony Liguori | static void vab_init(ram_addr_t ram_size, |
303 | 3023f332 | aliguori | const char *boot_device, |
304 | 16406950 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
305 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
306 | 16406950 | pbrook | { |
307 | fbe1b595 | Paul Brook | versatile_init(ram_size, |
308 | 3023f332 | aliguori | boot_device, |
309 | 16406950 | pbrook | kernel_filename, kernel_cmdline, |
310 | 3371d272 | pbrook | initrd_filename, cpu_model, 0x25e);
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311 | cdbdb648 | pbrook | } |
312 | cdbdb648 | pbrook | |
313 | f80f9ec9 | Anthony Liguori | static QEMUMachine versatilepb_machine = {
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314 | c9b1ae2c | blueswir1 | .name = "versatilepb",
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315 | c9b1ae2c | blueswir1 | .desc = "ARM Versatile/PB (ARM926EJ-S)",
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316 | c9b1ae2c | blueswir1 | .init = vpb_init, |
317 | c9b1ae2c | blueswir1 | .use_scsi = 1,
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318 | cdbdb648 | pbrook | }; |
319 | 16406950 | pbrook | |
320 | f80f9ec9 | Anthony Liguori | static QEMUMachine versatileab_machine = {
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321 | c9b1ae2c | blueswir1 | .name = "versatileab",
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322 | c9b1ae2c | blueswir1 | .desc = "ARM Versatile/AB (ARM926EJ-S)",
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323 | c9b1ae2c | blueswir1 | .init = vab_init, |
324 | c9b1ae2c | blueswir1 | .use_scsi = 1,
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325 | 16406950 | pbrook | }; |
326 | 3950f18b | Paul Brook | |
327 | f80f9ec9 | Anthony Liguori | static void versatile_machine_init(void) |
328 | f80f9ec9 | Anthony Liguori | { |
329 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&versatilepb_machine); |
330 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&versatileab_machine); |
331 | f80f9ec9 | Anthony Liguori | } |
332 | f80f9ec9 | Anthony Liguori | |
333 | f80f9ec9 | Anthony Liguori | machine_init(versatile_machine_init); |
334 | f80f9ec9 | Anthony Liguori | |
335 | 3950f18b | Paul Brook | static void versatilepb_register_devices(void) |
336 | 3950f18b | Paul Brook | { |
337 | 3950f18b | Paul Brook | sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state), |
338 | 3950f18b | Paul Brook | vpb_sic_init); |
339 | 3950f18b | Paul Brook | } |
340 | 3950f18b | Paul Brook | |
341 | 3950f18b | Paul Brook | device_init(versatilepb_register_devices) |