root / hw / ioapic.c @ c0b1905b
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/*
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* ioapic.c IOAPIC emulation logic
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* Split the ioapic logic from apic.c
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "host-utils.h" |
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//#define DEBUG_IOAPIC
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#define IOAPIC_NUM_PINS 0x18 |
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#define IOAPIC_LVT_MASKED (1<<16) |
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#define IOAPIC_TRIGGER_EDGE 0 |
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#define IOAPIC_TRIGGER_LEVEL 1 |
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/*io{apic,sapic} delivery mode*/
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#define IOAPIC_DM_FIXED 0x0 |
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#define IOAPIC_DM_LOWEST_PRIORITY 0x1 |
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#define IOAPIC_DM_PMI 0x2 |
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#define IOAPIC_DM_NMI 0x4 |
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#define IOAPIC_DM_INIT 0x5 |
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#define IOAPIC_DM_SIPI 0x5 |
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#define IOAPIC_DM_EXTINT 0x7 |
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struct IOAPICState {
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uint8_t id; |
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uint8_t ioregsel; |
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uint32_t irr; |
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uint64_t ioredtbl[IOAPIC_NUM_PINS]; |
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}; |
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static void ioapic_service(IOAPICState *s) |
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{ |
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uint8_t i; |
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uint8_t trig_mode; |
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uint8_t vector; |
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uint8_t delivery_mode; |
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uint32_t mask; |
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uint64_t entry; |
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uint8_t dest; |
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uint8_t dest_mode; |
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uint8_t polarity; |
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for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
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mask = 1 << i;
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if (s->irr & mask) {
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entry = s->ioredtbl[i]; |
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if (!(entry & IOAPIC_LVT_MASKED)) {
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trig_mode = ((entry >> 15) & 1); |
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dest = entry >> 56;
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dest_mode = (entry >> 11) & 1; |
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delivery_mode = (entry >> 8) & 7; |
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polarity = (entry >> 13) & 1; |
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if (trig_mode == IOAPIC_TRIGGER_EDGE)
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s->irr &= ~mask; |
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if (delivery_mode == IOAPIC_DM_EXTINT)
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vector = pic_read_irq(isa_pic); |
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else
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vector = entry & 0xff;
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apic_deliver_irq(dest, dest_mode, delivery_mode, |
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vector, polarity, trig_mode); |
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} |
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} |
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} |
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} |
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void ioapic_set_irq(void *opaque, int vector, int level) |
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{ |
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IOAPICState *s = opaque; |
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/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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if (vector == 0) |
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vector = 2;
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if (vector >= 0 && vector < IOAPIC_NUM_PINS) { |
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uint32_t mask = 1 << vector;
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uint64_t entry = s->ioredtbl[vector]; |
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if ((entry >> 15) & 1) { |
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/* level triggered */
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if (level) {
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s->irr |= mask; |
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ioapic_service(s); |
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} else {
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s->irr &= ~mask; |
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} |
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} else {
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/* edge triggered */
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if (level) {
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s->irr |= mask; |
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ioapic_service(s); |
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} |
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} |
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} |
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} |
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static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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IOAPICState *s = opaque; |
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int index;
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uint32_t val = 0;
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addr &= 0xff;
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if (addr == 0x00) { |
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val = s->ioregsel; |
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} else if (addr == 0x10) { |
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switch (s->ioregsel) {
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case 0x00: |
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val = s->id << 24;
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break;
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case 0x01: |
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val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ |
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break;
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case 0x02: |
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val = 0;
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break;
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default:
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index = (s->ioregsel - 0x10) >> 1; |
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if (index >= 0 && index < IOAPIC_NUM_PINS) { |
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if (s->ioregsel & 1) |
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val = s->ioredtbl[index] >> 32;
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else
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val = s->ioredtbl[index] & 0xffffffff;
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} |
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} |
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#ifdef DEBUG_IOAPIC
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printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
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#endif
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} |
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return val;
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} |
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static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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IOAPICState *s = opaque; |
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int index;
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addr &= 0xff;
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if (addr == 0x00) { |
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s->ioregsel = val; |
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return;
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} else if (addr == 0x10) { |
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#ifdef DEBUG_IOAPIC
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printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
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#endif
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switch (s->ioregsel) {
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case 0x00: |
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s->id = (val >> 24) & 0xff; |
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return;
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case 0x01: |
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case 0x02: |
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return;
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default:
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index = (s->ioregsel - 0x10) >> 1; |
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if (index >= 0 && index < IOAPIC_NUM_PINS) { |
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if (s->ioregsel & 1) { |
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s->ioredtbl[index] &= 0xffffffff;
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s->ioredtbl[index] |= (uint64_t)val << 32;
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} else {
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s->ioredtbl[index] &= ~0xffffffffULL;
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s->ioredtbl[index] |= val; |
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} |
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ioapic_service(s); |
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} |
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} |
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} |
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} |
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static const VMStateDescription vmstate_ioapic = { |
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.name = "ioapic",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_UINT8(id, IOAPICState), |
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VMSTATE_UINT8(ioregsel, IOAPICState), |
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VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static void ioapic_reset(void *opaque) |
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{ |
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IOAPICState *s = opaque; |
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int i;
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memset(s, 0, sizeof(*s)); |
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for(i = 0; i < IOAPIC_NUM_PINS; i++) |
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s->ioredtbl[i] = 1 << 16; /* mask LVT */ |
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} |
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static CPUReadMemoryFunc * const ioapic_mem_read[3] = { |
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ioapic_mem_readl, |
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ioapic_mem_readl, |
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ioapic_mem_readl, |
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}; |
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static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { |
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ioapic_mem_writel, |
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ioapic_mem_writel, |
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ioapic_mem_writel, |
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}; |
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qemu_irq *ioapic_init(void)
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{ |
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IOAPICState *s; |
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qemu_irq *irq; |
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int io_memory;
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s = qemu_mallocz(sizeof(IOAPICState));
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ioapic_reset(s); |
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io_memory = cpu_register_io_memory(ioapic_mem_read, |
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ioapic_mem_write, s); |
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cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); |
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vmstate_register(0, &vmstate_ioapic, s);
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qemu_register_reset(ioapic_reset, s); |
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irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS); |
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return irq;
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} |