root / hw / eccmemctl.c @ c0b5b109
History | View | Annotate | Download (10.5 kB)
1 | 7eb0c8e8 | blueswir1 | /*
|
---|---|---|---|
2 | 7eb0c8e8 | blueswir1 | * QEMU Sparc Sun4m ECC memory controller emulation
|
3 | 7eb0c8e8 | blueswir1 | *
|
4 | 7eb0c8e8 | blueswir1 | * Copyright (c) 2007 Robert Reif
|
5 | 7eb0c8e8 | blueswir1 | *
|
6 | 7eb0c8e8 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 7eb0c8e8 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
|
8 | 7eb0c8e8 | blueswir1 | * in the Software without restriction, including without limitation the rights
|
9 | 7eb0c8e8 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 7eb0c8e8 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
|
11 | 7eb0c8e8 | blueswir1 | * furnished to do so, subject to the following conditions:
|
12 | 7eb0c8e8 | blueswir1 | *
|
13 | 7eb0c8e8 | blueswir1 | * The above copyright notice and this permission notice shall be included in
|
14 | 7eb0c8e8 | blueswir1 | * all copies or substantial portions of the Software.
|
15 | 7eb0c8e8 | blueswir1 | *
|
16 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 7eb0c8e8 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 7eb0c8e8 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 7eb0c8e8 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 7eb0c8e8 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 7eb0c8e8 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 7eb0c8e8 | blueswir1 | * THE SOFTWARE.
|
23 | 7eb0c8e8 | blueswir1 | */
|
24 | 7eb0c8e8 | blueswir1 | #include "hw.h" |
25 | 7eb0c8e8 | blueswir1 | #include "sun4m.h" |
26 | 7eb0c8e8 | blueswir1 | #include "sysemu.h" |
27 | 7eb0c8e8 | blueswir1 | |
28 | 7eb0c8e8 | blueswir1 | //#define DEBUG_ECC
|
29 | 7eb0c8e8 | blueswir1 | |
30 | 7eb0c8e8 | blueswir1 | #ifdef DEBUG_ECC
|
31 | 7eb0c8e8 | blueswir1 | #define DPRINTF(fmt, args...) \
|
32 | 7eb0c8e8 | blueswir1 | do { printf("ECC: " fmt , ##args); } while (0) |
33 | 7eb0c8e8 | blueswir1 | #else
|
34 | 7eb0c8e8 | blueswir1 | #define DPRINTF(fmt, args...)
|
35 | 7eb0c8e8 | blueswir1 | #endif
|
36 | 7eb0c8e8 | blueswir1 | |
37 | 7eb0c8e8 | blueswir1 | /* There are 3 versions of this chip used in SMP sun4m systems:
|
38 | 7eb0c8e8 | blueswir1 | * MCC (version 0, implementation 0) SS-600MP
|
39 | 7eb0c8e8 | blueswir1 | * EMC (version 0, implementation 1) SS-10
|
40 | 7eb0c8e8 | blueswir1 | * SMC (version 0, implementation 2) SS-10SX and SS-20
|
41 | 7eb0c8e8 | blueswir1 | */
|
42 | 7eb0c8e8 | blueswir1 | |
43 | 8f2ad0a3 | blueswir1 | /* Register indexes */
|
44 | 8f2ad0a3 | blueswir1 | #define ECC_MER 0 /* Memory Enable Register */ |
45 | 8f2ad0a3 | blueswir1 | #define ECC_MDR 1 /* Memory Delay Register */ |
46 | 8f2ad0a3 | blueswir1 | #define ECC_MFSR 2 /* Memory Fault Status Register */ |
47 | 8f2ad0a3 | blueswir1 | #define ECC_VCR 3 /* Video Configuration Register */ |
48 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
49 | 8f2ad0a3 | blueswir1 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
50 | 8f2ad0a3 | blueswir1 | #define ECC_DR 6 /* Diagnostic Register */ |
51 | 8f2ad0a3 | blueswir1 | #define ECC_ECR0 7 /* Event Count Register 0 */ |
52 | 8f2ad0a3 | blueswir1 | #define ECC_ECR1 8 /* Event Count Register 1 */ |
53 | 7eb0c8e8 | blueswir1 | |
54 | 7eb0c8e8 | blueswir1 | /* ECC fault control register */
|
55 | dd53ded3 | blueswir1 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
56 | 77f193da | blueswir1 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
57 | 77f193da | blueswir1 | correctable errors */
|
58 | dd53ded3 | blueswir1 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
59 | dd53ded3 | blueswir1 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
60 | dd53ded3 | blueswir1 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
61 | dd53ded3 | blueswir1 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
62 | dd53ded3 | blueswir1 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
63 | dd53ded3 | blueswir1 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
64 | dd53ded3 | blueswir1 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
65 | dd53ded3 | blueswir1 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
66 | dd53ded3 | blueswir1 | #define ECC_MER_REU 0x00000200 /* Memory Refresh Enable (600MP) */ |
67 | dd53ded3 | blueswir1 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
68 | dd53ded3 | blueswir1 | #define ECC_MEM_A 0x00000400 /* Memory controller addr map select */ |
69 | 77f193da | blueswir1 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
70 | dd53ded3 | blueswir1 | #define ECC_MER_VER 0x0f000000 /* Version */ |
71 | dd53ded3 | blueswir1 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
72 | dd53ded3 | blueswir1 | |
73 | dd53ded3 | blueswir1 | /* ECC memory delay register */
|
74 | dd53ded3 | blueswir1 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
75 | dd53ded3 | blueswir1 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
76 | dd53ded3 | blueswir1 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
77 | dd53ded3 | blueswir1 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
78 | dd53ded3 | blueswir1 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
79 | dd53ded3 | blueswir1 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
80 | dd53ded3 | blueswir1 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
81 | dd53ded3 | blueswir1 | #define ECC_MDR_MASK 0x7fffffff |
82 | 7eb0c8e8 | blueswir1 | |
83 | 7eb0c8e8 | blueswir1 | /* ECC fault status register */
|
84 | dd53ded3 | blueswir1 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
85 | dd53ded3 | blueswir1 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
86 | dd53ded3 | blueswir1 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
87 | dd53ded3 | blueswir1 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
88 | dd53ded3 | blueswir1 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
89 | dd53ded3 | blueswir1 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
90 | dd53ded3 | blueswir1 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
91 | dd53ded3 | blueswir1 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
92 | 7eb0c8e8 | blueswir1 | |
93 | 7eb0c8e8 | blueswir1 | /* ECC fault address register 0 */
|
94 | dd53ded3 | blueswir1 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
95 | dd53ded3 | blueswir1 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
96 | dd53ded3 | blueswir1 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
97 | dd53ded3 | blueswir1 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
98 | dd53ded3 | blueswir1 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
99 | dd53ded3 | blueswir1 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
100 | dd53ded3 | blueswir1 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
101 | dd53ded3 | blueswir1 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
102 | dd53ded3 | blueswir1 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
103 | 7eb0c8e8 | blueswir1 | |
104 | 7eb0c8e8 | blueswir1 | /* ECC diagnostic register */
|
105 | dd53ded3 | blueswir1 | #define ECC_DR_CBX 0x00000001 |
106 | dd53ded3 | blueswir1 | #define ECC_DR_CB0 0x00000002 |
107 | dd53ded3 | blueswir1 | #define ECC_DR_CB1 0x00000004 |
108 | dd53ded3 | blueswir1 | #define ECC_DR_CB2 0x00000008 |
109 | dd53ded3 | blueswir1 | #define ECC_DR_CB4 0x00000010 |
110 | dd53ded3 | blueswir1 | #define ECC_DR_CB8 0x00000020 |
111 | dd53ded3 | blueswir1 | #define ECC_DR_CB16 0x00000040 |
112 | dd53ded3 | blueswir1 | #define ECC_DR_CB32 0x00000080 |
113 | dd53ded3 | blueswir1 | #define ECC_DR_DMODE 0x00000c00 |
114 | dd53ded3 | blueswir1 | |
115 | dd53ded3 | blueswir1 | #define ECC_NREGS 9 |
116 | 7eb0c8e8 | blueswir1 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
117 | dd53ded3 | blueswir1 | #define ECC_ADDR_MASK 0x1f |
118 | dd53ded3 | blueswir1 | |
119 | dd53ded3 | blueswir1 | #define ECC_DIAG_SIZE 4 |
120 | dd53ded3 | blueswir1 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
121 | 7eb0c8e8 | blueswir1 | |
122 | 7eb0c8e8 | blueswir1 | typedef struct ECCState { |
123 | e42c20b4 | blueswir1 | qemu_irq irq; |
124 | 7eb0c8e8 | blueswir1 | uint32_t regs[ECC_NREGS]; |
125 | dd53ded3 | blueswir1 | uint8_t diag[ECC_DIAG_SIZE]; |
126 | 7eb0c8e8 | blueswir1 | } ECCState; |
127 | 7eb0c8e8 | blueswir1 | |
128 | 7eb0c8e8 | blueswir1 | static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
129 | 7eb0c8e8 | blueswir1 | { |
130 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
131 | 7eb0c8e8 | blueswir1 | |
132 | 8f2ad0a3 | blueswir1 | switch ((addr & ECC_ADDR_MASK) >> 2) { |
133 | dd53ded3 | blueswir1 | case ECC_MER:
|
134 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER | ECC_MER_IMPL)) | |
135 | 8f2ad0a3 | blueswir1 | (val & ~(ECC_MER_VER | ECC_MER_IMPL)); |
136 | dd53ded3 | blueswir1 | DPRINTF("Write memory enable %08x\n", val);
|
137 | 7eb0c8e8 | blueswir1 | break;
|
138 | dd53ded3 | blueswir1 | case ECC_MDR:
|
139 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
140 | dd53ded3 | blueswir1 | DPRINTF("Write memory delay %08x\n", val);
|
141 | 7eb0c8e8 | blueswir1 | break;
|
142 | dd53ded3 | blueswir1 | case ECC_MFSR:
|
143 | 8f2ad0a3 | blueswir1 | s->regs[ECC_MFSR] = val; |
144 | dd53ded3 | blueswir1 | DPRINTF("Write memory fault status %08x\n", val);
|
145 | 7eb0c8e8 | blueswir1 | break;
|
146 | dd53ded3 | blueswir1 | case ECC_VCR:
|
147 | 8f2ad0a3 | blueswir1 | s->regs[ECC_VCR] = val; |
148 | dd53ded3 | blueswir1 | DPRINTF("Write slot configuration %08x\n", val);
|
149 | 7eb0c8e8 | blueswir1 | break;
|
150 | dd53ded3 | blueswir1 | case ECC_DR:
|
151 | 8f2ad0a3 | blueswir1 | s->regs[ECC_DR] = val; |
152 | dd53ded3 | blueswir1 | DPRINTF("Write diagnosiic %08x\n", val);
|
153 | dd53ded3 | blueswir1 | break;
|
154 | dd53ded3 | blueswir1 | case ECC_ECR0:
|
155 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
156 | dd53ded3 | blueswir1 | DPRINTF("Write event count 1 %08x\n", val);
|
157 | 7eb0c8e8 | blueswir1 | break;
|
158 | dd53ded3 | blueswir1 | case ECC_ECR1:
|
159 | 8f2ad0a3 | blueswir1 | s->regs[ECC_ECR0] = val; |
160 | dd53ded3 | blueswir1 | DPRINTF("Write event count 2 %08x\n", val);
|
161 | 7eb0c8e8 | blueswir1 | break;
|
162 | 7eb0c8e8 | blueswir1 | } |
163 | 7eb0c8e8 | blueswir1 | } |
164 | 7eb0c8e8 | blueswir1 | |
165 | 7eb0c8e8 | blueswir1 | static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) |
166 | 7eb0c8e8 | blueswir1 | { |
167 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
168 | 7eb0c8e8 | blueswir1 | uint32_t ret = 0;
|
169 | 7eb0c8e8 | blueswir1 | |
170 | 8f2ad0a3 | blueswir1 | switch ((addr & ECC_ADDR_MASK) >> 2) { |
171 | dd53ded3 | blueswir1 | case ECC_MER:
|
172 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MER]; |
173 | dd53ded3 | blueswir1 | DPRINTF("Read memory enable %08x\n", ret);
|
174 | 7eb0c8e8 | blueswir1 | break;
|
175 | dd53ded3 | blueswir1 | case ECC_MDR:
|
176 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MDR]; |
177 | dd53ded3 | blueswir1 | DPRINTF("Read memory delay %08x\n", ret);
|
178 | 7eb0c8e8 | blueswir1 | break;
|
179 | dd53ded3 | blueswir1 | case ECC_MFSR:
|
180 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFSR]; |
181 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault status %08x\n", ret);
|
182 | 7eb0c8e8 | blueswir1 | break;
|
183 | dd53ded3 | blueswir1 | case ECC_VCR:
|
184 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_VCR]; |
185 | dd53ded3 | blueswir1 | DPRINTF("Read slot configuration %08x\n", ret);
|
186 | 7eb0c8e8 | blueswir1 | break;
|
187 | dd53ded3 | blueswir1 | case ECC_MFAR0:
|
188 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR0]; |
189 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault address 0 %08x\n", ret);
|
190 | 7eb0c8e8 | blueswir1 | break;
|
191 | dd53ded3 | blueswir1 | case ECC_MFAR1:
|
192 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_MFAR1]; |
193 | dd53ded3 | blueswir1 | DPRINTF("Read memory fault address 1 %08x\n", ret);
|
194 | 7eb0c8e8 | blueswir1 | break;
|
195 | dd53ded3 | blueswir1 | case ECC_DR:
|
196 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_DR]; |
197 | dd53ded3 | blueswir1 | DPRINTF("Read diagnostic %08x\n", ret);
|
198 | 7eb0c8e8 | blueswir1 | break;
|
199 | dd53ded3 | blueswir1 | case ECC_ECR0:
|
200 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
201 | dd53ded3 | blueswir1 | DPRINTF("Read event count 1 %08x\n", ret);
|
202 | dd53ded3 | blueswir1 | break;
|
203 | dd53ded3 | blueswir1 | case ECC_ECR1:
|
204 | 8f2ad0a3 | blueswir1 | ret = s->regs[ECC_ECR0]; |
205 | dd53ded3 | blueswir1 | DPRINTF("Read event count 2 %08x\n", ret);
|
206 | 7eb0c8e8 | blueswir1 | break;
|
207 | 7eb0c8e8 | blueswir1 | } |
208 | 7eb0c8e8 | blueswir1 | return ret;
|
209 | 7eb0c8e8 | blueswir1 | } |
210 | 7eb0c8e8 | blueswir1 | |
211 | 7eb0c8e8 | blueswir1 | static CPUReadMemoryFunc *ecc_mem_read[3] = { |
212 | 7c560456 | blueswir1 | NULL,
|
213 | 7c560456 | blueswir1 | NULL,
|
214 | 7eb0c8e8 | blueswir1 | ecc_mem_readl, |
215 | 7eb0c8e8 | blueswir1 | }; |
216 | 7eb0c8e8 | blueswir1 | |
217 | 7eb0c8e8 | blueswir1 | static CPUWriteMemoryFunc *ecc_mem_write[3] = { |
218 | 7c560456 | blueswir1 | NULL,
|
219 | 7c560456 | blueswir1 | NULL,
|
220 | 7eb0c8e8 | blueswir1 | ecc_mem_writel, |
221 | 7eb0c8e8 | blueswir1 | }; |
222 | 7eb0c8e8 | blueswir1 | |
223 | dd53ded3 | blueswir1 | static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
224 | dd53ded3 | blueswir1 | uint32_t val) |
225 | dd53ded3 | blueswir1 | { |
226 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
227 | dd53ded3 | blueswir1 | |
228 | dd53ded3 | blueswir1 | DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val); |
229 | dd53ded3 | blueswir1 | s->diag[addr & ECC_DIAG_MASK] = val; |
230 | dd53ded3 | blueswir1 | } |
231 | dd53ded3 | blueswir1 | |
232 | dd53ded3 | blueswir1 | static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
233 | dd53ded3 | blueswir1 | { |
234 | dd53ded3 | blueswir1 | ECCState *s = opaque; |
235 | dd53ded3 | blueswir1 | uint32_t ret = s->diag[addr & ECC_DIAG_MASK]; |
236 | dd53ded3 | blueswir1 | DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret); |
237 | dd53ded3 | blueswir1 | return ret;
|
238 | dd53ded3 | blueswir1 | } |
239 | dd53ded3 | blueswir1 | |
240 | dd53ded3 | blueswir1 | static CPUReadMemoryFunc *ecc_diag_mem_read[3] = { |
241 | dd53ded3 | blueswir1 | ecc_diag_mem_readb, |
242 | dd53ded3 | blueswir1 | NULL,
|
243 | dd53ded3 | blueswir1 | NULL,
|
244 | dd53ded3 | blueswir1 | }; |
245 | dd53ded3 | blueswir1 | |
246 | dd53ded3 | blueswir1 | static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = { |
247 | dd53ded3 | blueswir1 | ecc_diag_mem_writeb, |
248 | dd53ded3 | blueswir1 | NULL,
|
249 | dd53ded3 | blueswir1 | NULL,
|
250 | dd53ded3 | blueswir1 | }; |
251 | dd53ded3 | blueswir1 | |
252 | 7eb0c8e8 | blueswir1 | static int ecc_load(QEMUFile *f, void *opaque, int version_id) |
253 | 7eb0c8e8 | blueswir1 | { |
254 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
255 | 7eb0c8e8 | blueswir1 | int i;
|
256 | 7eb0c8e8 | blueswir1 | |
257 | dd53ded3 | blueswir1 | if (version_id != 2) |
258 | 7eb0c8e8 | blueswir1 | return -EINVAL;
|
259 | 7eb0c8e8 | blueswir1 | |
260 | 7eb0c8e8 | blueswir1 | for (i = 0; i < ECC_NREGS; i++) |
261 | 7eb0c8e8 | blueswir1 | qemu_get_be32s(f, &s->regs[i]); |
262 | 7eb0c8e8 | blueswir1 | |
263 | dd53ded3 | blueswir1 | for (i = 0; i < ECC_DIAG_SIZE; i++) |
264 | dd53ded3 | blueswir1 | qemu_get_8s(f, &s->diag[i]); |
265 | dd53ded3 | blueswir1 | |
266 | 7eb0c8e8 | blueswir1 | return 0; |
267 | 7eb0c8e8 | blueswir1 | } |
268 | 7eb0c8e8 | blueswir1 | |
269 | 7eb0c8e8 | blueswir1 | static void ecc_save(QEMUFile *f, void *opaque) |
270 | 7eb0c8e8 | blueswir1 | { |
271 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
272 | 7eb0c8e8 | blueswir1 | int i;
|
273 | 7eb0c8e8 | blueswir1 | |
274 | 7eb0c8e8 | blueswir1 | for (i = 0; i < ECC_NREGS; i++) |
275 | 7eb0c8e8 | blueswir1 | qemu_put_be32s(f, &s->regs[i]); |
276 | dd53ded3 | blueswir1 | |
277 | dd53ded3 | blueswir1 | for (i = 0; i < ECC_DIAG_SIZE; i++) |
278 | dd53ded3 | blueswir1 | qemu_put_8s(f, &s->diag[i]); |
279 | 7eb0c8e8 | blueswir1 | } |
280 | 7eb0c8e8 | blueswir1 | |
281 | 7eb0c8e8 | blueswir1 | static void ecc_reset(void *opaque) |
282 | 7eb0c8e8 | blueswir1 | { |
283 | 7eb0c8e8 | blueswir1 | ECCState *s = opaque; |
284 | 7eb0c8e8 | blueswir1 | |
285 | dd53ded3 | blueswir1 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL); |
286 | dd53ded3 | blueswir1 | s->regs[ECC_MER] |= ECC_MER_MRR; |
287 | dd53ded3 | blueswir1 | s->regs[ECC_MDR] = 0x20;
|
288 | dd53ded3 | blueswir1 | s->regs[ECC_MFSR] = 0;
|
289 | dd53ded3 | blueswir1 | s->regs[ECC_VCR] = 0;
|
290 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR0] = 0x07c00000;
|
291 | dd53ded3 | blueswir1 | s->regs[ECC_MFAR1] = 0;
|
292 | dd53ded3 | blueswir1 | s->regs[ECC_DR] = 0;
|
293 | dd53ded3 | blueswir1 | s->regs[ECC_ECR0] = 0;
|
294 | dd53ded3 | blueswir1 | s->regs[ECC_ECR1] = 0;
|
295 | 7eb0c8e8 | blueswir1 | } |
296 | 7eb0c8e8 | blueswir1 | |
297 | e42c20b4 | blueswir1 | void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
|
298 | 7eb0c8e8 | blueswir1 | { |
299 | 7eb0c8e8 | blueswir1 | int ecc_io_memory;
|
300 | 7eb0c8e8 | blueswir1 | ECCState *s; |
301 | 7eb0c8e8 | blueswir1 | |
302 | 7eb0c8e8 | blueswir1 | s = qemu_mallocz(sizeof(ECCState));
|
303 | 7eb0c8e8 | blueswir1 | if (!s)
|
304 | 7eb0c8e8 | blueswir1 | return NULL; |
305 | 7eb0c8e8 | blueswir1 | |
306 | 7eb0c8e8 | blueswir1 | s->regs[0] = version;
|
307 | e42c20b4 | blueswir1 | s->irq = irq; |
308 | 7eb0c8e8 | blueswir1 | |
309 | 7eb0c8e8 | blueswir1 | ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
|
310 | 7eb0c8e8 | blueswir1 | cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory); |
311 | dd53ded3 | blueswir1 | if (version == 0) { // SS-600MP only |
312 | dd53ded3 | blueswir1 | ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
|
313 | dd53ded3 | blueswir1 | ecc_diag_mem_write, s); |
314 | dd53ded3 | blueswir1 | cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
|
315 | dd53ded3 | blueswir1 | ecc_io_memory); |
316 | dd53ded3 | blueswir1 | } |
317 | dd53ded3 | blueswir1 | register_savevm("ECC", base, 2, ecc_save, ecc_load, s); |
318 | 7eb0c8e8 | blueswir1 | qemu_register_reset(ecc_reset, s); |
319 | 7eb0c8e8 | blueswir1 | ecc_reset(s); |
320 | 7eb0c8e8 | blueswir1 | return s;
|
321 | 7eb0c8e8 | blueswir1 | } |