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1 | 05ee37eb | balrog | /*
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2 | 05ee37eb | balrog | * CFI parallel flash with Intel command set emulation
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3 | 05ee37eb | balrog | *
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4 | 05ee37eb | balrog | * Copyright (c) 2006 Thorsten Zitterell
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5 | 05ee37eb | balrog | * Copyright (c) 2005 Jocelyn Mayer
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6 | 05ee37eb | balrog | *
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7 | 05ee37eb | balrog | * This library is free software; you can redistribute it and/or
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8 | 05ee37eb | balrog | * modify it under the terms of the GNU Lesser General Public
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9 | 05ee37eb | balrog | * License as published by the Free Software Foundation; either
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10 | 05ee37eb | balrog | * version 2 of the License, or (at your option) any later version.
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11 | 05ee37eb | balrog | *
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12 | 05ee37eb | balrog | * This library is distributed in the hope that it will be useful,
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13 | 05ee37eb | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 05ee37eb | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 05ee37eb | balrog | * Lesser General Public License for more details.
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16 | 05ee37eb | balrog | *
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17 | 05ee37eb | balrog | * You should have received a copy of the GNU Lesser General Public
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18 | 05ee37eb | balrog | * License along with this library; if not, write to the Free Software
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19 | 05ee37eb | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 05ee37eb | balrog | */
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21 | 05ee37eb | balrog | |
22 | 05ee37eb | balrog | /*
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23 | 05ee37eb | balrog | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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24 | 05ee37eb | balrog | * Supported commands/modes are:
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25 | 05ee37eb | balrog | * - flash read
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26 | 05ee37eb | balrog | * - flash write
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27 | 05ee37eb | balrog | * - flash ID read
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28 | 05ee37eb | balrog | * - sector erase
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29 | 05ee37eb | balrog | * - CFI queries
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30 | 05ee37eb | balrog | *
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31 | 05ee37eb | balrog | * It does not support timings
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32 | 05ee37eb | balrog | * It does not support flash interleaving
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33 | 05ee37eb | balrog | * It does not implement software data protection as found in many real chips
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34 | 05ee37eb | balrog | * It does not implement erase suspend/resume commands
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35 | 05ee37eb | balrog | * It does not implement multiple sectors erase
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36 | 05ee37eb | balrog | *
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37 | 05ee37eb | balrog | * It does not implement much more ...
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38 | 05ee37eb | balrog | */
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39 | 05ee37eb | balrog | |
40 | 87ecb68b | pbrook | #include "hw.h" |
41 | 87ecb68b | pbrook | #include "flash.h" |
42 | 87ecb68b | pbrook | #include "block.h" |
43 | 87ecb68b | pbrook | #include "qemu-timer.h" |
44 | 05ee37eb | balrog | |
45 | 05ee37eb | balrog | #define PFLASH_BUG(fmt, args...) \
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46 | 05ee37eb | balrog | do { \
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47 | 05ee37eb | balrog | printf("PFLASH: Possible BUG - " fmt, ##args); \ |
48 | 05ee37eb | balrog | exit(1); \
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49 | 05ee37eb | balrog | } while(0) |
50 | 05ee37eb | balrog | |
51 | 05ee37eb | balrog | /* #define PFLASH_DEBUG */
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52 | 05ee37eb | balrog | #ifdef PFLASH_DEBUG
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53 | 05ee37eb | balrog | #define DPRINTF(fmt, args...) \
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54 | 05ee37eb | balrog | do { \
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55 | 05ee37eb | balrog | printf("PFLASH: " fmt , ##args); \ |
56 | 05ee37eb | balrog | } while (0) |
57 | 05ee37eb | balrog | #else
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58 | 05ee37eb | balrog | #define DPRINTF(fmt, args...) do { } while (0) |
59 | 05ee37eb | balrog | #endif
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60 | 05ee37eb | balrog | |
61 | 05ee37eb | balrog | struct pflash_t {
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62 | 05ee37eb | balrog | BlockDriverState *bs; |
63 | 05ee37eb | balrog | target_ulong base; |
64 | 05ee37eb | balrog | target_ulong sector_len; |
65 | 05ee37eb | balrog | target_ulong total_len; |
66 | 05ee37eb | balrog | int width;
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67 | 05ee37eb | balrog | int wcycle; /* if 0, the flash is read normally */ |
68 | 05ee37eb | balrog | int bypass;
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69 | 05ee37eb | balrog | int ro;
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70 | 05ee37eb | balrog | uint8_t cmd; |
71 | 05ee37eb | balrog | uint8_t status; |
72 | 05ee37eb | balrog | uint16_t ident[4];
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73 | 05ee37eb | balrog | uint8_t cfi_len; |
74 | 05ee37eb | balrog | uint8_t cfi_table[0x52];
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75 | 05ee37eb | balrog | target_ulong counter; |
76 | 05ee37eb | balrog | QEMUTimer *timer; |
77 | 05ee37eb | balrog | ram_addr_t off; |
78 | 05ee37eb | balrog | int fl_mem;
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79 | 05ee37eb | balrog | void *storage;
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80 | 05ee37eb | balrog | }; |
81 | 05ee37eb | balrog | |
82 | 05ee37eb | balrog | static void pflash_timer (void *opaque) |
83 | 05ee37eb | balrog | { |
84 | 05ee37eb | balrog | pflash_t *pfl = opaque; |
85 | 05ee37eb | balrog | |
86 | 05ee37eb | balrog | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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87 | 05ee37eb | balrog | /* Reset flash */
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88 | 05ee37eb | balrog | pfl->status ^= 0x80;
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89 | 05ee37eb | balrog | if (pfl->bypass) {
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90 | 05ee37eb | balrog | pfl->wcycle = 2;
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91 | 05ee37eb | balrog | } else {
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92 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
93 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
94 | 05ee37eb | balrog | pfl->wcycle = 0;
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95 | 05ee37eb | balrog | } |
96 | 05ee37eb | balrog | pfl->cmd = 0;
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97 | 05ee37eb | balrog | } |
98 | 05ee37eb | balrog | |
99 | 05ee37eb | balrog | static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width) |
100 | 05ee37eb | balrog | { |
101 | 05ee37eb | balrog | target_ulong boff; |
102 | 05ee37eb | balrog | uint32_t ret; |
103 | 05ee37eb | balrog | uint8_t *p; |
104 | 05ee37eb | balrog | |
105 | 05ee37eb | balrog | ret = -1;
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106 | 05ee37eb | balrog | offset -= pfl->base; |
107 | 05ee37eb | balrog | boff = offset & 0xFF; /* why this here ?? */ |
108 | 05ee37eb | balrog | |
109 | 05ee37eb | balrog | if (pfl->width == 2) |
110 | 05ee37eb | balrog | boff = boff >> 1;
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111 | 05ee37eb | balrog | else if (pfl->width == 4) |
112 | 05ee37eb | balrog | boff = boff >> 2;
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113 | 05ee37eb | balrog | |
114 | c8b153d7 | ths | DPRINTF("%s: reading offset " TARGET_FMT_lx " under cmd %02x\n", |
115 | c8b153d7 | ths | __func__, boff, pfl->cmd); |
116 | 05ee37eb | balrog | |
117 | 05ee37eb | balrog | switch (pfl->cmd) {
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118 | 05ee37eb | balrog | case 0x00: |
119 | 05ee37eb | balrog | /* Flash area read */
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120 | 05ee37eb | balrog | p = pfl->storage; |
121 | 05ee37eb | balrog | switch (width) {
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122 | 05ee37eb | balrog | case 1: |
123 | 05ee37eb | balrog | ret = p[offset]; |
124 | c8b153d7 | ths | DPRINTF("%s: data offset " TARGET_FMT_lx " %02x\n", |
125 | c8b153d7 | ths | __func__, offset, ret); |
126 | 05ee37eb | balrog | break;
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127 | 05ee37eb | balrog | case 2: |
128 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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129 | 05ee37eb | balrog | ret = p[offset] << 8;
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130 | 05ee37eb | balrog | ret |= p[offset + 1];
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131 | 05ee37eb | balrog | #else
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132 | 05ee37eb | balrog | ret = p[offset]; |
133 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
134 | 05ee37eb | balrog | #endif
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135 | c8b153d7 | ths | DPRINTF("%s: data offset " TARGET_FMT_lx " %04x\n", |
136 | c8b153d7 | ths | __func__, offset, ret); |
137 | 05ee37eb | balrog | break;
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138 | 05ee37eb | balrog | case 4: |
139 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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140 | 05ee37eb | balrog | ret = p[offset] << 24;
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141 | 05ee37eb | balrog | ret |= p[offset + 1] << 16; |
142 | 05ee37eb | balrog | ret |= p[offset + 2] << 8; |
143 | 05ee37eb | balrog | ret |= p[offset + 3];
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144 | 05ee37eb | balrog | #else
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145 | 05ee37eb | balrog | ret = p[offset]; |
146 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
147 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
148 | 05ee37eb | balrog | ret |= p[offset + 2] << 16; |
149 | 05ee37eb | balrog | ret |= p[offset + 3] << 24; |
150 | 05ee37eb | balrog | #endif
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151 | c8b153d7 | ths | DPRINTF("%s: data offset " TARGET_FMT_lx " %08x\n", |
152 | c8b153d7 | ths | __func__, offset, ret); |
153 | 05ee37eb | balrog | break;
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154 | 05ee37eb | balrog | default:
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155 | 05ee37eb | balrog | DPRINTF("BUG in %s\n", __func__);
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156 | 05ee37eb | balrog | } |
157 | 05ee37eb | balrog | |
158 | 05ee37eb | balrog | break;
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159 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
160 | 05ee37eb | balrog | case 0x50: /* Clear status register */ |
161 | 05ee37eb | balrog | case 0x60: /* Block /un)lock */ |
162 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
163 | 05ee37eb | balrog | case 0xe8: /* Write block */ |
164 | 05ee37eb | balrog | /* Status register read */
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165 | 05ee37eb | balrog | ret = pfl->status; |
166 | 05ee37eb | balrog | DPRINTF("%s: status %x\n", __func__, ret);
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167 | 05ee37eb | balrog | break;
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168 | 05ee37eb | balrog | case 0x98: /* Query mode */ |
169 | 05ee37eb | balrog | if (boff > pfl->cfi_len)
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170 | 05ee37eb | balrog | ret = 0;
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171 | 05ee37eb | balrog | else
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172 | 05ee37eb | balrog | ret = pfl->cfi_table[boff]; |
173 | 05ee37eb | balrog | break;
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174 | 05ee37eb | balrog | default:
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175 | 05ee37eb | balrog | /* This should never happen : reset state & treat it as a read */
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176 | 05ee37eb | balrog | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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177 | 05ee37eb | balrog | pfl->wcycle = 0;
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178 | 05ee37eb | balrog | pfl->cmd = 0;
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179 | 05ee37eb | balrog | } |
180 | 05ee37eb | balrog | return ret;
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181 | 05ee37eb | balrog | } |
182 | 05ee37eb | balrog | |
183 | 05ee37eb | balrog | /* update flash content on disk */
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184 | 05ee37eb | balrog | static void pflash_update(pflash_t *pfl, int offset, |
185 | 05ee37eb | balrog | int size)
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186 | 05ee37eb | balrog | { |
187 | 05ee37eb | balrog | int offset_end;
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188 | 05ee37eb | balrog | if (pfl->bs) {
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189 | 05ee37eb | balrog | offset_end = offset + size; |
190 | 05ee37eb | balrog | /* round to sectors */
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191 | 05ee37eb | balrog | offset = offset >> 9;
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192 | 05ee37eb | balrog | offset_end = (offset_end + 511) >> 9; |
193 | 05ee37eb | balrog | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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194 | 05ee37eb | balrog | offset_end - offset); |
195 | 05ee37eb | balrog | } |
196 | 05ee37eb | balrog | } |
197 | 05ee37eb | balrog | |
198 | 05ee37eb | balrog | static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value, |
199 | 05ee37eb | balrog | int width)
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200 | 05ee37eb | balrog | { |
201 | 05ee37eb | balrog | target_ulong boff; |
202 | 05ee37eb | balrog | uint8_t *p; |
203 | 05ee37eb | balrog | uint8_t cmd; |
204 | 05ee37eb | balrog | |
205 | 05ee37eb | balrog | cmd = value; |
206 | 0f459d16 | pbrook | offset -= pfl->base; |
207 | 05ee37eb | balrog | |
208 | c8b153d7 | ths | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d wcycle 0x%x\n", |
209 | c8b153d7 | ths | __func__, offset, value, width, pfl->wcycle); |
210 | 05ee37eb | balrog | |
211 | 05ee37eb | balrog | /* Set the device in I/O access mode */
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212 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
213 | 05ee37eb | balrog | boff = offset & (pfl->sector_len - 1);
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214 | 05ee37eb | balrog | |
215 | 05ee37eb | balrog | if (pfl->width == 2) |
216 | 05ee37eb | balrog | boff = boff >> 1;
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217 | 05ee37eb | balrog | else if (pfl->width == 4) |
218 | 05ee37eb | balrog | boff = boff >> 2;
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219 | 05ee37eb | balrog | |
220 | 05ee37eb | balrog | switch (pfl->wcycle) {
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221 | 05ee37eb | balrog | case 0: |
222 | 05ee37eb | balrog | /* read mode */
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223 | 05ee37eb | balrog | switch (cmd) {
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224 | 05ee37eb | balrog | case 0x00: /* ??? */ |
225 | 05ee37eb | balrog | goto reset_flash;
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226 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
227 | 05ee37eb | balrog | p = pfl->storage; |
228 | 05ee37eb | balrog | offset &= ~(pfl->sector_len - 1);
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229 | 05ee37eb | balrog | |
230 | c8b153d7 | ths | DPRINTF("%s: block erase at " TARGET_FMT_lx " bytes " |
231 | c8b153d7 | ths | TARGET_FMT_lx "\n",
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232 | c8b153d7 | ths | __func__, offset, pfl->sector_len); |
233 | 05ee37eb | balrog | |
234 | 05ee37eb | balrog | memset(p + offset, 0xff, pfl->sector_len);
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235 | 05ee37eb | balrog | pflash_update(pfl, offset, pfl->sector_len); |
236 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
237 | 05ee37eb | balrog | break;
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238 | 05ee37eb | balrog | case 0x50: /* Clear status bits */ |
239 | 05ee37eb | balrog | DPRINTF("%s: Clear status bits\n", __func__);
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240 | 05ee37eb | balrog | pfl->status = 0x0;
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241 | 05ee37eb | balrog | goto reset_flash;
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242 | 05ee37eb | balrog | case 0x60: /* Block (un)lock */ |
243 | 05ee37eb | balrog | DPRINTF("%s: Block unlock\n", __func__);
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244 | 05ee37eb | balrog | break;
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245 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
246 | 05ee37eb | balrog | DPRINTF("%s: Read status register\n", __func__);
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247 | 05ee37eb | balrog | pfl->cmd = cmd; |
248 | 05ee37eb | balrog | return;
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249 | 05ee37eb | balrog | case 0x98: /* CFI query */ |
250 | 05ee37eb | balrog | DPRINTF("%s: CFI query\n", __func__);
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251 | 05ee37eb | balrog | break;
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252 | 05ee37eb | balrog | case 0xe8: /* Write to buffer */ |
253 | 05ee37eb | balrog | DPRINTF("%s: Write to buffer\n", __func__);
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254 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
255 | 05ee37eb | balrog | break;
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256 | 05ee37eb | balrog | case 0xff: /* Read array mode */ |
257 | 05ee37eb | balrog | DPRINTF("%s: Read array mode\n", __func__);
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258 | 05ee37eb | balrog | goto reset_flash;
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259 | 05ee37eb | balrog | default:
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260 | 05ee37eb | balrog | goto error_flash;
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261 | 05ee37eb | balrog | } |
262 | 05ee37eb | balrog | pfl->wcycle++; |
263 | 05ee37eb | balrog | pfl->cmd = cmd; |
264 | 05ee37eb | balrog | return;
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265 | 05ee37eb | balrog | case 1: |
266 | 05ee37eb | balrog | switch (pfl->cmd) {
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267 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
268 | 05ee37eb | balrog | case 0x28: |
269 | 05ee37eb | balrog | if (cmd == 0xd0) { /* confirm */ |
270 | 05ee37eb | balrog | pfl->wcycle = 1;
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271 | 05ee37eb | balrog | pfl->status |= 0x80;
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272 | 9248f413 | aurel32 | } else if (cmd == 0xff) { /* read array mode */ |
273 | 05ee37eb | balrog | goto reset_flash;
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274 | 05ee37eb | balrog | } else
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275 | 05ee37eb | balrog | goto error_flash;
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276 | 05ee37eb | balrog | |
277 | 05ee37eb | balrog | break;
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278 | 05ee37eb | balrog | case 0xe8: |
279 | c8b153d7 | ths | DPRINTF("%s: block write of %x bytes\n", __func__, cmd);
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280 | 05ee37eb | balrog | pfl->counter = cmd; |
281 | 05ee37eb | balrog | pfl->wcycle++; |
282 | 05ee37eb | balrog | break;
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283 | 05ee37eb | balrog | case 0x60: |
284 | 05ee37eb | balrog | if (cmd == 0xd0) { |
285 | 05ee37eb | balrog | pfl->wcycle = 0;
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286 | 05ee37eb | balrog | pfl->status |= 0x80;
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287 | 05ee37eb | balrog | } else if (cmd == 0x01) { |
288 | 05ee37eb | balrog | pfl->wcycle = 0;
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289 | 05ee37eb | balrog | pfl->status |= 0x80;
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290 | 05ee37eb | balrog | } else if (cmd == 0xff) { |
291 | 05ee37eb | balrog | goto reset_flash;
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292 | 05ee37eb | balrog | } else {
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293 | 05ee37eb | balrog | DPRINTF("%s: Unknown (un)locking command\n", __func__);
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294 | 05ee37eb | balrog | goto reset_flash;
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295 | 05ee37eb | balrog | } |
296 | 05ee37eb | balrog | break;
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297 | 05ee37eb | balrog | case 0x98: |
298 | 05ee37eb | balrog | if (cmd == 0xff) { |
299 | 05ee37eb | balrog | goto reset_flash;
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300 | 05ee37eb | balrog | } else {
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301 | 05ee37eb | balrog | DPRINTF("%s: leaving query mode\n", __func__);
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302 | 05ee37eb | balrog | } |
303 | 05ee37eb | balrog | break;
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304 | 05ee37eb | balrog | default:
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305 | 05ee37eb | balrog | goto error_flash;
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306 | 05ee37eb | balrog | } |
307 | 05ee37eb | balrog | return;
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308 | 05ee37eb | balrog | case 2: |
309 | 05ee37eb | balrog | switch (pfl->cmd) {
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310 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
311 | 05ee37eb | balrog | p = pfl->storage; |
312 | c8b153d7 | ths | DPRINTF("%s: block write offset " TARGET_FMT_lx
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313 | c8b153d7 | ths | " value %x counter " TARGET_FMT_lx "\n", |
314 | c8b153d7 | ths | __func__, offset, value, pfl->counter); |
315 | 05ee37eb | balrog | switch (width) {
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316 | 05ee37eb | balrog | case 1: |
317 | 05ee37eb | balrog | p[offset] = value; |
318 | 05ee37eb | balrog | pflash_update(pfl, offset, 1);
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319 | 05ee37eb | balrog | break;
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320 | 05ee37eb | balrog | case 2: |
321 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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322 | 05ee37eb | balrog | p[offset] = value >> 8;
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323 | 05ee37eb | balrog | p[offset + 1] = value;
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324 | 05ee37eb | balrog | #else
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325 | 05ee37eb | balrog | p[offset] = value; |
326 | 05ee37eb | balrog | p[offset + 1] = value >> 8; |
327 | 05ee37eb | balrog | #endif
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328 | 05ee37eb | balrog | pflash_update(pfl, offset, 2);
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329 | 05ee37eb | balrog | break;
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330 | 05ee37eb | balrog | case 4: |
331 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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332 | 05ee37eb | balrog | p[offset] = value >> 24;
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333 | 05ee37eb | balrog | p[offset + 1] = value >> 16; |
334 | 05ee37eb | balrog | p[offset + 2] = value >> 8; |
335 | 05ee37eb | balrog | p[offset + 3] = value;
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336 | 05ee37eb | balrog | #else
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337 | 05ee37eb | balrog | p[offset] = value; |
338 | 05ee37eb | balrog | p[offset + 1] = value >> 8; |
339 | 05ee37eb | balrog | p[offset + 2] = value >> 16; |
340 | 05ee37eb | balrog | p[offset + 3] = value >> 24; |
341 | 05ee37eb | balrog | #endif
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342 | 05ee37eb | balrog | pflash_update(pfl, offset, 4);
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343 | 05ee37eb | balrog | break;
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344 | 05ee37eb | balrog | } |
345 | 05ee37eb | balrog | |
346 | 05ee37eb | balrog | pfl->status |= 0x80;
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347 | 05ee37eb | balrog | |
348 | 05ee37eb | balrog | if (!pfl->counter) {
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349 | 05ee37eb | balrog | DPRINTF("%s: block write finished\n", __func__);
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350 | 05ee37eb | balrog | pfl->wcycle++; |
351 | 05ee37eb | balrog | } |
352 | 05ee37eb | balrog | |
353 | 05ee37eb | balrog | pfl->counter--; |
354 | 05ee37eb | balrog | break;
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355 | 7317b8ca | balrog | default:
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356 | 7317b8ca | balrog | goto error_flash;
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357 | 05ee37eb | balrog | } |
358 | 05ee37eb | balrog | return;
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359 | 05ee37eb | balrog | case 3: /* Confirm mode */ |
360 | 05ee37eb | balrog | switch (pfl->cmd) {
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361 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
362 | 05ee37eb | balrog | if (cmd == 0xd0) { |
363 | 05ee37eb | balrog | pfl->wcycle = 0;
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364 | 05ee37eb | balrog | pfl->status |= 0x80;
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365 | 05ee37eb | balrog | } else {
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366 | 05ee37eb | balrog | DPRINTF("%s: unknown command for \"write block\"\n", __func__);
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367 | 05ee37eb | balrog | PFLASH_BUG("Write block confirm");
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368 | 7317b8ca | balrog | goto reset_flash;
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369 | 05ee37eb | balrog | } |
370 | 7317b8ca | balrog | break;
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371 | 7317b8ca | balrog | default:
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372 | 7317b8ca | balrog | goto error_flash;
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373 | 05ee37eb | balrog | } |
374 | 05ee37eb | balrog | return;
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375 | 05ee37eb | balrog | default:
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376 | 05ee37eb | balrog | /* Should never happen */
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377 | 05ee37eb | balrog | DPRINTF("%s: invalid write state\n", __func__);
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378 | 05ee37eb | balrog | goto reset_flash;
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379 | 05ee37eb | balrog | } |
380 | 05ee37eb | balrog | return;
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381 | 05ee37eb | balrog | |
382 | 05ee37eb | balrog | error_flash:
|
383 | 05ee37eb | balrog | printf("%s: Unimplemented flash cmd sequence "
|
384 | c8b153d7 | ths | "(offset " TARGET_FMT_lx ", wcycle 0x%x cmd 0x%x value 0x%x\n", |
385 | c8b153d7 | ths | __func__, offset, pfl->wcycle, pfl->cmd, value); |
386 | 05ee37eb | balrog | |
387 | 05ee37eb | balrog | reset_flash:
|
388 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
389 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
390 | 05ee37eb | balrog | |
391 | 05ee37eb | balrog | pfl->bypass = 0;
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392 | 05ee37eb | balrog | pfl->wcycle = 0;
|
393 | 05ee37eb | balrog | pfl->cmd = 0;
|
394 | 05ee37eb | balrog | return;
|
395 | 05ee37eb | balrog | } |
396 | 05ee37eb | balrog | |
397 | 05ee37eb | balrog | |
398 | 05ee37eb | balrog | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
399 | 05ee37eb | balrog | { |
400 | 05ee37eb | balrog | return pflash_read(opaque, addr, 1); |
401 | 05ee37eb | balrog | } |
402 | 05ee37eb | balrog | |
403 | 05ee37eb | balrog | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
404 | 05ee37eb | balrog | { |
405 | 05ee37eb | balrog | pflash_t *pfl = opaque; |
406 | 05ee37eb | balrog | |
407 | 05ee37eb | balrog | return pflash_read(pfl, addr, 2); |
408 | 05ee37eb | balrog | } |
409 | 05ee37eb | balrog | |
410 | 05ee37eb | balrog | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
411 | 05ee37eb | balrog | { |
412 | 05ee37eb | balrog | pflash_t *pfl = opaque; |
413 | 05ee37eb | balrog | |
414 | 05ee37eb | balrog | return pflash_read(pfl, addr, 4); |
415 | 05ee37eb | balrog | } |
416 | 05ee37eb | balrog | |
417 | 05ee37eb | balrog | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
418 | 05ee37eb | balrog | uint32_t value) |
419 | 05ee37eb | balrog | { |
420 | 05ee37eb | balrog | pflash_write(opaque, addr, value, 1);
|
421 | 05ee37eb | balrog | } |
422 | 05ee37eb | balrog | |
423 | 05ee37eb | balrog | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
424 | 05ee37eb | balrog | uint32_t value) |
425 | 05ee37eb | balrog | { |
426 | 05ee37eb | balrog | pflash_t *pfl = opaque; |
427 | 05ee37eb | balrog | |
428 | 05ee37eb | balrog | pflash_write(pfl, addr, value, 2);
|
429 | 05ee37eb | balrog | } |
430 | 05ee37eb | balrog | |
431 | 05ee37eb | balrog | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
432 | 05ee37eb | balrog | uint32_t value) |
433 | 05ee37eb | balrog | { |
434 | 05ee37eb | balrog | pflash_t *pfl = opaque; |
435 | 05ee37eb | balrog | |
436 | 05ee37eb | balrog | pflash_write(pfl, addr, value, 4);
|
437 | 05ee37eb | balrog | } |
438 | 05ee37eb | balrog | |
439 | 05ee37eb | balrog | static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
440 | 05ee37eb | balrog | &pflash_writeb, |
441 | 05ee37eb | balrog | &pflash_writew, |
442 | 05ee37eb | balrog | &pflash_writel, |
443 | 05ee37eb | balrog | }; |
444 | 05ee37eb | balrog | |
445 | 05ee37eb | balrog | static CPUReadMemoryFunc *pflash_read_ops[] = {
|
446 | 05ee37eb | balrog | &pflash_readb, |
447 | 05ee37eb | balrog | &pflash_readw, |
448 | 05ee37eb | balrog | &pflash_readl, |
449 | 05ee37eb | balrog | }; |
450 | 05ee37eb | balrog | |
451 | 05ee37eb | balrog | /* Count trailing zeroes of a 32 bits quantity */
|
452 | 05ee37eb | balrog | static int ctz32 (uint32_t n) |
453 | 05ee37eb | balrog | { |
454 | 05ee37eb | balrog | int ret;
|
455 | 05ee37eb | balrog | |
456 | 05ee37eb | balrog | ret = 0;
|
457 | 05ee37eb | balrog | if (!(n & 0xFFFF)) { |
458 | 05ee37eb | balrog | ret += 16;
|
459 | 05ee37eb | balrog | n = n >> 16;
|
460 | 05ee37eb | balrog | } |
461 | 05ee37eb | balrog | if (!(n & 0xFF)) { |
462 | 05ee37eb | balrog | ret += 8;
|
463 | 05ee37eb | balrog | n = n >> 8;
|
464 | 05ee37eb | balrog | } |
465 | 05ee37eb | balrog | if (!(n & 0xF)) { |
466 | 05ee37eb | balrog | ret += 4;
|
467 | 05ee37eb | balrog | n = n >> 4;
|
468 | 05ee37eb | balrog | } |
469 | 05ee37eb | balrog | if (!(n & 0x3)) { |
470 | 05ee37eb | balrog | ret += 2;
|
471 | 05ee37eb | balrog | n = n >> 2;
|
472 | 05ee37eb | balrog | } |
473 | 05ee37eb | balrog | if (!(n & 0x1)) { |
474 | 05ee37eb | balrog | ret++; |
475 | 05ee37eb | balrog | n = n >> 1;
|
476 | 05ee37eb | balrog | } |
477 | 05ee37eb | balrog | #if 0 /* This is not necessary as n is never 0 */
|
478 | 05ee37eb | balrog | if (!n)
|
479 | 05ee37eb | balrog | ret++;
|
480 | 05ee37eb | balrog | #endif
|
481 | 05ee37eb | balrog | |
482 | 05ee37eb | balrog | return ret;
|
483 | 05ee37eb | balrog | } |
484 | 05ee37eb | balrog | |
485 | 88eeee0a | balrog | pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
486 | c8b153d7 | ths | BlockDriverState *bs, uint32_t sector_len, |
487 | 88eeee0a | balrog | int nb_blocs, int width, |
488 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
489 | 88eeee0a | balrog | uint16_t id2, uint16_t id3) |
490 | 05ee37eb | balrog | { |
491 | 05ee37eb | balrog | pflash_t *pfl; |
492 | 05ee37eb | balrog | target_long total_len; |
493 | 05ee37eb | balrog | |
494 | 05ee37eb | balrog | total_len = sector_len * nb_blocs; |
495 | 05ee37eb | balrog | |
496 | 05ee37eb | balrog | /* XXX: to be fixed */
|
497 | c8b153d7 | ths | #if 0
|
498 | 05ee37eb | balrog | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
499 | 05ee37eb | balrog | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
500 | 05ee37eb | balrog | return NULL;
|
501 | c8b153d7 | ths | #endif
|
502 | 05ee37eb | balrog | |
503 | 05ee37eb | balrog | pfl = qemu_mallocz(sizeof(pflash_t));
|
504 | 05ee37eb | balrog | |
505 | 05ee37eb | balrog | if (pfl == NULL) |
506 | 05ee37eb | balrog | return NULL; |
507 | 05ee37eb | balrog | pfl->storage = phys_ram_base + off; |
508 | 05ee37eb | balrog | pfl->fl_mem = cpu_register_io_memory(0,
|
509 | 05ee37eb | balrog | pflash_read_ops, pflash_write_ops, pfl); |
510 | 05ee37eb | balrog | pfl->off = off; |
511 | 05ee37eb | balrog | cpu_register_physical_memory(base, total_len, |
512 | 05ee37eb | balrog | off | pfl->fl_mem | IO_MEM_ROMD); |
513 | 05ee37eb | balrog | |
514 | 05ee37eb | balrog | pfl->bs = bs; |
515 | 05ee37eb | balrog | if (pfl->bs) {
|
516 | 05ee37eb | balrog | /* read the initial flash content */
|
517 | 05ee37eb | balrog | bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
518 | 05ee37eb | balrog | } |
519 | 05ee37eb | balrog | #if 0 /* XXX: there should be a bit to set up read-only,
|
520 | 05ee37eb | balrog | * the same way the hardware does (with WP pin).
|
521 | 05ee37eb | balrog | */
|
522 | 05ee37eb | balrog | pfl->ro = 1;
|
523 | 05ee37eb | balrog | #else
|
524 | 05ee37eb | balrog | pfl->ro = 0;
|
525 | 05ee37eb | balrog | #endif
|
526 | 05ee37eb | balrog | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
527 | 05ee37eb | balrog | pfl->base = base; |
528 | 05ee37eb | balrog | pfl->sector_len = sector_len; |
529 | 05ee37eb | balrog | pfl->total_len = total_len; |
530 | 05ee37eb | balrog | pfl->width = width; |
531 | 05ee37eb | balrog | pfl->wcycle = 0;
|
532 | 05ee37eb | balrog | pfl->cmd = 0;
|
533 | 05ee37eb | balrog | pfl->status = 0;
|
534 | 05ee37eb | balrog | pfl->ident[0] = id0;
|
535 | 05ee37eb | balrog | pfl->ident[1] = id1;
|
536 | 05ee37eb | balrog | pfl->ident[2] = id2;
|
537 | 05ee37eb | balrog | pfl->ident[3] = id3;
|
538 | 05ee37eb | balrog | /* Hardcoded CFI table */
|
539 | 05ee37eb | balrog | pfl->cfi_len = 0x52;
|
540 | 05ee37eb | balrog | /* Standard "QRY" string */
|
541 | 05ee37eb | balrog | pfl->cfi_table[0x10] = 'Q'; |
542 | 05ee37eb | balrog | pfl->cfi_table[0x11] = 'R'; |
543 | 05ee37eb | balrog | pfl->cfi_table[0x12] = 'Y'; |
544 | 05ee37eb | balrog | /* Command set (Intel) */
|
545 | 05ee37eb | balrog | pfl->cfi_table[0x13] = 0x01; |
546 | 05ee37eb | balrog | pfl->cfi_table[0x14] = 0x00; |
547 | 05ee37eb | balrog | /* Primary extended table address (none) */
|
548 | 05ee37eb | balrog | pfl->cfi_table[0x15] = 0x31; |
549 | 05ee37eb | balrog | pfl->cfi_table[0x16] = 0x00; |
550 | 05ee37eb | balrog | /* Alternate command set (none) */
|
551 | 05ee37eb | balrog | pfl->cfi_table[0x17] = 0x00; |
552 | 05ee37eb | balrog | pfl->cfi_table[0x18] = 0x00; |
553 | 05ee37eb | balrog | /* Alternate extended table (none) */
|
554 | 05ee37eb | balrog | pfl->cfi_table[0x19] = 0x00; |
555 | 05ee37eb | balrog | pfl->cfi_table[0x1A] = 0x00; |
556 | 05ee37eb | balrog | /* Vcc min */
|
557 | 05ee37eb | balrog | pfl->cfi_table[0x1B] = 0x45; |
558 | 05ee37eb | balrog | /* Vcc max */
|
559 | 05ee37eb | balrog | pfl->cfi_table[0x1C] = 0x55; |
560 | 05ee37eb | balrog | /* Vpp min (no Vpp pin) */
|
561 | 05ee37eb | balrog | pfl->cfi_table[0x1D] = 0x00; |
562 | 05ee37eb | balrog | /* Vpp max (no Vpp pin) */
|
563 | 05ee37eb | balrog | pfl->cfi_table[0x1E] = 0x00; |
564 | 05ee37eb | balrog | /* Reserved */
|
565 | 05ee37eb | balrog | pfl->cfi_table[0x1F] = 0x07; |
566 | 05ee37eb | balrog | /* Timeout for min size buffer write */
|
567 | 05ee37eb | balrog | pfl->cfi_table[0x20] = 0x07; |
568 | 05ee37eb | balrog | /* Typical timeout for block erase */
|
569 | 05ee37eb | balrog | pfl->cfi_table[0x21] = 0x0a; |
570 | 05ee37eb | balrog | /* Typical timeout for full chip erase (4096 ms) */
|
571 | 05ee37eb | balrog | pfl->cfi_table[0x22] = 0x00; |
572 | 05ee37eb | balrog | /* Reserved */
|
573 | 05ee37eb | balrog | pfl->cfi_table[0x23] = 0x04; |
574 | 05ee37eb | balrog | /* Max timeout for buffer write */
|
575 | 05ee37eb | balrog | pfl->cfi_table[0x24] = 0x04; |
576 | 05ee37eb | balrog | /* Max timeout for block erase */
|
577 | 05ee37eb | balrog | pfl->cfi_table[0x25] = 0x04; |
578 | 05ee37eb | balrog | /* Max timeout for chip erase */
|
579 | 05ee37eb | balrog | pfl->cfi_table[0x26] = 0x00; |
580 | 05ee37eb | balrog | /* Device size */
|
581 | 05ee37eb | balrog | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
582 | 05ee37eb | balrog | /* Flash device interface (8 & 16 bits) */
|
583 | 05ee37eb | balrog | pfl->cfi_table[0x28] = 0x02; |
584 | 05ee37eb | balrog | pfl->cfi_table[0x29] = 0x00; |
585 | 05ee37eb | balrog | /* Max number of bytes in multi-bytes write */
|
586 | 05ee37eb | balrog | pfl->cfi_table[0x2A] = 0x04; |
587 | 05ee37eb | balrog | pfl->cfi_table[0x2B] = 0x00; |
588 | 05ee37eb | balrog | /* Number of erase block regions (uniform) */
|
589 | 05ee37eb | balrog | pfl->cfi_table[0x2C] = 0x01; |
590 | 05ee37eb | balrog | /* Erase block region 1 */
|
591 | 05ee37eb | balrog | pfl->cfi_table[0x2D] = nb_blocs - 1; |
592 | 05ee37eb | balrog | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
593 | 05ee37eb | balrog | pfl->cfi_table[0x2F] = sector_len >> 8; |
594 | 05ee37eb | balrog | pfl->cfi_table[0x30] = sector_len >> 16; |
595 | 05ee37eb | balrog | |
596 | 05ee37eb | balrog | /* Extended */
|
597 | 05ee37eb | balrog | pfl->cfi_table[0x31] = 'P'; |
598 | 05ee37eb | balrog | pfl->cfi_table[0x32] = 'R'; |
599 | 05ee37eb | balrog | pfl->cfi_table[0x33] = 'I'; |
600 | 05ee37eb | balrog | |
601 | 05ee37eb | balrog | pfl->cfi_table[0x34] = '1'; |
602 | 05ee37eb | balrog | pfl->cfi_table[0x35] = '1'; |
603 | 05ee37eb | balrog | |
604 | 05ee37eb | balrog | pfl->cfi_table[0x36] = 0x00; |
605 | 05ee37eb | balrog | pfl->cfi_table[0x37] = 0x00; |
606 | 05ee37eb | balrog | pfl->cfi_table[0x38] = 0x00; |
607 | 05ee37eb | balrog | pfl->cfi_table[0x39] = 0x00; |
608 | 05ee37eb | balrog | |
609 | 05ee37eb | balrog | pfl->cfi_table[0x3a] = 0x00; |
610 | 05ee37eb | balrog | |
611 | 05ee37eb | balrog | pfl->cfi_table[0x3b] = 0x00; |
612 | 05ee37eb | balrog | pfl->cfi_table[0x3c] = 0x00; |
613 | 05ee37eb | balrog | |
614 | 05ee37eb | balrog | return pfl;
|
615 | 05ee37eb | balrog | } |